JPH08227384A - Numerical control device - Google Patents

Abstract

PURPOSE: To constitute a parity memory of a semiconductor storage device having the same capacity as a semiconductor storage device constituting a data memory. CONSTITUTION: This numerical control device is provided with a central processing unit(CPU) 1 for executing burst access, a data memory 2, a parity memory 3 constituted of a semiconductor storage device having the same capacity as a quotient obtained by dividing the number of bits of parities corresponding to data on n addresses of the memory 2 by an integer m (m<n) and storing all parities corresponding to data on one address of the memory 2 in one address, a memory controller 4 for receiving an address command from the CPU 1, generating an address to the memory 2 and generating an address storing parities corresponding to data accessed to the memory 2 in each burst access to the memory 3, a parity checking circuit 5, and a parity generating circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a numerical controller for performing a parity check when writing / reading data. In particular, the present invention relates to an improvement that allows a parity memory to be configured with a semiconductor memory device having the same capacity as a semiconductor memory device that configures a data memory.

[0002]

2. Description of the Related Art In order to improve the reliability of data handled by a numerical control device, it is often practiced to add a parity to each fixed amount of data and perform a parity check. For example, when one bit of parity is added to each 8-bit data, conventionally, a semiconductor memory device of 8-bit structure for storing 8-bit data and a semiconductor memory device of 1-bit structure for storing 1-bit parity are used. In the case of a combination, for example, a memory having a data width of 32 bits, four combinations are used to configure the memory. Also, data and parity are stored together 9
A memory may be configured using a plurality of sets of bit-structured semiconductor memory devices or 18-bit-structured semiconductor memory devices.

Since the numerical control device according to the prior art accesses only one address during one read / write operation, even if the bit configuration of the semiconductor memory device forming the parity memory is increased, the data memory Was limited by the number of bits of parity corresponding to the data at one address.

[0004]

By the way, the storage capacity of a semiconductor memory device is 256 kbits, 1 Mbits, 4 Mbits, which is quadrupled with each new generation of development, and the cost per bit has been reduced. , This trend is expected to continue in the future. In the numerical control device according to the related art, the semiconductor memory device having an 8-bit structure and the semiconductor memory device having a 1-bit structure have different developed generations. Therefore, when used in combination, there is concern about supply by a memory maker. Further, the memory of 9-bit configuration or the memory of 18-bit configuration may not be supplied when the next generation of the semiconductor memory device is developed.

In addition, in a 32-bit width memory in which 1 bit of parity is added for every 8 bits of data, a semiconductor memory device of 8 bits is used as the parity memory, and 8 bits called from the parity memory by one access. 4 bits are used as parity, and the remaining 4
The method of leaving bits unused is too inefficient and ridiculous.

An object of the present invention is to solve these problems, and to provide a numerical control device which can fully use the semiconductor memory devices constituting the parity memory and uses only the semiconductor memory devices of the same capacity. As a result, the storage device can be configured only by the memories of the same generation.

[0007]

The above object is to provide a plurality of consecutive n addresses (n is 2) when reading / writing data.
A central processing unit (1) for performing burst access for continuously accessing (the above integers), a data memory (2),
The number of bits of parity corresponding to the data at n addresses of this data memory (2) is an integer m (m is less than n)
And the parity corresponding to the data at one address of the data memory (2) is constituted by a semiconductor memory device in which the number of bits at one address is the same as the quotient divided by the integer m. All of which receive an address command from the central processing unit (1) and a parity memory (3) which is designed to be stored in one address, issue an address to the data memory (2), and perform one burst. A memory controller (4) for issuing to the parity memory (3) an address storing a parity corresponding to data accessed in the data memory (2) for each access; (2)
And a parity check circuit (5) for issuing a pass / fail judgment result to the central processing unit (1) and a parity check circuit (5) for writing data to the central processor. And a parity generating circuit (6) for receiving data issued to the data memory (2), generating / accumulating parity, and issuing to the parity memory (3). It

A latch circuit for temporarily holding the parity issued by the parity memory (3) and issuing the parity held when reading the data corresponding to the held parity to the parity check circuit (5). (7)
Is convenient because it is not necessary to issue an address to the parity memory (3) every time the memory controller (4) issues an address to the data memory (2).

[0009]

Since the numerical control device according to the prior art accesses only one address during one read / write operation, the number of bits of the parity corresponding to one address in the data memory 2 and the parity memory 3 can be reduced. The number of bits in one address was the same.

The numerical controller according to the present invention utilizes the fact that the central processing unit 1 performs burst access in which n (n is an integer of 2 or more) consecutive addresses are successively accessed during reading and writing. And the number of bits of parity corresponding to the data at the n addresses of the data memory 2,
The total number of bits in the m addresses (m is less than n) of the parity memory 3 is the same, and when the memory controller 4 receives an address command from the central processing unit 1, it issues an address to the data memory 2, The address in which the parity corresponding to the data accessed in the data memory 2 is stored is issued to the parity memory 3 every burst access.

Since the burst access is used, the bit configuration of the semiconductor memory device forming the parity memory does not have to be limited by the number of bits of the parity corresponding to the data at one address of the data memory 2. It can be increased in proportion to the number of addresses accessed in one burst access. Therefore, a semiconductor device having the same capacity as the semiconductor device forming the data memory 2 can be used. Further, in one burst access, all the bits called from the parity memory are effectively used as the parity, and the total storage capacity of the data memory is multiplied by the number of data bits corresponding to 1 bit of parity. In this case, the semiconductor memory device that constitutes the parity memory can be used without exhaustion.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A numerical controller according to an embodiment of the present invention will be described in more detail below with reference to the drawings.

FIG. 1 is a block diagram of a numerical controller according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a central processing unit, which is capable of performing a burst access in which a plurality of consecutive n addresses (n is an integer of 2 or more) are continuously accessed when reading / writing data. Reference numeral 2 is a data memory, 3 is a parity memory, and 4 is a memory controller which receives an address signal from the central processing unit 1 and issues an address signal to the data memory 2 and the parity memory 3.

Reference numeral 7 is a latch circuit for temporarily holding the parity read from the parity memory 3. 5 is a parity check circuit, the central processing unit 1 is a data memory 2
When reading the data stored in the memory, it is determined whether the data stored in the data memory 2 and the parity stored in the parity memory 3 and input via the latch circuit match, and the determination result is displayed. It has a function of transmitting it to the central processing unit 1.

Reference numeral 6 denotes a parity generation circuit, which receives the data output from the central processing unit 1 when the central processing unit 1 writes the data in the data memory 2, and determines which of the data is even or odd from the data. It has a function of generating the parity of and writing it in the parity memory 3.

FIG. 2 is a diagram showing an example of the configuration of a data memory 2 having a 32-bit width and a parity memory 3 having a 1-bit parity for each 8-bit data. In FIG. 2, the memory UU
Each of D, memory UMD, memory LMD and memory LLD is an 8-bit semiconductor memory device. The parity memory 3 is composed of an 8-bit semiconductor memory device having the same capacity as the semiconductor memory device forming the data memory 2.

The parity for the data in the memory UUD located at address 0H of data memory 2 is stored in bit 7 of address 0H of parity memory 3. Similarly, the parity for the data of the memory UMD is stored in the bit 6 of the address 0H, the parity for the data of the memory LMD is stored in the bit 5 of the address 0H, and the parity for the data of the memory LLD is stored in the bit 4 of the address 0H. In addition, the memory UUD at address 1H of the data memory 2,
Parities for the data in the memory UMD, the memory LMD and the memory LLD are stored in bits 3 to 0 of the address 0H of the parity memory 3. Similarly, the parity for the data at addresses 2H and 3H of the data memory 2 is stored in bits 7 to 0 of the address 1H of the parity memory 3.

Parities corresponding to all the data in the four semiconductor memory devices, the memory UUD, the memory UMD, and the memory LMD and the memory LLD are just half the capacity of one parity memory 3. Therefore, in actuality, four more 8-bit semiconductor memory devices having the same capacity are prepared, and a total of 8
The data memory 2 is composed of individual semiconductor memory devices.

FIG. 3 shows another example of the configuration of the 32-bit width data memory 2 and the parity memory 3 having 1-bit parity for 8-bit data. In FIG. 3, the memory
UUUD, memory UUMD, memory UMUD, memory UMMD, memory LM
The MD, the memory LMLD, the memory LLMD, and the memory LLLD are semiconductor memory devices each having a 4-bit configuration. The parity memory 3 is composed of an 8-bit semiconductor memory device having the same capacity as the semiconductor memory device forming the data memory 2.

Parity for a total of 8 bits of data of the memory UUUD and the memory UUMD at the address 0H of the data memory 2 is stored in the bit 7 of the address 0H of the parity memory 3. Similarly, the parity for the data of the memory UMUD and the memory UMMD is the bit 6 of the address 0H,
The parity for the data of the memory LMMD and the memory LMLD is stored in the bit 5 of the address 0H, and the parity for the data of the memory LLMD and the memory LLLD is stored in the bit 4 of the address 0H. Further, the memory UUUD, the memory UUMD, the memory UMUD, the memory UMM at the address 1H of the data memory 2
D, memory LMMD, memory LMLD, memory LLMD and memory LLLD
Parities for the data and are stored in bits 3 to 0 of the address 0H of the parity memory 3. Similarly, the parity for the data at addresses 2H and 3H of the data memory 2 is stored in bits 7 to 0 of the address 1H of the parity memory 3.

In the structure shown in FIG. 3, the number of parities corresponding to the data of the eight semiconductor memory devices of 4-bit structure which constitute the data memory is the same as that of one 8-bit semiconductor memory which constitutes the parity memory 3. It matches the number of bits of the device, and there is no excess or deficiency in the capacity of the parity memory 3.

Next, the central processing unit 1 performs burst access to issue four consecutive addresses to the memory controller 4 at a time, and the data is read from the data memory 2 and the parity memory 3 having the configuration shown in FIG. 2 or 3. Shows a time chart for reading and writing.

See FIG. 4 FIG. 4 is an example of a time chart for reading data. In FIG. 4, a and c are address signals issued to the data memory 2 and the parity memory 3 by the memory controller 4 receiving the address signal from the central processing unit 1, respectively, and are shown in the figure. Addresses are accessed sequentially. b and d are the data memory 2
And a read signal to the parity memory 3, the data is read from the data memory 2 of the address being accessed at the time of rising of the read signal, and the parity is read from the parity memory 3. e indicates the timing of latching the parity read by the latch circuit 7.

32 at address 0H of data memory 2
When the bit data is read, this data and the parity from bit 7 to bit 4 of the parity read from the address 0H of the parity memory 3 are sent to the parity check circuit (not shown in the figure). And
Of the parities read from the address 0H of the parity memory 3, the parities from bit 3 to bit 0 are temporarily held in the latch circuit 7. Next, when the 32-bit data at the address 1H of the data memory 2 is read, this data and the parity from the bit 3 to the bit 0 of the address 0H of the parity memory 3 held in the latch circuit 7 are checked for parity. Sent to the circuit (not shown). The parity from bit 7 to bit 0 read from the address 1H of the parity memory 3 is once held in the latch circuit 7. Subsequently, when the 32-bit data at the address 2H of the data memory 2 is read, this data and the parity from the bit 7 to the bit 4 of the address 1H of the parity memory 3 held in the latch circuit 7 are checked for parity. Sent to the circuit (not shown). Finally, when the 32-bit data at the address 3H of the data memory 2 is read, this data and the parity from the bit 3 to the bit 0 of the address 1H of the parity memory 3 held in the latch circuit 7 are checked for parity. Sent to the circuit (not shown). As described above, one burst read access is completed.

When the burst read access starts from address 1H of the data memory, addresses 2H, 3H, which are consecutive addresses of the data memory,
The address 0H is sequentially accessed to complete one burst read access. At this time, access to the parity memory 3 is carried out at address 0H and address 1H, and the latch circuit 7 sends the necessary parity to the parity check circuit 5 at that timing among the read parities, and holds the others once, and then the required timing. Parity check circuit 5
You can send it to.

As in this example, the memory controller 4
It is not necessary to access the parity memory each time the data memory 2 is accessed, and the address in which the parity corresponding to the data accessed to the data memory 2 is stored is issued to the parity memory 3 every burst access. do it. For example, the timing of accessing the address 1H of the parity memory may be the timing of accessing the address 2H of the data memory instead of the timing of accessing the address 1H of the data memory.

See FIG. 5 FIG. 5 is another example of a time chart for reading data. In FIG. 5, a, b, c and d are the same signals as in FIG. In the example of FIG. 5, the parity memory 3 is accessed every time the data memory 2 is accessed by accessing the address where the parity corresponding to the data in the data memory 2 is stored. Therefore, in the case of this example, the latch circuit 7 of FIG. 1 is unnecessary. That is, the 32-bit data at address 0H of data memory 2 and the parity from bit 7 to bit 4 at address 0H of parity memory 3 are sent to the parity check circuit (not shown). Next, the data memory 2
The 32-bit data at address 1H and the parity from bit 3 to bit 0 at address 0H of parity memory 3 are sent to the parity check circuit (not shown in the figure). Subsequently, the 32-bit data at the address 2H of the data memory 2 and the parity memory 3
The parity from bit 7 to bit 4 at the address 1H is sent to the parity check circuit (not shown in the figure). Finally, the 32-bit data at address 3H of data memory 2 and the parity from bit 3 to bit 0 at address 1H of parity memory 3 are sent to the parity check circuit (not shown in the figure), One burst read access is completed.

FIG. 6 is an example of a time chart when writing data. 6, a and c are the same as in FIG. 4, and are address signals issued to the data memory 2 and the parity memory 3, and the addresses shown in the figure are sequentially accessed. f and g are write signals to the data memory 2 and the parity memory 3, respectively, and data is written to the data memory 2 at the address accessed at the rising edge of the write signal and parity is written to the parity memory 3.

The data memory 2 has addresses 0H, 1H, 2
H, 3H are sequentially accessed to complete one burst write access. Address 0H of data memory 2,
While 1H is being accessed, the parity memory 3 is being accessed at address 0H. In the parity generation circuit 6,
While the address 0H of the data memory 2 is being accessed, the parity up to bit 7 or the rabbit 4 of the address 0H of the parity memory 3 is generated and held once, and while the address 1H of the data memory 2 is being accessed. , The parity of the bit 0 or the bit 0 of the address 0H of the parity memory 3 is generated and is integrated with the held bits 7 to 4, and the address 0 of the parity memory 3 is generated.
Write to H (not shown). Similarly, the parity of the address 1H is generated, and when the address 1H of the parity memory 3 is being accessed, the parity is written to the address 1H (not shown in the figure).

Although the embodiment has been described above, the data width of one address in the data memory is not limited to 32 bits, and the data bit to which the parity is added is not limited to 8 bits. Furthermore, the bit configuration of the semiconductor memory device forming the data memory 2 and the parity memory 3 and the read / write timing are not limited to those in the embodiment.

[0031]

As described above, according to the numerical control device of the present invention, the central processing unit capable of burst access and the parity required for the data accessed in one burst access access the data memory. The parity is matched with the total number of bits of the parity memory stored in the addresses less than the number of times, and the parity corresponding to the data accessed in one burst access is configured to be accessed. Therefore, the semiconductor memory device having the same capacity and the same generation as the data memory can be efficiently used for the parity memory, and there is no fear in supplying the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a block diagram of a numerical control device according to an embodiment of the present invention.

FIG. 2 is an example of a configuration diagram of a data memory and a parity memory according to the present invention.

FIG. 3 is another example of a configuration diagram of a data memory and a parity memory according to the present invention.

FIG. 4 is an example of a time chart at the time of reading of the numerical control device according to the present invention.

FIG. 5 is another example of a time chart at the time of reading of the numerical control device according to the present invention.

FIG. 6 is another example of a time chart at the time of writing of the numerical control device according to the present invention.

[Explanation of symbols]

 1 central processing unit 2 data memory 3 parity memory 4 memory controller 5 parity check circuit 6 parity generation circuit 7 latch circuit

Claims (2)

[Claims] 1. A central processing unit (1) for performing burst access for continuously accessing a plurality of consecutive n addresses (n is an integer of 2 or more) at the time of reading / writing data, and a data memory (2). ) And the number of bits of parity corresponding to data at n addresses of the data memory (2) can be divided by an integer m (m is less than n), and the number of bits at one address is an integer m. The semiconductor memory device is the same as the quotient divided by
A parity memory (3) in which all of the parities corresponding to data at one address of the data memory (2) are stored at one address; and an address command from the central processing unit (1), A memory controller which issues an address to the data memory (2) and issues an address storing a parity corresponding to data accessed in the data memory (2) to the parity memory (3) at each burst access. (4) and a parity check circuit for collating the data issued by the data memory (2) with the parity issued by the parity memory (3) at the time of data reading, and issuing a pass / fail judgment result to the central processing unit (1). (5) and at the time of data writing, the central processing unit (1) receives the data issued to the data memory (2), Generate a Thi
A numerical control device comprising a parity generation circuit (6) for accumulating and issuing to the parity memory (3). 2. A latch circuit (7) for temporarily holding the parity issued by the parity memory (3) and issuing the parity held when reading the data corresponding to the held parity to the parity check circuit (5). The numerical control device according to claim 1, further comprising: