JPH08221359A - Digital filter circuit - Google Patents

Abstract

PURPOSE: To simplify the circuit constitution of a digital filter circuit by providing a play mode computing cycle in one frame and computing a play mode by using a digital filter. CONSTITUTION: The left or right specification in LR selection signal is changed according to the specification of a play mode setting signal during a play mode setting period by an LR selection control circuit 210 and data are read from a RAM 40 according to the changed left or right specification. The data is multiplied by a coefficient drived based on the play mode setting signal in a multiplier and the results are cumulatively added to each other in a cumulative adder to obtain the data for a left or right output channel. Since the play mode computing cycle is provided and the output of the left or right channel is changed according to the play mode in the LR selection signal setting circuit 210 of simple constitution, the need of providing a play mode setting circuit whose circuit scale is large is eliminated and thus, the entire chip area is reduced as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter circuit used in a digital audio device such as a CD player, and in particular, it controls a left channel and a right channel of an audio output called a play mode used therein. It is about circuits.

[0002]

2. Description of the Related Art In digital audio equipment such as CD players, audio data is interpolated by oversampling using a digital filter circuit in order to improve sound quality. On a CD or the like, the sound of the left and right channels is recorded in stereo by time division.
Using the digital filter circuit, these left and right voices
After oversampling to 8 times, output to the left and right channels of the speaker. There is a case where the relationship between the left and right input channel sounds and the output channel is changed (hereinafter referred to as play mode). FIG. 2 is a diagram showing a play mode used in a digital audio device. As shown in FIG. 2, the play mode includes MUTE for the left channel output and right channel output.
(Silence), left channel input sound output, right channel input sound output, (left channel input sound + right channel input sound) / 2, and there are 16 combinations in total. 3 is a block diagram of a conventional digital filter circuit, and FIG. 4 is a block diagram of the play mode setting circuit in FIG.

As shown in FIG. 3, the input sounds of the left and right channels pass through the interface circuit 1 and the left channel latch circuit 11- of the play mode circuit 10 shown in FIG.
1, after being latched by the right channel latch circuit 11-2, the adders 12-1, 12-2 and the selector 13-
1, 13-2 are input. Adders 12-1, 12-2
By adding the input sound of the left and right channels, and × 1
/ 2 is calculated and output to the selectors 13-1 and 13-2. According to the play mode input from the play mode setting terminal by the selectors 13-1 and 13-2,
It outputs to RAM40 in FIG. The RAM 40 causes the control signal from the RAM control circuit 30 based on the LR selection signal output from the timing circuit 20 to read the left and right channels in order and output them to the latch circuit 50. The multiplier 90 multiplies the output of the latch circuit 50 by the filter coefficient or the coefficient of the attenuator 60 (the output level is adjusted when the interpolation data is output). The output of the multiplier 90 is cumulatively added a predetermined number of times by the adder 100 and the cumulative adders of the latch circuits 110 and 120 under the control of the timing circuit 20 to create interpolation data, and the RAM 60 (or digital filter) is created. Output to a D / A converter or the like).

[0004]

However, the conventional digital filter circuit has the following problems. In the conventional digital filter circuit, the play mode circuit shown in FIG. 4 exists as a single block, and the circuit itself is large and the whole chip has a large area, which is a problem.

[0005]

In order to solve the above-mentioned problems, the second invention outputs left and right only for a predetermined play mode setting period of one frame period which is a sampling period of audio data inputted from the outside. Based on the play mode setting signal that specifies how to output to the channel, the left or right or the left or right of the LR selection signal is repeatedly specified for each cycle of the clock. And an LR selection signal control circuit for changing. further,
First storage means for outputting audio data of the left or right input channel or data subjected to digital filter operation based on the audio data in accordance with designation of the left or right of the output signal of the LR selection signal control circuit; A second storage means for storing a coefficient based on the play mode setting signal and a third storage means for storing a filter coefficient are provided.
Further, during the play mode operation cycle corresponding to the play mode setting period, the audio data output from the first storage means is multiplied by the coefficient stored in the second storage means to perform digital In the period of the filter operation cycle, a multiplier for multiplying the audio data output from the first storage means and the filter coefficient stored in the third storage means, a first latch circuit, and A second latch circuit that latches the output of the first latch circuit; and an adder that adds the output of the second latch circuit and the output of the multiplier and outputs the result to the first latch circuit. A cumulative adder and a timing circuit for controlling the number of cumulative additions of the cumulative adder and outputting the cumulative addition to the first storage means at a predetermined timing.

[0006]

According to the second invention, as described above,
Since the filter is configured, the left or right channel is designated by the LR selection signal, for example, with left as "L" and right as "H", with the clock as one cycle in the order of left and right.
In the digital filter operation cycle, the data of the left or right input channel is read out by the first storage means on the basis of the LR selection signal, and the digital filter operation is performed. On the other hand, the LR selection control circuit changes the left or right designation of the LR selection signal according to the designation of the play mode setting signal during the play mode setting period. The data is read from the first storage unit according to the changed left or right designation. The multiplier multiplies this data by the coefficient based on the play mode setting signal, and the data cumulatively added by the cumulative adder is used as the data of the left or right output channel. Therefore, the above problem can be solved.

[0007]

1 is a block diagram showing a digital filter circuit according to an embodiment of the present invention. Elements common to those of the conventional digital filter circuit of FIG. 3 are designated by common reference numerals. The difference between the digital filter circuit of the present embodiment and the conventional digital filter circuit is that when the interpolation data created by the digital filter is output as the digital filter (or the interpolation data is output by the attenuator, (When writing to RAM to use as input data when setting and setting as the output of the digital filter)
That is, the period of 2 cycles or 4 cycles in one frame is provided as the play mode period. Then, by providing the LR selection signal control circuit 210, the designation of the left or right of the LR selection signal in the play mode period is changed according to the play mode setting signal, and based on the output of the LR selection signal control circuit. , The interpolation data of the left or right input channel from the RAM 40 is output to the latch circuit 50.

As shown in FIG. 1, this digital filter circuit includes an interface circuit 1 and a timing circuit 2.
00, LR selection signal control circuit 210, RAM control circuit 3
0, RAM 40, latch circuit 50, ROM control circuit 25
0, coefficient ROM 260, attenuator 240, multiplier 9
0, adder 100, latch circuit 110, latch circuit 12
It is composed of 0s. The interface circuit 1 includes a predetermined sampling frequency (eg,
Input sounds of the left and right input channels sampled at a sampling frequency of 44.1 kHz (hereinafter, this sampling period is referred to as one frame) are input. The system clock CLK is input to the timing circuit 200. The LR selection signal control circuit 210 receives the LR selection signal LR and the play mode latch signal PLAT from the timing circuit 200, the play mode setting signal Pi from the play mode setting terminal, and the system clock C.
LK is input. The RAM control circuit 30 has an address for R / W of audio data from the timing circuit 200,
Also, a signal for timing control is input, and the system clock CLK is input.

The RAM 40 has an interface circuit 1
A signal for inputting voice data of the input channel and interpolation data S120 from the latch 120, an address control signal or the like from the RAM control circuit 30, and an instruction to read the data of the left or right channel from the LR selection signal control circuit 210. S210 is input and the system clock CLK is input. The ROM control circuit 250 receives a control signal from the timing circuit 200 and a system clock CLK. The coefficient ROM 260 stores a filter coefficient and a coefficient based on a play mode setting signal, and a control signal such as an address of the coefficient is input from the ROM control circuit 250. The attenuator 240 is
Outputs a coefficient that adjusts the output level of speakers, etc. The audio data of the left or right channel from the RAM 40 is input to the latch circuit 50. In the multiplier 90,
Data is input from the latch circuit 50, and the attenuator 2
The output level is input from 40, the coefficient S260 is input from the coefficient ROM 260, and the system clock CLK is input. The adder 100 and the latch circuits 110 and 120 form a cumulative adder. The output S90 of the multiplier 90 is input to the B terminal of the adder 100, and the output S120 of the latch circuit 120 is input to the A terminal. Latch circuit 1
The output S100 of the adder 100 is input to 10, and the system clock CLK is input. Latch circuit 120
The output of the latch circuit 110 is input to. The latch circuit 120 outputs the audio data to the D / A converter or the RAM 40.

First Embodiment FIG. 5 is a circuit diagram of an LR selection signal control circuit 210 in FIG. 1 showing a first embodiment of the present invention. The LR selection signal control circuit 100 includes analog switches (hereinafter, referred to as SW) 211-1 to 211-4, data flip-flops (hereinafter, referred to as DFF) 212-1 and 212-2, and EX.
It is composed of an OR gate 213. SW211
-1, 211-3 are turned on when the gate input is "L". SW111-2 and 211-4 are turned on when the gate input is "H". Play mode latch signal PLAT
Are input to the gates of SW211-1 to 211-4. The play mode setting signal P0 is input to the source of SW211-2, and P1 is input to the source of SW211-4. The LR selection control signal LR is supplied to the EXOR gate 21.
Input to 3. System clock CLK is DFF2
The clock is input to 12-1 and 212-2. SW21
The source of 1-1 is connected to the ground potential. SW21
The drains of 1-1 and 211-2 are connected to the D terminal of DFF212-1. SW21 is the Q terminal of DFF2
Connected to 1-3 sources. SW211-3, 2
The drain of 11-4 is connected to the D terminal of DFF212-2. The Q terminal of DFF212-2 is EXOR
It is connected to the input terminal of the gate 213.

FIG. 6 is a time chart showing the operation of the digital filter circuit of FIG. 1, FIG. 7 is a diagram showing the relationship between the frame and the operation cycle, and FIG. 8 is the L of FIG.
7 is a time chart showing the operation of the R selection signal control circuit. The operation of the digital filter circuit according to the first embodiment of the present invention will be described below with reference to these drawings. The digital filter circuit uses the RAM4 during one frame.
The output data of 0 and the digital filter coefficient of the coefficient ROM are multiplied by the multiplier 90 and cumulatively added by the cumulative adder of the adder 100 and the latch circuits 110 and 120 to create the interpolation data, and the RAM 40 Output to. Hereinafter, the operation of this digital filter circuit will be referred to as a digital filter operation cycle. First, R is generated by the precharge signal S30 output from the RAM control circuit 30.
The AM 40 is precharged, and the voice data S40 is output from the RAM 40. The audio data S40 is latched by the latch circuit 50 by the system clock CLK, and the data S50 is output to the multiplier 90. ROM
The counter (cycle number in one frame) output from the timing circuit 200 is decoded by the control circuit 250 by the decoder, and the coefficient S260 of the digital filter corresponding to the cycle number is stored in the coefficient ROM 26.
Output from 0 to the multiplier 90.

The multiplier 90 allows the data S50 and the coefficient S to be obtained.
It is multiplied by 260 and the data S90 is output to the B terminal of the adder 100. The cumulative adder 100 cumulatively adds the audio data S90 of the left and right channels to create interpolation data. This interpolation data is written in the RAM 40 so as to be the output of the digital filter. Then, as shown in FIG. 7, based on the play mode setting signals P0 and P1, the left or right designation of the LR selection signal LR is changed only for the play mode setting period of two cycles, and the interpolation data in the RAM 40 is changed. Readout is controlled according to the output channel, and this readout data is
The multiplier 90 and the cumulative adder of the digital filter circuit perform an operation (hereinafter, referred to as a play mode operation cycle) and output it. 8A to 8D are timing charts of the LR selection signal control circuit 210 of FIG. FIG.
(A) shows P0 = “H” and P1 = “L”, (b) shows P0 = “L” and P1 = “L”, and (c) shows P0 = “L”. H ", P1 =" H ", same figure (d)
Is when P0 = “L” and P1 = “H”. In FIG. 8, 2C from the fall of the system clock CLK immediately after the play mode latch signal PLAT rises.
The LK period is the play mode setting period. Also, FIG.
In the description, the play mode calculation cycle is described as being equal to the play mode setting period, but strictly speaking, by the time the voice input data is calculated by the multiplier 90, R
The play mode operation cycle is delayed by the operation of reading data from the AM 40 and latching the data by the latch circuit 50.

Hereinafter, referring to FIGS. 8 (a) to 8 (d),
LR selection signal control circuit 2 for setting play mode
The operation of 10 will be described. (A) When P0 = “H” and P1 = “L” As shown in FIG. 8A, the PLAT output from the timing circuit 200 plays with the digital filter operation cycle (PLAT is “L”). Mode operation cycle (P
LAT distinguishes from "H"). PLAT is "L"
At the time of, SW211-1 and SW211-3 in FIG. 5 are turned on, and SW211-2 and 211-4 are turned off. Therefore, “L” is input to the EXOR gate 213 from the Q terminal of the DFF 212-2. EX
The OR gate 213 outputs the LR selection signal LR as it is. On the other hand, when PLAT becomes "H", SW211
-2, 211-4 are turned on, and SW211-1,
211-3 is turned off. Therefore, P0 and P1 are DF at the falling edge of the clock signal CLK.
It is latched by F212-1, 212-2, respectively. D
The P1 latched by the FF 222-2 is input to the EXOR gate 213. At this timing, since the LR selection signal LR is "L" and P1 = "L", the EXOR gate 213 outputs "L". At the next timing, PLAT is “L”, so SW
212-2 and SW211-4 are turned on, and DFF
P0 latched by 212-1 is DFF212-2
Latched on. At this timing, the LR selection signal L
Since R is "H" and P0 = "H", E
“L” is output from the XOR gate 213. EXOR
The signal S210 output from the gate 213 represents the left channel when "L" and the right channel when "H". Therefore, in the play mode operation cycle, the signal S210 is output in the order of "L" and "L". The RAM 40 is instructed to read the left channel data and the left channel data. As a result, the play mode is set so that the left channel outputs the left channel data and the right channel outputs the left channel data. That is, the play mode function of outputting only the left channel data from both the left and right channels can be realized.

(B) When P0 = "L" and P1 = "L" When P0 = "L" and P1 = "L", PLAT becomes "H" as shown in FIG. 8B. When P1 = "L"
And the LR selection signal LR (“L”) between the EXOR gate 21
3 is input, “L” is output, and then P0 =
"L" and LR selection control signal LR ("H") are EXO
It is input to the R gate 213 and “H” is output. Therefore, the left channel is output at the timing when the left channel is originally output, and the right channel is output at the timing when the right channel is output. This is a normal stereo output. (C) When P0 = "H" and P1 = "H" When P0 = "H" and P1 = "H", when PLAT becomes "H" as shown in FIG. 8C, P1 = "H"
And the LR selection signal LR (“L”) between the EXOR gate 21
3 is input, “H” is output, and then P0 =
“H” and the LR selection signal LR (“H”) are input to the EXOR gate 213, and “L” is output. Therefore, the right channel is output at the timing when the left channel is originally output, and the left channel is output at the timing when the right channel is output. This is a stereo output in which the left channel and the right channel are switched and output.

(D) When P0 = "L" and P1 = "H" When P0 = "L" and P1 = "H", PLAT becomes "H" as shown in FIG. 8 (d). When P1 = "H"
And the LR selection signal LR (“L”) between the EXOR gate 21
3 is input, “H” is output, and then P0 =
“L” and the LR selection signal LR (“H”) are input to the EXOR gate 213, and “H” is output. Therefore, the right channel is output at the timing when the left channel is originally output, and the right channel is output at the timing when the right channel is output. This is a function of outputting the right channel data from both the left and right channels. From the RAM 40, the LR selection signal control circuit 21
When the output signal S210 of 0 is "L", the left channel data S40 is output, and when it is "H", the right channel data S40 is output. The data S40 is latched by the latch circuit 50, and the data S50 is output to the multiplier 90. The multiplier 90 multiplies the coefficient (output level) output from the attenuator 240 by the data S50 to add the adder 100 and the latch circuits 110 and 120.
Through, the data is output. At this time, the adder 100
Timing circuit 2 so that 0 is input to the A terminal of
Controlled from 00. As described above, the interpolation data of the input channel designated by the play mode setting signals P0 and P1 is output to the output channel.

As described above, in the first embodiment, the play mode setting signals P0 and P1 and the play mode operation cycle are provided, and the LR selection signal setting circuit 21 having a simple structure is provided.
Since the outputs of the left and right channels are changed by 0 according to the play mode, it is not necessary to provide the play mode setting circuit 10 having a large circuit scale, and as a result, the entire chip area is reduced. The function of the play mode of the first embodiment is a total of four combinations of the left channel output for the left channel or the right channel and the right channel output for the right channel, and the left channel.

Second Embodiment FIG. 9 is a block diagram of an LR selection signal control circuit showing a second embodiment of the present invention. As shown in the figure, the LR selection signal control circuit includes SWs 221-1 to 221-8, inverters 222-1 and 222-2, and DFFs 223-1 to 223.
-4 and an EXOR gate 224.
SW221-1,221-3,221-5,221-7
Turns on when the gate is "L". SW221-2, 2
The gates of 21-4, 226-1 and 221-8 are "H".
It turns on at. The play mode latch signal PLAT is S
It is input to the gates of W221-1 to 221-8. P2
Is input to the inverter 222-1. The source of the SW 221-1 is connected to the output side of the inverter 222-1. P0 is input to the source of SW221-4. P3 is input to the source of SW221-6. P1 is input to the inverter 222-2. The output side of the inverter 222-2 is SW221.
It is connected to the -8 source. SW221-1, 22
The drain of 1-2 is connected to the D terminal of DFF223-1. SW221 is connected to the Q terminal of DFF223-1.
-3 sources are connected. SW221-3, 22
The drain of 1-4 is connected to the D terminal of DFF223-2. The Q terminal of DFF223-2 is SW221.
It is connected to the -5 source. SW221-5, 22
The drain of 1-6 is connected to the D terminal of DFF223-3. The Q terminal of DFF223-3 is SW221.
It is connected to the -7 source. SW221-7, 22
The drain of 1-8 is connected to the D terminal of DFF223-4. The Q terminal of the DFF 223-4 is connected to one input terminal of the EXOR gate 224. DFF
The clock signal CLK is input to the clock terminals of 223-1 to 223-4. The LR selection signal LR is input to the other input terminal of the EXOR gate 224.

FIG. 10 is a block diagram of a part of the ROM control circuit in FIG. This circuit includes a NOR gate 251-
1, 251-2, inverters 252-1, 252-2,
AND gates 253-1, 253-2, 254-1, 2
54-2, 256-1, 256-2, OR gate 255
, 255-2. P0 and P1 are input to the NOR gate 251-1. P2 and P3 are input to the NOR gate 251-2. The NOR gate 251 is provided in the inverters 252-1 and 252-2.
-1, 251-2 outputs are respectively input. AND
The output of the NOR gate 251-1 and the reverse phase signal of the LR selection signal are input to the gate 253-1. The AND gate 253-2 outputs to the output of the inverter 252-1 and L.
An opposite phase signal of the R selection signal is input. AND gate 25
The output of the NOR gate 251-2 and the LR selection signal are input to 4-1. The output of the inverter 252-2 and the LR selection signal are input to the AND gate 254-2. The OR gate 255-1 has an AND gate 253-.
The outputs of 1, 254-1 are input, and the OR gate 255-
The output of the AND gates 253-2 and 254-2 is input to 2. The output of the OR gate 255-1 and the output of the decoder are input to the AND gate 256-1. A
The output of the OR gate 255-2 and the output of the decoder are input to the ND gate 256-2. AND for coefficient 0
The output of the gate 256-1 is input, and the coefficient 1/2 has A
The output of the ND gate 256-2 is input.

FIG. 11 is a diagram showing a list of the play mode functions of FIG. 12A and 12B are time charts of FIG. 9, and in FIG. 12A, P0 = “L” and P1 =
When "H", P2 = "H", and P3 = "H", the same figure (b)
Is P0 = “L”, P1 = “L”, P2 = “L”, P3 =
It is the time of "H". Hereinafter, referring to these figures, FIG.
The operation of is explained. SW2 when PLAT is "L"
21-1, 221-3, 221-5, 221-7 are in the ON state, SW 221-2, 221-4, 221-6, 22
1-8 is turned off, "L" is input to the EXOR gate 224, and the LR selection signal LR is directly output from the EXOR gate 224. When PLAT becomes "H", SW221-2, 221-4, 221-6, 2
21-8 is in the ON state, SW 221-1, 221-3, 2
21-5 and 221-7 are turned off, and the DFF 223-1 is generated at the falling timing of the clock signal CLK.
Is an inverted signal of P2, and DFF223-2 is P0, DFF2
23-3 latches P3 and DFF 223-4 latches the inverted signal of P1 respectively, and the inverted signal of P1 is first input to the EXO gate 224. After that, when PLAT becomes “L”, SWs 221-1, 221-3, 221-5, 22
1-7 is on, SW 221-2, 221-4, 22
1-6 and 221-8 are turned off, and the DFF 223-
The contents latched by 3, 223-2 and 223-1 are sequentially input to the EXOR gate 224 at the falling timing of the clock signal CLK.

First, an inverted signal of P1, P3, P0, P2
When the inverted signal of LR is input to the EXOR gate 224, the LR selection signal LR is “L”, “H”,
It becomes "L" and "H". (A) P0 = "L", P1 = "H", P2 = "H",
When P3 = “H” As shown in FIG. 11A, the signal S2 is output from the EXOR gate 224 in the order of “L”, “L”, “L”, “H”.
10 is output to RAM40. From the RAM 40, in the play mode operation cycle, according to the signal S210,
Interpolation data is output in the order of left, left, left, right. The latch circuit 50 latches the output S40 of the RAM 40 in accordance with the system clock CLK and outputs the data S50.
Is output to the multiplier 90. NOR gate 25 in FIG.
"L" is output from 1-1, and "L" is output from the NOR gate 251-2. When the LR selection signal is “L”, that is, when the left channel is operated, the OR gate 255-1 outputs
"L", "H" is output from the OR gate 255-2. When the LR selection signal is "H", that is, when the right channel operation is performed, "L" is output from the OR gate 255-1 and "H" is output from the OR gate 255-2. further,
This output can be accessed to the ROM 260 only when the output of the decoder in the ROM 260 indicating the play mode operation cycle is "H". Therefore, P0 = "L",
When P1 = "H", P2 = "H", and P3 = "H", the ROM 260 is in the order of coefficients 1/2, 1/2, 1/2, 1/2.
Will be accessed. The multiplier 90 multiplies this coefficient 1/2 by the data S50 and adds the result to the adder 100.
Output to. In the adder 100, the output of the multiplier 90 and the data of the cycle two cycles before latched by the latch circuit 120 are cumulatively added and output to the latch circuits 110 and 120. As a result, the cumulative addition output S120 from the latch circuit 120 is left × 1/2, left × 1/2, left × 1,
It is output in the order of (left + right) / 2. The data of the two left and right channels behind is controlled by the timing circuit 200 and is output as D / as the output of the digital filter.
It is output to the A converter (or to the RAM 40 if the level needs to be adjusted by the attenuator 240).

(B) P0 = "L", P1 = "L", P
When 2 = “L” and P3 = “H” As shown in FIG. 12B, from the EXOR gate 224, the RAM is arranged in the order of “H”, “L”, “L”, “L”.
The signal S210 is output to 40. In the RAM 40, in the play mode operation cycle, according to S210,
The signals are output in the order of right, left, left, left, and the output S40 of the RAM 40 is latched by the latch circuit 5 according to the clock CLK.
It latches at 0 and outputs the data S50 to the multiplier 90. From the OR gate 251-1 in FIG.
The level is output, and the OR gate 251-2 outputs
The "L" level is output. When the LR selection signal is "L", that is, when the left channel is operated, "H" is output from the OR gate 255-1 and "L" is output from the OR gate 255-2. When the LR selection signal is "H", that is, when the right channel is operated, the OR gate 255-1 outputs "L",
"H" is output from the OR gate 255-2. Therefore, the ROM 260 in the order of coefficients 0, 1/2, 0, 1/2
Is accessed and the coefficient S260 is output.

The output S50 of the latch circuit 50 and the RAM 26
The coefficient S260 from 0 is multiplied by the multiplier 90, and cumulative addition is performed using the adder 100 and the latch circuits 110 and 120. Cumulative addition result S12 from the latch circuit 50
0 is output in the order of 0, left × 1/2, 0, left × 1.
Of these, 0 and left × 1 are output to the D / A converter (or to the RAM 40 if the level needs to be adjusted by the attenuator 240) as the output of the digital filter. As a result, MUTE is applied to the left channel, and the left channel data is output to the D / A converter and the like for the right channel. For other combinations of P0 to P3, the outputs of the left and right channels are controlled in the same manner, as shown in FIG.
The play mode function shown in FIG. As described above, according to the second embodiment, there are the same advantages as the first embodiment, and 16 combinations of outputs of the left and right channels can be realized by combining P0 to P3. it can.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the second embodiment, the coefficient 0 or 1/2 is output from the ROM 260 according to P0 to P3, but a structure for outputting the coefficient 0 or 1/2 without using the coefficient ROM 60 will be described. (A) Access method of coefficient 1/2 A method of making data by multiplying the coefficient 1/2 without using the coefficient ROM 260 will be described. FIG. 13 is a configuration diagram showing a modified example of the RAM in FIG. D when calculating the digital filter
RAM41 and RAM44 latched by FF42 and 44
The output of each is shifted to the lower order by 1 bit by the adder 46, that is, halved and added to the RAM.
40 outputs. Next, in the play mode calculation, 2c
The h selector 45 selects the input B. That is, the adder 4
The B input of 6 becomes ALL "0", and the output of the RAM 40 is obtained by halving the output of the RAM 41. The voice for play mode calculation is controlled by the RAM control circuit 30 so that it is stored only in the RAM 41. Further, which of the A input and the B input is output to the selector 45 is determined by the play mode operation cycle, which is controlled by the timing circuit 200. Which of the data stored in the RAMs 41 and 43 is output is controlled by the RAM control signal from the RAM control circuit 30 and the output from the timing circuit 200. In this way, coefficient 1 is used without using coefficient ROM 260.
It becomes possible to do / 2.

(B) Access Method for Coefficient 0 A method for accessing coefficient 0 without using the coefficient ROM 260 will be described. FIG. 14 is a configuration diagram showing a modified example of the attenuator in FIG. The coefficient of the coefficient ROM 260 is input to the multiplier 90 only during the digital filter operation, and the coefficient from the attenuator 240 is input to the multiplier 90 only during the play mode operation. In the attenuator 240, when P0 = P1 = 0,
"H" is output from the AND gate 241-2 to set the counter value of the counter 242-1 for the left channel to ALL.
When “0” and P2 = P3 = 0, the AND gate 241-
"H" is output from 1 and the counter 2 for the right channel
The counter value of 42-2 is set to ALL "0", and the coefficient "0" is accessed. As a result, the coefficient 0 can be accessed. Thus, from RAM 40, coefficient 1
Data multiplied by / 2, coefficient 0 by attenuator 240
Is output, there is an advantage that the output level can be adjusted by the attenuator 240 in the play mode operation cycle. (2) Although the LR selection signal control circuits shown in FIGS. 5 and 9 are given, any circuit may be used as long as the output result is equal to these. (3) In the second embodiment, the output S2 shown in FIG.
10 and the coefficient S260, the sum of the multiplication of the audio data S210 and the coefficient S260 in the first period and the second period in the first to fourth periods in which the play mode setting period is continuous is the play mode setting. It suffices if it matches the play mode set by the signal. (4) The play mode operation cycle is performed after all digital filter operations are completed. Therefore, when performing oversampling, it is necessary to provide as many play mode operation cycles as the number of interpolations. For example, if the interpolated data of the sampling frequency f _s to 8f _s is required eight play mode operation cycle in one frame.

[0025]

As described in detail above, according to the first to fifth inventions, a play mode operation cycle in one frame is provided, and in this play mode operation cycle, a play mode is used by using a digital filter. Since the calculation is performed, the circuit configuration of the digital filter circuit becomes simple.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital filter circuit showing an embodiment of the present invention.

FIG. 2 is a diagram showing a play mode function.

FIG. 3 is a configuration diagram of a conventional digital filter circuit.

4 is a configuration diagram of a break mode setting circuit in FIG.

FIG. 5 is a configuration diagram of an LR selection signal control circuit showing a first embodiment of the present invention.

FIG. 6 is a time chart of FIG.

FIG. 7 is a diagram showing a relationship between frames and operation cycles.

FIG. 8 is a time chart of FIG.

FIG. 9 is a configuration diagram of an LR selection signal control circuit showing a second embodiment of the present invention.

10 is a diagram showing a partial configuration of a ROM control circuit in FIG.

FIG. 11 is a diagram showing a list of play mode functions of FIG. 9;

FIG. 12 is a time chart of FIG.

FIG. 13 is a diagram showing a modification of the RAM in FIG.

FIG. 14 is a configuration diagram showing a modified example of the attenuator in FIG.

[Explanation of symbols]

30 RAM control circuit 30 40 RAM 50, 110, 120 Latch circuit 90 Multiplier 100 Adder 200 Timing circuit 210 LR selection control circuit 240 Attenuator 250 ROM control circuit 260 Coefficient ROM

Claims (5)

[Claims] 1. A play mode setting signal for designating how to output to left and right output channels only during a predetermined play mode setting period of one frame period which is a sampling period of audio data inputted from the outside. An LR selection signal control circuit that changes the designation of the left or right of the LR selection signal that is repeatedly designated left / right or right / left based on one clock cycle, and the output of the LR selection signal control circuit Outputs audio data of left or right input channel or data subjected to digital filter operation according to designation of left or right of signal
Storage means, a second storage means for storing a filter coefficient, the audio data output from the first storage means and the second storage means during a digital filter operation cycle.
Of the second latch circuit, a first latch circuit, a second latch circuit that latches the output of the first latch circuit, and a multiplier that multiplies with the filter coefficient stored in the storage means. A cumulative adder having an adder for adding the output and the output of the multiplier to output to the first latch circuit, and controlling the cumulative addition number of the cumulative adder at a predetermined timing. And a timing circuit for outputting to the first storage means. 2. A play mode setting signal for designating how to output to the left and right output channels only during a predetermined play mode setting period of one frame period which is a sampling period of audio data input from the outside. An LR selection signal control circuit that changes the designation of the left or right of the LR selection signal that is repeatedly designated left / right or right / left based on one clock cycle, and the output of the LR selection signal control circuit Outputs audio data of left or right input channel or data subjected to digital filter operation according to designation of left or right of signal
Second storage means for storing a coefficient based on the play mode setting signal
Storage means, a third storage means for storing a filter coefficient, and a voice data output from the first storage means and the second storage means during a play mode operation cycle corresponding to a play mode setting period. Multiplying with the coefficient stored in the storage means, the audio data output from the first storage means and the filter coefficient stored in the third storage means during the digital filter operation cycle. A multiplier for performing multiplication, a first latch circuit, a second latch circuit for latching the output of the first latch circuit, an output of the second latch circuit and an output of the multiplier are added. A cumulative adder having an adder for outputting to the first latch circuit, and a cumulative addition number of the cumulative adder is controlled to output to the first storage means at a predetermined timing. A digital filter circuit comprising an imming circuit. 3. The play mode setting signal specifies that the outputs to the left and right output channels are digitally filtered data based on the data of the left or right input channel, and the predetermined mode is set. The digital filter circuit according to claim 1 or 2, wherein a play mode setting period is two cycles of the clock. 4. The play mode setting signal outputs the outputs to the left and right output channels, respectively.
E, the LR selection signal, which is designated as the average of the data digitally filtered based on the left or right input channel data or the digitally filtered data based on the left and right input channel data The control circuit sets the predetermined play mode setting period to four cycles of the clock that are continuous in the first to fourth periods, and the designation of the left or right of the first to fourth periods is the first to the first period. No. 4 of the left or right designation, the data output from the first storage means is multiplied by the coefficient 0 or 1/2 based on the play mode setting signal. The sum of the results of the third period and the sum of the results of the second and fourth periods match the designation of the left and right output channels designated by the play mode setting signal, respectively. Features and Digital filter circuit according to claim 2, wherein that. 5. A play mode setting signal for designating how to output to the left and right output channels only during a predetermined play mode setting period of one frame period which is a sampling period of audio data input from the outside. An LR selection signal control circuit that changes the designation of the left or right of the LR selection signal that is repeatedly designated left / right or right / left based on one clock cycle, and the output of the LR selection signal control circuit Outputs audio data of left or right input channel or data subjected to digital filter operation according to designation of left or right of signal
Output means for storing a filter coefficient, a second storage means for storing a filter coefficient, an attenuator for specifying an output level, and a play mode operation cycle corresponding to a play mode setting period. The audio data output from the first storage means and the audio data output from the second storage means are stored during the digital filter operation cycle. A multiplier that multiplies with the filter coefficient, a first latch circuit, a second latch circuit that latches the output of the first latch circuit, an output of the second latch circuit, and an output of the multiplier And a cumulative adder having an adder for outputting to the first latch circuit, and the number of cumulative additions of the cumulative adder is controlled to control a predetermined time. And a timing circuit for outputting the first play means to the first storage means, and the LR setting control circuit sets the predetermined play mode setting period to four cycles of the clock for consecutive first to fourth periods, The designation of the left or right of the first to fourth periods is based on the designation of the left or right of the first to fourth periods based on the data output from the first storage means and the play mode setting signal. Based coefficient 0 or 1
The sum of the results of the first and the third periods and the sum of the results of the second and the fourth periods with respect to the result of multiplying by 1/2, respectively, left and right specified by the play mode setting signal. Of the output channel, the first storage means is configured to output 1/2 times the data according to the left or right designation in the play mode setting period, the LR setting control circuit A digital filter circuit characterized in that a coefficient 0 corresponding to each of the first to fourth periods set by is output from an attenuator.