JPS62159400A - Sound recording and reproducing device - Google Patents

Abstract

PURPOSE:To easily perform the sound recording of sound data in plural groups without making a device oversize, or increasing a cost substantially, by storing in order and alternately the sound data in inputted plural groups. CONSTITUTION:The clock signal of constant frequency outputted from an oscillator 21 is frequency divided at a division and timing circuit 22, and is given to a control part 23 as a timing signal. The control part 23 generates and outputs a sound recording and reproducing signal (R'/P), and every kind of control clock signals, phi1, phi2, and phi3 from the timing signal corresponding to the operations of a sound recording/reproduction changing over switch SW1, and a sound recording and reproduction starting switch SW2. In other words, at every operation of the switch SW1, the level of the signal R'/P is switched from L (low) to H (high), or from H to L. Also, when the other switch SW2 is operated at the L level of the signal R'/R, the clock signals phi2 and phi3 are outputted, then the multiplex sound recording can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording/playback device capable of recording and reproducing audio in a storage means such as a semiconductor storage device.

[Conventional technology]

FIG. 4 shows the circuit configuration of a conventional wristwatch incorporating this type of recording/playback device. In the figure, under normal conditions, oscillator 1
The clock signal outputted from is divided into a predetermined frequency by a frequency division and timing circuit 2, and predetermined time data is created by a clock circuit 3 based on this frequency-divided signal and displayed on a display unit 4. .

On the other hand, when recording, switch SW I""" SW 2
The control unit 5 is activated by the operation of ``, and the audio data input from the ficro is passed through the amplifier 7, the bypass filter 8, and the low-pass filter 9 to the A/D conversion and encoding circuit 1.
0, where it is encoded with the sampling period.

This encoded audio data is sequentially written into a predetermined area of the RAM 12 designated by the address section 11.

When playing audio data recorded in this way,
The control unit 5 is activated by operating the switches SW + to SW:l.
operates, and RAM1 specified by the address section 11
The audio data is sequentially read out from the predetermined area of D/A
It is converted into analog by the conversion circuit 13 and then passed through the low-pass filter 1.
4 and an amplifier 15, the signal is output as audio from the speaker 16.

[Problems with conventional technology]

The conventional device described above is for recording only one system of audio data, and is not capable of recording multiple systems of audio data, such as through audio multiplex recording, for example. If a conventional device were to perform such recording, it would have to be equipped with at least 2Mi of recording and playback circuitry as shown in Figure 4, and in particular, it would have to be equipped with an encoding circuit and storage means such as RAM. Providing a large number of devices is not desirable because it increases the size of the entire device and significantly increases costs.

[Purpose of the invention]

In view of the above conventional problems, the present invention provides a recording/playback device capable of recording multiple systems of audio data, such as audio multiplex recording, for example, without increasing the size or cost of the device. The purpose is to

[Key points of the invention]

In order to achieve the above object, the present invention is capable of sequentially and alternately storing input audio data of a plurality of systems in a storage means.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This circuit is capable of multiplexed (stereo) recording and multiplexed (stereo) playback of audio.

In the figure, a clock signal of a constant frequency output from an oscillator 21 is frequency-divided by a frequency division and timing circuit 22 and provided to a control section 23 as a timing signal.

The control unit 23 outputs a recording/playback (π/P) signal and various control clock signals φ1, φ2, Create and output φ3. That is, each time the switch SW1 is operated once, the level of the R/P signal is switched from L (low) to H (high) or from H to L. Also, R
When the /P signal is at L level, the other switch SW2
When is operated, clock signals φ2 and φ3 are output, and multiple recording of audio is performed as described later. On the other hand, when the π/P signal is at H level, switch SW2
When is operated, clock signals φ1 and φ2 are output, and multiple reproduction of audio is performed as described later.

First, a description will be given of the time of recording, that is, the time when the switch SWz is operated when the π/P signal is at the L level.

In this case, each voice on the right side and the left side is transmitted to the microphones 24a and 24
b, and are input to transfer gates 28a, 2 via amplifiers 25a, 25b, bypass filters 26a, 26b1, and low-pass filters 27a, 27b, respectively.
Sent to 8b. Here, when the π/P signal is at L level, it is inverted by the inverter circuit G, and the AND circuit G4
Since the H signal is input to one input terminal of , the least significant bit AO (L or H) of the address section 31 to which 1 is sequentially added by the clock signal φ2 passes through the AND circuit G4 and is input to the transfer gate 28a. It is also applied to the other transfer gate 28b via the inverter circuit G2. Therefore, the transfer gates 28a and 28b are connected to the Hl of the lowest bit node A0.
It turns on alternately depending on L. Then, the right and left audio data output from the low-pass filters 27a and 27b alternately pass through transfer gates 28a and 28b, and are respectively input to the A/D conversion and encoding circuit 2.
9 performs A/D conversion and encoding based on the clock signal φ3, and sends it to the RAM 30. Note that the above encoding may be performed by, for example, PCM or the like, and of course other encoding methods may be used.

The right and left audio data sent to the RAM 30 are sent to the address (Ao A+) specified in the address section 31 mentioned above.
According to A2...), they will be written down one by one in turn. The relationship between the written data and the address is
As shown in the figure. As is clear from the figure, data on the left side is sequentially written where the least significant bit 80 of the address is rOJ (L), while the least significant bit 1-AO is rl
Right data is sequentially written to J (H).

Next, a description will be given of when the switch S W Z is operated during reproduction, that is, when the R/P signal is at the H level.

At this time, since the π/P signal (H signal) is input to one input terminal of the AND circuit G, the least significant bit A0 of the address section 31 passes through the AND circuit G and launch circuit 32a. It is also sent to the clock terminal of the other latch circuit 32b via the inverter circuit G3. Therefore, the right and left audio data alternately stored in the RAM 30 are sequentially read out based on the address designation of the address section 31, and the high
, L are alternately latched by the latch circuits 32a532b. The audio data on the right side and the left side, once lied in this way, are transferred to the D/A conversion circuits 33a and 33b, respectively.
After being D/A converted based on the clock signal φ, the low-pass filters 34a, 34b and the amplifier 3
The right and left sounds are outputted by the speakers 35a and 35b via the speakers 5a and 35b.

In the manner described above, multiple recording and multiple playback of audio becomes possible. Since this embodiment uses only one RAM, it can be easily incorporated into small electronic devices such as wristwatches.

Next, another embodiment of the present invention is shown in FIG. What is the circuit in the same diagram? ! I overdubbed the voices of several phone calls and recorded one of them.
This allows one channel to be selected for playback.

In the figure, an oscillator 41 and a frequency division and timing circuit 42 are similar to those in FIG. 1, and output a predetermined timing signal to a control section 43. switch SW1,
Similarly to FIG. 1, SW2 is a switch for switching between recording and playback, and a switch for starting recording and playback, respectively, and switch SW2 is a switch for selecting a channel during playback. The control unit 43 controls these switches SW3 and SW2.
, SW, outputs the aforementioned R/P signal, various control clock signals φ1 to φ, and multichannel control signal S. This multi-channel control signal S is sent to a multiplexer circuit 52 (described later) during recording and playback.
This is a signal for controlling the operation of the

First, when recording, that is, when switch SW2 is operated when the R/P signal is at L level, multiple telephones T,
, . . . , T are picked up by the pickup 44a, respectively.
..., 44n, and the amplifier 45a1...
, 45n1 bypass filters 46a, . . . , 46n and low-pass filters 47a, .

The signals are sent to sphere gates 48a, . . . , 48n.

Here, since the R/P signal is at the L level, it is inverted by the inverter circuit G and becomes an H signal, and the AND circuit G7a
,..., G7n is opened. Then, the multiplexer circuit 52, based on the address contents of the address section 51,
Transfer gates 48a, . . . , 48 are sequentially time-divisionally transferred via the AND circuits Q, a, . . . , G=n.
We will open up n. Therefore, the low-pass filter 47a,
. . , 47n sequentially and alternately pass through transfer gates 48a, . , are sent to the RAM 50. Each piece of audio data alternately sent to the RAM 50 is sequentially and alternately stored in accordance with the address designated by the address section 51.

Next, at the time of playback, that is, when the switch SWz is operated while the R/P signal is at the H level, the audio data of multiple systems (multiple channels) alternately stored in the RAM 50 are transferred to the address of the address section 51. They are read out sequentially based on the specifications. At this time, the AND circuit G is output from the multiplexer 53 in synchronization with the timing at which data of one channel designated in advance by the switch SW3 is read out.

Since the H signal is sent to the clock terminal of the latch circuit 52 via the latch circuit 52, only the data of the designated channel is sequentially latched by the latch circuit 53.

The audio data once latched in this way is transferred to the D/A
After being D/A converted by the conversion circuit 54, the signal is output as audio from the speaker 57 via the low-pass filter 55 and amplifier 56.

Note that if it is desired to output audio data of another channel, the desired channel may be specified by sequentially operating the switches SW. With such a function, even when a plurality of telephones are frequently used, the contents of the telephones can be easily checked later.

〔Effect of the invention〕

As explained above, according to the present invention, by sequentially and alternately storing input audio data of multiple systems, audio data of multiple systems can be stored without increasing the size of the device or requiring a large cost amplifier. Data can now be easily recorded.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 1 is a diagram showing an example of audio data storage in the RAM, FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of a conventional recording/playback device. be. 23...Control unit, 24a, 24b-...Microphone, 25a, 25b...Amplifier, 29...A/D conversion and encoding circuit, 30...R
AM1 31...Address section, 33a, 33b=...D/A conversion circuit, 34a, 34b
...Low pass filter, 35a, 35b...Amplifier, 36a, 36b...-Speaker, 43...Control unit, 44a1..., 44n...Pickup, 45a
1..., 45n... Amplifier, 49... A/D conversion and encoding circuit, 50... Address section, 52... Multiplexer circuit, 54... D/A conversion circuit, 55. ...Low pass filter, 56...Amplifier, 57...Speaker. Patent Applicant: Casio Computer Co., Ltd. Address: A3 A2 At 400 0
o 0 001. 01 o 1 2nd Day Prisoner

Claims (1)

[Scope of Claims] An input means for inputting a plurality of systems of audio data, a storage means for sequentially and alternately storing the plurality of systems of audio data input by the input means, and audio data stored in the storage means. A recording and reproducing device comprising an output means for outputting.