JPH0821627B2 - Multilayer wiring compaction method for integrated circuits - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring compaction method for an integrated circuit, which performs compaction of a layout in which multilayer wiring is performed.

[Prior Art] An integrated circuit, particularly a large scale integrated circuit (LSI) is usually manufactured through the following processes.

(B) Create LSI functional specifications based on system specifications,
A functional design process that designs the behavioral details.

(B) A logic design process for designing with a focus on the connection relationship between gates, that is, the logic circuit configuration.

(C) A device design process that designs the shape and electrical characteristics of the transformer used based on the LSI manufacturing conditions.

(D) A circuit design process in which the basic logic unit used in the logic cell library and the transistor library obtained by device design are combined to design a basic circuit or circuit cell, and the performance is predicted by a circuit simulator.

(E) Layout design process for creating LSI mask patterns.

(F) A manufacturing process for manufacturing an LSI using the mask pattern of the layout design process.

Of these processes, the layout design process is the most important design process in LSI design, and the layout of logic gates is calculated using the connection information obtained by logic design and the logic cell library prepared by circuit design. This is the process of wiring.

In this layout design process, in order to improve the chip yield, it is required to make the chip area as small as possible while complying with the constraints (design rules) due to manufacturing conditions. As a method for reducing this area, the so-called compaction method is widely used. It is used.

Conventional compaction methods can be roughly classified into the following three.

(A) The vertical relationship of the initial layout is orthogonal to each other 2
A directed graph method that uses a directed graph in the X and Y directions, which are directions, and performs compaction within the range allowed by the design rules to obtain minimized layout data.

(B) A compression ridge method in which a band-shaped portion in which a space having a constant width is completely crossed in the initial layout is found and the band-shaped portion is compacted.

(C) A virtual grid method in which data in the X direction or Y direction of the initial layout are arranged in order and registered in the virtual grids, and the respective grids are approached within the range of the design rule.

Among these compaction methods, the compression ridge method of (b) is algorithmically clear and easy to design, but the bending of the wiring (jog), which is the point of reduction, is determined by the shear line (the line that breaks the strip-shaped portion). There is a drawback that it ends up.

Also, in the virtual grid method of (c),
Although the processing time is fast, there is a drawback that the order of the grids cannot be changed and the areas that should be compacted are not compacted. Therefore, in view of the present ability and future possibility, the directed graph method of (a) is regarded as the most promising at present.

On the other hand, a technique for forming a plurality of wiring layers to reduce the chip area and performing multilayer wiring to substantially reduce the wiring area is also indispensable especially for very large scale integrated circuits (VLSI). In, the compaction using the directed graph method is also examined.

In the conventional compaction method using a directed graph in multi-layer wiring, first, data of functional blocks and wiring in the initial layout and design rules are read and converted into an internal representation to create a data file. As data,
For each functional block, the coordinates of each block and each vertex are input, and for the wiring, the wiring layer and end point coordinates are input. Then, initial parameters such as a compaction direction are set, and line segment data is created based on the compaction direction.

Then, based on this line segment data, a directed graph is created according to the following rules.

(I) When each line segment data is a node and wiring or a functional block corresponding to a certain two nodes are adjacent on the same X coordinate, a branch is provided between these nodes. In addition, in this operation, the size and the minimum interval determined by the design rule shall be taken into consideration.

(Ii) Branches are also provided between the wiring blocks to be connected and the nodes corresponding to the wiring.

(Iii) The directions of the branches are determined from those having a large Y coordinate to those having a small Y coordinate, and are arbitrarily determined when the Y coordinates are the same.

(Iv) When the graphs created in (i) to (iii) have cycles, two wirings that intersect among the cycle-like nodes are obtained, and the wirings are divided into two to cancel the cycle. To do.

According to this rule, the functional block as shown in FIG.
If a directed graph in the OY direction of the initial layout in which the wirings A, B and the wirings l, j, m in the first layer and the wiring k in the second layer are arranged is created,
It becomes like the figure. In the figure, thick branches indicate branches whose distance between nodes is fixed, and thin branches indicate branches whose nodes are defined by design rules.

Then, in this directed graph, the nodes connected by thin branches are successively reduced to the lowest line (lower side of the figure) within the range allowed by the design rules.

The result of compaction in the OY direction is shown in FIG. 8 (B). In addition, FIG. 8 (A) shows the same figure as FIG. 6 (A) for comparison.

[Problems to be Solved by the Invention] However, some problems have occurred in the conventional multilayer wiring compaction method. As described above, the line segment data for performing compaction is created based on the layout data, but in the conventional layout data, the block name and the coordinates of the vertices are input to the functional block. Therefore, if line segment data is created based on this data and a directed graph is created, line segment data k and 2 corresponding to the functional block of the first layer are generated as shown in FIG.
There is a branch defined by the design rule between the line segment data e corresponding to the wiring of the layer.

Therefore, if compaction is performed using this directed graph, the line segment data k corresponding to the second layer wiring is obtained from the line segment data e corresponding to the first layer functional block as shown in FIG. 8B. The area on the functional block indicated by the alternate long and short dash line in the figure, which is not compacted but is originally compacted, exists as an ineffective area, resulting in a reduction in compaction efficiency.

Of course, if the layout data of the functional blocks and the wiring are input independently for each layer and the compaction is performed for each layer, the above-mentioned problem is solved, but in this case, the first layer and the second layer are compacted independently. Therefore, there is a problem that the relative positions of the first layer and the second layer are displaced.

The present invention has been made in view of the above conventional problems,
An object of the present invention is to provide a multilayer wiring compaction method for an integrated circuit capable of wiring a predetermined area on a functional block when performing compaction of the multilayer wiring in a multilayer wiring layout and improving the compaction efficiency. It is in.

[Means for Solving the Problem] In order to achieve the above object, the present invention provides reference coordinates common to each layer indicating the position of a functional block formed on a semiconductor chip and the functional block of each layer of a multilayer wiring layer. A layout data creation process for creating a file by inputting vertex coordinates representing the size of the functional block set in consideration of the wiring prohibited area and end point coordinates of the wiring connecting the functional blocks, and a layout data creation process created by this process. Based on the layout data, the line segment data creation process for creating the line segment data for the functional block from the reference coordinates and the vertex coordinates for each layer and the line segment data for the wiring, and for each layer created in this process Based on the line segment data, there is a branch defined by the design rule between the line segment data in the same layer, and A directed graph creation process that creates a directed graph with fixed distance branches between line segment data related to functional blocks in a layer
It has a compaction process that makes the layout of the functional blocks and wiring of all layers compact by using the directed graph created in this process, and sets the line segment data corresponding to the functional blocks for each layer. It is characterized by performing compaction.

[Operation] That is, the functional block is provided with reference coordinates indicating the position of the functional block and vertex coordinates of the vertices indicating the size of the functional block, and the layout data is created by setting the vertex coordinates for each layer. The line segment data corresponding to can be set for each layer.

Therefore, if a directed graph is created based on this line segment data, for example, the line segment data corresponding to the wiring of the second layer forms a branch in relation to the line segment data of the functional block of the second layer, and the line of the first layer is formed. It is compacted without being affected by minute data. On the other hand, since each line segment data of the functional block is the vertex coordinates based on one reference coordinate, the line segment data of the first layer and the second layer do not shift as a result of compaction, and the vertex coordinates of the second layer of the functional block do not shift. Is set to a desired value, the second layer wiring can pass over the wirable area of the functional block.

[Embodiment] A preferred embodiment of the multilayer wiring compaction method for an integrated circuit according to the present invention will be described below with reference to the drawings, taking as an example the case of performing the compaction of the two-layer wiring layout shown in FIG. FIG. 1 is a flowchart of the present embodiment. First, layout data creation process 10 creates layout data, which will be described later. Then, set initial parameters such as compaction direction (process 12),
Create line segment data (process 14). After that, a directed graph is created from the created line segment data and compaction is performed in two orthogonal directions (OX and OY) (process 16-
28), consisting of a series of processes for converting to CAD data (process 30).

FIG. 2 shows a data format of functional blocks in the layout creating process 10. As shown in the figure, for the functional blocks, a data file of the functional block name, the origin coordinates (reference coordinates) of the functional blocks, and the vertex coordinates (relative coordinates) of the functional blocks for each layer is created in advance. The origin coordinate is a coordinate indicating the position of the functional block, and is a value common to each layer for one functional block. On the other hand, the vertex coordinates are a value indicating the size of the functional block, and by setting this value for each layer, the size of one functional block in each layer can be set. In this embodiment, the function blocks A and B in the layout shown in FIG. 6 are set in consideration of the wiring prohibited areas in the function blocks A and B to create a file. On the other hand, regarding the wiring, the file was created by inputting the wiring layer and the end point coordinates as in the conventional case. FIG. 3 shows line segment data of a functional block created based on the layout data shown in FIG. In the figure, the solid line (a, d, e, f, i) represents the line segment data of the first layer, and the broken line (b, c, g, h) represents the line segment data of the second layer. The line segment data g is set in the block.

When a directed graph is created based on the line segment data of the functional block and the line segment data of the wiring, the line segment data k corresponding to the second layer wiring is between the line segment data g of the same second layer functional block. There are branches, and the first and second layers of functional blocks
A fixed distance branch is formed between the line segment data of the layer, and the result is the directed graph shown in FIG.

Then, when the compaction is performed based on this directed graph, each line segment data indicated by a, d, j, l, m, f, i is compacted as in the conventional case, but the line segment corresponding to the second layer wiring is The data k only has a branch defined by the design rule between the second-layer line segment data g of the functional block A and is compacted beyond the line segment data e of the functional block A.

The compaction result of this embodiment is shown in FIG.
The result of conversion into data is shown. Comparing with the conventional compaction result shown in FIG. 3A, it is understood that the wiring k of the second layer passes over the functional block A and the compaction is performed efficiently.

Although the case of the two-layer wiring is shown in this embodiment, it is needless to say that the present invention can be applied to the multi-layer wiring of two or more layers by setting the relative coordinates of the vertices of the functional block to three layers or four layers. Absent.

[Effects of the Invention] As described above, according to the present invention, when performing the compaction of the multi-layer wiring in the multi-layer wiring layout, the wiring can be provided even on the functional block, and the compaction efficiency can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart of an embodiment of a multilayer wiring compaction method for integrated circuits according to the present invention, and FIG. 2 is an illustration showing a format of layout data of functional blocks in the embodiment, FIG. 3 is an explanatory diagram of line segment data of functional blocks in the same embodiment, FIG. 4 is a directed graph diagram in the same embodiment, FIG. 5 is an explanatory diagram showing a layout after compaction, and FIG. 6 is an explanatory diagram of an initial layout. FIG. 7 is a directed graph diagram in the conventional multilayer wiring compaction method in the initial layout of FIG. 6, and FIG. 8 is an explanatory diagram of the compaction result by the conventional compaction method. 10 …… Layout data creation process 14,22 …… Line segment data creation process 16,24 …… Directed data creation process 18,26 …… Compaction process

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takaaki Takai, Inventor Takaaki Takai, 21 Mizozaki-cho, Saiin, Ukyo-ku, Kyoto, Japan (56) References JP 62-115740 (JP, A) JP 62 -274638 (JP, A) JP-A-57-113254 (JP, A) JP-A-2-89343 (JP, A)

Claims (1)

[Claims] 1. A size of the functional block set in consideration of a wiring prohibition area of the functional block for each layer of a multilayer wiring layer and reference coordinates common to each layer indicating a position of the functional block formed on a semiconductor chip. Based on the layout data created in this process, the layout data creation process that creates a file by inputting the vertex coordinates that represent the
Based on the line segment data creation process that creates line segment data related to functional blocks from the reference coordinates and vertex coordinates for each layer and line data related to wiring, and line segment data for each layer created in this process, A directed graph creation process for creating a directed graph having branches defined by design rules between line segment data in the same layer and fixed distances between line segment data relating to functional blocks of different layers, and this process The compaction process that collectively compacts the functional block and wiring layouts of all layers by using the directed graph created in step 1. is set, and the line segment data corresponding to the functional block is set for each layer for compaction. A multilayer wiring compaction method for integrated circuits, which is characterized by being performed.