JPH0821618B2 - Semiconductor substrate manufacturing method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor substrate having a buried dielectric layer formed therein.

[Prior art]

As a method for separating elements in a semiconductor integrated circuit, a method using a pn junction has been used for a long time, but in recent years, it has become impossible to cope with an increase in isolation capacitance and a reduction in element size with the sophistication of ICs.

A dielectric isolation method is promising as a new element isolation method replacing the above method. This is especially true when a high breakdown voltage element is included. For example, in a power IC that integrates an output stage power transistor and an IC that drives or controls it, it is necessary to electrically and reliably separate the power transistor and the drive or control IC part. In many cases, separation is insufficient, and the dielectric separation method is suitable.

[Problems to be solved by the invention]

However, the conventional dielectric isolation method has a problem that it is not easy to wrap a part of the element with the dielectric. In particular, in order to electrically separate the element region from the substrate region, it is necessary to embed a dielectric layer in the substrate, but the conventional dielectric embedding method has many problems.

For example, a method known as a polycrystal support structure dielectric isolation method (for example, described in "Practical Semiconductor Technology Patent Handbook", Hisaita Shimamoto et al., Science Forum 1986 p14) forms an element on the surface of a semiconductor substrate, and a lateral element is formed. After the separation, the semiconductor substrate is lapped from the back surface to expose the lower part of the element region, and a dielectric film such as an oxide film is formed here.
Although a polycrystalline silicon layer or the like to be used as a support is formed again, this method has many process restrictions, and the substrate tends to warp due to the difference in thermal expansion between polycrystalline silicon and single crystal silicon. There's a problem.

Further, as another example, an SOI method in which a polycrystalline or amorphous silicon film is formed on a dielectric layer formed on a single crystal substrate and the film is single crystallized by heat treatment, laser light, electron beam, or the like ( (For example, described in the above document)
However, this method has a problem in that an expensive device such as a laser or an electron beam is required, and the size, quality, shape, etc. of the single crystal to be formed are limited.

Further, as described in JP-A-61-115334, a groove and a cavity region are formed in a semiconductor substrate, and a portion surrounded by the cavity region and the groove is formed by filling the portion with an insulator. As described in JP-A-62-122143 and a method for forming an isolation region, a cavity region is formed by selectively etching the laminated lower epitaxial layer, and the cavity region is surrounded by the cavity region. There is a method of using a part as a separation area.

However, in the above-mentioned method, the method of supporting the portion directly above the cavity region serving as the isolation region is such that a part of the bottom portion thereof is connected to and supported by the semiconductor substrate. Then, in a later step, the supporting portion is thermally oxidized to be insulated, but it is difficult to accurately inspect the oxidation state of the portion inside the substrate by nondestructive inspection. Therefore, in order to inspect whether or not the above supporting portion is completely insulated, it is necessary to dismantle and inspect the portion of the isolation region directly above the cavity region, which greatly increases the inspection man-hour and the cost. there were.

The present invention has been made in order to solve the problems of the prior art as described above, and provides a method for manufacturing a semiconductor substrate that enables inexpensive manufacture of a semiconductor substrate having a highly reliable element isolation structure. The purpose is to do.

[Means for solving problems]

In order to achieve the above object, in the present invention, a cavity region is formed inside the semiconductor substrate through a hole or a groove that communicates with the surface of the semiconductor substrate, and a support in which the hole or groove is not provided in the surface portion of the semiconductor substrate. A step of forming so that the portion directly above the cavity region is supported by a portion, an oxidizing gas, a nitriding gas, a nitride film forming gas,
Supplying or injecting at least one of an oxide film forming solution and an organic polymer resin solution into the cavity region through the hole or groove; and heating in the above state to form a dielectric film on the surface of the cavity region. It is configured so as to include a step of forming and a step of insulating and isolating a portion directly above the cavity region from other portions by thermally oxidizing the supporting portion of the surface portion of the semiconductor substrate.

That is, in the present invention, the portion directly above the cavity region serving as the isolation region is supported by the surface portion of the semiconductor substrate (the portion where no groove or the like is provided), and the surface portion is thermally oxidized in a later step to be insulated and separated. It is configured as follows.

Example of Invention

(A) First Embodiment FIG. 1 is a sectional view showing a process of the first embodiment of the present invention.

In this embodiment, the semiconductor substrate is 0.3 Ω · cm.
The above n-type silicon substrate 1 is used.

First, in (a), the resistance of a predetermined region 2 including a portion which becomes a cavity region in the silicon substrate 1 and a portion 3 ′ which becomes a hole for selectively etching the predetermined region 2 in a later step have resistances thereof. Phosphorus is implanted by ion implantation or the like so as to be 0.015 Ω · cm or less.

Next, in (b), boron is implanted by ion implantation or the like into the surface layer portion of the region 2 of the phosphorus-implanted regions 2 and 3 ′, that is, the portion 4 directly above the portion 5 ′ that becomes the cavity region. , So that the resistance value is 0.3 Ω · cm or more.

Instead of the step (b), the silicon substrate 1
Boron is injected into the entire main surface of the and its resistance value is 0.3Ω ・ cm
After making the above, phosphorus may be injected into the portion 3'to be the hole so that the resistance value becomes 0.015 Ω · cm or less.

According to the latter, the concentration near the main surface of the silicon substrate 1 is high in the portions other than 4, but the impurity concentration is averaged in the wide portion.

Next, in (c), in the above step, only phosphorus is injected at a high concentration so that the resistance value is 0.015 Ω · cm or less, that is, the above-mentioned portion 3'to be the hole and the cavity region. The portion 5'is etched to form the hole 3 and the cavity region 5. It should be noted that the portion 4 directly above the cavity region 5 has holes 3
Is connected to the semiconductor substrate 1 at a portion where is not provided (portion 10 or 11 in FIGS. 2 and 3 described later), and is supported by the portion.

By using electrolytic etching using 5% HF as an etching solution as the above-mentioned etching method, it is possible to selectively etch a portion having a resistance value of 0.015 Ω · cm or less in which only phosphorus is introduced at a high concentration.

In the step (c), the holes 3 are patterned by resist using a photo process, and reactive ion etching (RI) using a Cl-based, F-based, or Cl-F-based gas is performed.
It may be formed by dry etching such as E). At that time, it is not necessary to control the impurity concentration for forming the holes 3.

Next, in (d), the oxide film 6 is formed on the surface of the cavity region 5 by heating in a dry oxygen atmosphere at about 1000 ° C. while supplying oxygen from the hole 3 to the cavity region 5. At that time, an oxide film is also formed on a portion other than the cavity region, that is, on the main surface of the substrate.

Next, in (e), an unnecessary portion of the formed oxide film, that is, a portion of the main surface of the substrate that is to be an element forming region or the like is photo-patterned and is etched with, for example, an ammonium fluoride solution. And remove.

Instead of (e) above, a nitride film is selectively formed in a predetermined portion (region for forming the element) before the oxidation in (d) so that an oxide film is not formed in that portion. May be.

Further, the portion 4 has a high concentration of phosphorus or boron implanted in the steps (a) and (b), and therefore, in order to use it as an element formation region, the concentration of phosphorus and boron as impurities is high in the element performance. However, in such a case, as shown in (f), the epitaxial film 7 is formed on the surface of the silicon substrate 1 at a predetermined concentration and a predetermined thickness, and this portion is used as an element formation region. Good.

The element isolation structure of the epitaxial film 7 is as follows.
As shown in (g), the hole 3 is formed again by etching.

That is, the portion 8 is an isolation region insulated from the surrounding portion 9.

Further, in consideration of prevention of disconnection of wiring, enhancement of mechanical strength of the structure, etc., the hole 3 may be filled with SiO ₂ , Si ₃ N ₄ or the like by CVD or the like.

Further, in the above (d), a nitride film may be formed instead of forming the oxide film 6. As the formation method,
There are a method in which a nitriding gas such as ammonia is heated to 1100 to 1200 ° C., an ion nitriding method in which a high frequency glow discharge or a DC bias is applied, a plasma CVD method using ammonia, dichlorosilane, etc., a method by LPCVD and the like.

Next, FIGS. 2 and 3 are plan views of an embodiment of the element isolation structure formed as described above. In FIGS. 2 and 3, a portion 8 is an isolation region, and an insulating portion 10 is formed as necessary, or a high-concentration impurity is injected into the portion 11 shown by a broken line to insulate the surrounding portion, Can be insulated and separated from the portion 9 of FIG.

As a method of forming the insulating portions 10 and 11, for example,
When the insulating film 6 is SiO ₂ , it depends on the thickness dimension of the epitaxial films 7 and 4, but when it is thick, the 10 part is selectively etched by using the Si ₃ N ₄ film as a mask. It is thinned to about 1 to 2 μm, exposed to an oxidizing gas atmosphere and thermally oxidized at about 1000 to 1200 ° C., and SiO ₂ is formed only on that portion so that it is connected to the oxide film 6 already formed. Completely isolate the isolation region 8 from the surroundings.

In addition, according to the method of the present invention, the shape of the separation region 8 can be any shape. Therefore, it goes without saying that various shapes other than those illustrated in FIGS. 2 and 3 are possible.

Further, in the present embodiment, the case where the selective etching by electro chemical etching by n-n + is used is exemplified, but the method of performing by n + -p, n-p +, p + -p is also applicable.

(B) Second Embodiment Next, FIG. 4 is a process drawing of a second embodiment of the present invention.

Also in this embodiment, as the semiconductor substrate, the first
The n-type silicon substrate 1 of 0.3 Ω · cm or more is used as in the above embodiment.

First, in (a), ion implantation is performed so as to have a resistance of 0.015 Ω · cm or less in a portion 15 ′ to be a cavity region and a portion 13 ′ to be a hole for selectively etching the portion in a later step. And so on.

Next, in (b), an n-type epitaxial film 12 of 0.3 Ω · cm or more is formed on the main surface of the substrate.

Next, in (c), phosphorus is injected by ion implantation or the like into the upper portion of the hole portion 13 ′ in the epitaxial film 12 so that the resistance is 0.015 Ω · cm or less, and the hole portion 13 ″ is formed. To form.

Next, in (d), the above-mentioned holes 13 'and
Etch the part 15 'that becomes the cavity area through 13 ",
A hole 13 and a cavity region 15 are formed. The etching method is the same as in the first embodiment. Therefore, in the structure of FIG. 4, the cavity region 15 is formed inside the silicon substrate 1 and surrounded by the silicon substrate 1 and the epitaxial film 12.

Thereafter, as in the first embodiment, an oxide film 16 or a nitride film is formed on the surface of the cavity region 15 and unnecessary portions are removed. In addition, (e) of FIG. 4 corresponds to (d) of FIG.
(F) corresponds to (e), respectively.

In (f), among the above epitaxial films 12,
The portion insulated from the surrounding portion 19 by the hole 13 becomes the separation region 18.

In this case as well, the plan views shown in FIGS. 2 and 3 are examples.

The second embodiment shown in FIG. 4 is basically different from the first embodiment shown in FIG. 1 in that the isolation region 18 for forming an element is set to a predetermined size before the formation of the cavity region 15. It is formed by depositing an epitaxial film whose concentration is controlled. Other points, for example, the etching method, the flattening of the hole 13, the complete separation of the separation region 18, and the like are the same as those in the first embodiment.

(C) Third Embodiment In this embodiment, an oxide film is formed by using an oxidizing solution when forming the oxide film 6 in the step (d) of the first embodiment shown in FIG. Are formed.

As the above-mentioned oxidizing solution, for example, a coating liquid OCD (trade name, known as spin-on glass for forming a SiO ₂ film)
Represented by Tokyo Ohka Kogyo Co., Ltd. and Si (OR) _4.
A solution obtained by dissolving Si alkoxide in an organic solvent such as ethanol and adding water for hydrolysis and an acid or a base, if necessary, is used.

The former, for example, those wt% of Si is 5.9, the latter, such as, for example, ethyl silicate _{Si (OC 2 H 5) 4} 1mol water (H ₂ O) 500cm ³ hydrochloric acid (HCl) 0.02 mol of ethanol 300 cm ³ Use the one with solution distribution. The mixed solution is refluxed at 90 ° C. for 120 minutes for homogenization before use.

The method of forming the oxide film 6 is as follows in (d) of FIG.
First, a solution for forming a SiO ₂ film is injected into the cavity region 5 through the hole 3 and spun so that the solution evenly wets the surface in the cavity region 5.

Depending on the shape and size of the holes 3, it may be preferable to add a solvent to dilute the solution before performing the injection operation. In that case, the solution is injected and pre-cured by low temperature heating, and the resin solution injection and low temperature heating are repeated as many times as necessary.

 After the injection, heat treatment is performed under the following conditions as an example.

In the case of OCD: 150 ° C. for 30 minutes in N ₂ ventilation, then 1000 ° C. for 30 minutes In the case of Si alkoxide solution: 120 ° C. for 30 minutes in N ₂ ventilation, then 1000 ° C. for 60 minutes. An oxide film 6 (SiO ₂ film) is formed on the inner surface and the like.

In the case of Si alkoxide solution, the reaction of Si (OC ₂ H ₅ ) ₄ + 4H ₂ O → Si (OH) ₄ + 4C ₂ H ₅ OH
It occurs during baking at 120 ℃ and is hydrolyzed to Si (OH)
It is presumed that a gel film composed of ₄ is formed, and further heat treatment causes a reaction of Si (OH) ₄ → SiO ₂ + 2H ₂ O ↑ to form SiO ₂ .

Also, in the case of OCD, RnSi (O
It is considered that SiO ₂ is formed when H) _4- n undergoes hydrolysis and dehydration decomposition by heating.

The SiO ₂ film forming solution is not limited to the above. Also, the heating condition is about 500, which causes hydrolysis.
It was confirmed that when the temperature was at least ° C, SiO ₂ was generated, and if the treatment time was extended, the same effect as in the above example could be obtained.

After forming the oxide film 6 as described above, the first
As in the case of the figure, in (e), the oxide film of the unnecessary portion of the formed oxide film, that is, the portion to be the element forming region on the main surface of the substrate is photo-patterned, and, for example, fluorine is used. It is removed by etching with an ammonium chloride solution.

Instead of (e) above, a nitride film is selectively formed in a predetermined portion (region for forming the element) before the oxidation in (d) so that an oxide film is not formed in that portion. May be.

Further, the portion 4 has a high concentration of phosphorus and boron implanted in the steps (a) and (b), and therefore, in order to use it as an element formation region, the concentration of phosphorus and boron as impurities is high in the element performance. However, in such a case, as shown in (f), the epitaxial film 7 is formed on the surface of the silicon substrate 1 at a predetermined concentration and a predetermined thickness, and this portion is used as an element formation region. Good.

The points other than the step (d) such as the plan view of the element are the same as those in the first embodiment.

(D) Fourth Embodiment This embodiment is a method for forming the oxide film 16 in the step (e) in the second embodiment shown in FIG.
The method using the oxidizing solution (coating solution OCD for forming SiO ₂ film) shown in the third embodiment is adopted, and the step (e) in FIG. 4 is performed in the third embodiment. Other than that, the second and third methods are the same.
This is the same as the embodiment.

(E) Fifth Embodiment In this embodiment, instead of forming the oxide film 6 in the step (d) of the first embodiment shown in FIG.
An organic polymer dielectric film is formed using a dielectric film forming resin.

That is, in FIG. 1 (d), the cavity region 5
A dielectric film 6 ′ is formed on the surface of and the surface of the hole 3.

Although it depends on the heat resistance performance of the dielectric film forming resin used at this time, the dielectric film is usually formed by PSG, nitriding for those elements after the element formation including the high temperature heat treatment step and the wiring formation step between them are completed. Since it needs to be formed after forming a protective film such as a film, if the step (f) in FIG. 1 needs to be performed, the step is performed before (d).

If the elements and wirings can be formed at a temperature within the heat resistant range of the resin, the elements and wirings may of course be formed after the dielectric film forming step.

As the dielectric film forming resin, for example, as a polyimide-based resin, "PIQ" (trade name, manufactured by Hitachi Chemical Co., Ltd.) and "isoimide type IP-6001" (trade name, Kanebo Corporation, NS) (Made by C), "Fluorocoat EC-104" (trade name, manufactured by Asahi Glass Co., Ltd.) as a fluorine-based resin, and "FA-7001" (trade name, manufactured by Kanebo Co., Ltd., NSC) as a fluorinated polyimide resin Etc. can be used.

It goes without saying that the organic polymer resin solution for forming a dielectric is not limited to these.

As for the dielectric forming method, in any resin solution, the solution is injected from the hole 3 and spin is applied so that the solution evenly wets the surface in the cavity region 5. This operation is carried out in the saturated vapor of the solvent, especially in the case of Fluorocoat.

The rotation speed of the spin was set to 6000 rpm in consideration of safety when using a 3-inch wafer.

The viscosity of each resin solution product above is CP
It will be as shown below.

PIQ… 11 (14.5%) solvent NMP / DMAc
IP-6001… 28 (30%) Solvent NAP / Xylene Fluorocoat “EC-104”… 1.1 Solvent CFC R-11
3 FA-7001 50 (30%) Solvent NAP / xylene Therefore, depending on the shape and size of the holes 3, it may be better to dilute the solution by adding the solvent before performing the injection operation. In that case, the resin solution is injected and pre-cured by low temperature heating, and the resin solution injection low temperature heating is repeated as many times as necessary.

The fluoro coat can be injected and attached in the form of an aerosol.

 After the injection, heat treatment is performed, for example, under the following conditions.

For PIQ… 60 minutes at 200 ℃, then 30 minutes at 350 ℃ IP-6001… 60 minutes at 300 ℃, then 15 minutes at 400 ℃ Fluorocoat EC-104… 180 minutes at 60 ℃, then room temperature In the case of dry FA-7001 ... 300 ° C. for 60 minutes, then 400 ° C. for 15 minutes By the heat treatment as described above, a dielectric film 6 ′ having the following desired performance is formed.

Relative permittivity (1kHz) PIQ 3.4 IP-6001 3.6 EC-104 3.7 FA-7001 3.0 In addition, in this example, to remove unnecessary portions of the formed dielectric film (step e in FIG. 1) , For example, by O ₂ plasma or the like.

Moreover, in order to increase the mechanical strength of the structure, a silicon-based filler or the like may be injected into the holes 3.

In addition, also in the case of this embodiment, the above-mentioned second
An example is shown in FIGS.

(F) Sixth Embodiment This embodiment is different from the second embodiment shown in FIG. 4 in that the oxide film 16 is formed in the step (e) instead of the fifth embodiment. The method of forming an organic polymer dielectric film by using the dielectric film forming resin is adopted, and the step (e) of FIG. 4 is replaced with the method described in the fifth embodiment. The other points are the same as those of the second and fifth embodiments.

The dielectric film formed here has heat resistance enough to withstand the temperature of 200 to 350 ° C. in the wire bonding process of the post-treatment.

In addition, several methods may be combined in order to make the insulation separation more complete than the above-mentioned embodiment alone. For example,
On the oxide film (6 or 16 in FIGS. 1 and 4) formed in the first, second, third, and fourth embodiments, the organic polymer dielectric is formed by the method shown in the fifth and sixth embodiments. It is a combination such as forming a film.
As a result, even if a defective insulation portion such as a pinhole occurs in the lower oxide film, it can be covered by the upper layer.

〔The invention's effect〕

As described above, according to the present invention, the portion directly above the cavity region serving as the isolation region is supported by the surface portion of the semiconductor substrate (the portion where no groove or the like is provided), and the oxide film or the organic film is formed on the surface of the cavity region. Since a dielectric layer such as a polymer dielectric film is formed and the above surface portion is thermally oxidized and isolated in a later step, the element isolation region is reliably formed on the semiconductor substrate. Can be formed. In addition, since the supporting portion of the separation region is on the surface of the substrate and that portion is thermally oxidized for insulation separation, the thickness distribution of the oxide film on the substrate surface is measured when inspecting whether the separation is complete or not. It can be easily confirmed by nondestructive inspection. Therefore, the number of inspection steps and costs are reduced, and the effect that the manufacturing can be performed at low cost is obtained.

Further, according to the method of the present invention, the shape of the separation region 8 can be made arbitrary, and the space formed in the hollow region has an effect of air separation.

In addition, in the third and fourth embodiments, an oxidizing solvent is used for forming an oxide film, the solvent is forcibly injected by a mechanical method, and then the film is formed by heat treatment. It is possible to easily form a good oxide film without causing poor controllability due to blockage of the holes 3 during oxidation during the process.

In addition, in the fifth and sixth embodiments, the organic dielectric film formed on the device and the wiring region is also effective as a protective film against them, and the dielectric formation for device isolation is performed at the same time with respect to moisture resistance and resistance. There is an advantage that it can also form a protective film for stress and the like.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the steps of the first embodiment of the present invention, FIGS. 2 and 3 are plan views of an example of the embodiment of FIG. 1, and FIG. 4 is a second view of the present invention. It is sectional drawing which shows the process of an Example. <Explanation of reference symbols> 1 ... Silicon substrate 2 ... Predetermined region including a portion to be a cavity region 3,13 ... Hole 3 ', 13' ... Portion to be a hole by etching 4 ... Portion immediately above the cavity region 5 , 15 ...... Cavity area 5 ', 15' ...... The part which becomes a cavity area by etching 6,16 …… Oxide film (dielectric film) 7,12 …… Epitaxial film 8,18 …… Separation area (element formation area ) 9,19 …… Surrounding part 10, 11 …… Insulating part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 27/00 301 L

Claims (2)

[Claims] 1. A cavity region is formed inside the semiconductor substrate through a hole or groove that communicates with the surface of the semiconductor substrate, and a support portion in the surface portion of the semiconductor substrate that is not provided with the hole or groove directly above the cavity region. The step of forming so that the portion is supported, and at least one of an oxidizing gas, a nitriding gas, a nitride film forming gas, an oxide film forming solution or an organic polymer resin solution is passed through the hole or groove and The step of supplying or injecting into the cavity region, the step of heating in the above state to form a dielectric film on the surface of the cavity region, and the portion directly above the cavity region by thermally oxidizing the supporting portion of the semiconductor substrate surface portion. A method for manufacturing a semiconductor substrate, comprising: a step of insulatingly separating from the other part. 2. The semiconductor substrate, wherein an epitaxial layer is formed on a base semiconductor substrate, and the cavity region includes a portion of the epitaxial layer and the epitaxial layer in the base semiconductor substrate. It is formed by being surrounded by a part of a semiconductor substrate to be a base, and the step of thermally oxidizing the supporting portion is a step of thermally oxidizing the supporting portion of the semiconductor substrate and the epitaxial layer. The method of manufacturing a semiconductor substrate according to claim 1, wherein