JPH08214187A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a television circuit from operating at a lower frequency than a prescribed lowest frequency. SOLUTION: A video display device is constituted of a phase detector 21 which detects the phase difference between output signals and input signals, converters 23, 24, and 25 which generate signals having such values that indicate the frequency of the input signals, but are limited through a diode D25a , and an oscillator 22 which is controlled for phase and self-running frequency by the outputs of the detector 21 and oscillators 23, 24, and 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device for synchronizing an output signal source with a synchronization input signal of a deflection frequency.

[0002]

2. Description of the Related Art In a television monitor, for example, a deflection current generated by an output stage of a deflection circuit is synchronized with a horizontal synchronization pulse extracted from an incoming television signal by using an ordinary synchronization separator. Synchronizing the deflection oscillator directly with the synchronization pulse is not preferred because the deflection current generated by the output stage is more likely to be affected by disturbances, for example, due to noise present in the synchronization pulse. Phase locked loops (PLLs) are commonly used to eliminate this interference.
Is used. The PLL includes a phase discriminator having a tunable oscillator and a low-pass filter downstream, the phase discriminator comparing a specified reference end of the oscillator output signal to the leading edge or center of the synchronization pulse. The control voltage or control current derived from this phase deviation is integrated by a low-pass filter and supplied to the oscillator as a DC voltage or DC current, and the frequency of the oscillator is output until the output signal of the oscillator and the phase of the corresponding synchronization pulse become equal. And change the phase. The residual error depends on the severity of control, that is, the loop gain.

In order to prevent scan line jitter due to interference caused by noise in the synchronization pulse, it is desirable that the response time of the PLL to a change in the phase or frequency of the synchronization pulse not be too fast. This is generally obtained by the relatively large time constant of the low-pass filter and the small overall gain, but such a large time constant itself reduces the acquisition or lock-in range of the PLL oscillator. This capture range is defined, for example, as the maximum difference between the free-running frequency of the oscillator and the frequency of the synchronization input signal that allows the oscillator to lock in to the synchronization pulse. Also, to prevent the capture time or lock-in time from becoming unnecessarily long, it is substantially greater than the maximum required in terms of the maximum frequency difference between the frequency of the synchronization pulse and the free running frequency of the oscillator encountered during operation. It may be desirable to specify that the capture range be limited so that it does not. Limiting the capture range to this necessary maximum is obtained, for example, by limiting the maximum change range of the control current that controls the frequency of the oscillator.

For example, in a normal television receiver, the frequency change of a synchronization pulse that occurs during reception of an incoming television signal is generally smaller than the frequency of the synchronization pulse. Therefore, the oscillation frequency is controlled in such an application. There is no problem in limiting the maximum control range of the control current. But,
In certain other applications, such as television monitors designed to receive incoming signals with various synchronization frequencies, the predetermined frequency of the synchronization pulse will be selected from a wide range of possible frequencies. . For example, the frequency of the synchronization pulse may be a frequency selected from a frequency range of 15750 to 31500 Hz. Thus, the desired narrow capture range, which spans from below a certain free-running frequency of the oscillator to above a certain frequency, is not wide enough to synchronize the oscillator over the full possible range of frequencies of the sync pulse.

[0005]

According to one aspect of the present invention, an output signal source has a frequency controlled according to a combination control current flowing through its control terminal, and the combination control current is generated by a phase detector. It includes the control current of. The phase detector is responsive to an output signal and a synchronization input signal. The first control current controls the phase of the output signal according to the phase of the input signal. A frequency-to-current converter, including a frequency-to-voltage converter, responds to the synchronization input signal, and the frequency-to-voltage converter generates a voltage representative of the frequency of the synchronization input signal. The voltage generated by the frequency-to-voltage converter is coupled to a voltage-to-current converter, where a second control current representing the frequency of the synchronization input signal is generated.

In a circuit embodying the present invention, an output signal is generated by a PLL oscillator (OSC). The oscillator oscillates at a horizontal frequency when synchronized, and its output signal controls the timing of a deflection cycle formed at the output stage of the deflection circuit. The first control current signal that controls the frequency of the oscillator represents the phase difference between the horizontal sync pulse and the output signal of the oscillator. For example, the first control current signal synchronizes the phase of the output signal to match the phase of the horizontal sync pulse, and the second control current signal sets the free running frequency of the oscillator. The capture range of a given oscillator corresponds to a given value of the second control current signal, and for a given free-running frequency of the oscillator, only a fraction of the horizontal frequency. It may extend from a lower frequency to a higher frequency by a fraction. Therefore, the capture range is narrower than the free-running frequency of the oscillator.

[0007] The second control current signal can take a range of values. Since this value has the advantage of making the free-running frequency of the oscillator approximately equal to the frequency of the synchronization pulse, the frequency of the synchronization pulse can be selected from a wide range of necessary frequencies. This frequency range is, for example, 15750-31500H
May cross z. Therefore, the frequency of the sync pulse which can be selected from this wide range of frequencies may be within the narrow acquisition range of the oscillator set by the second control current signal.

Since the capture range for a given value of the second control current signal is substantially narrower than the full frequency range that the sync pulse can take, the capture range for each given frequency of the sync pulse is relatively narrow. In this way, the acquisition or lock-in time of the oscillator is kept short with respect to the phase and frequency of the synchronization input signal. The second control current signal can move the capture range anywhere, for example, within the entire required frequency range of the sync pulse, and is relatively controlled by adjusting the free-running frequency of the oscillator to be approximately equal to the frequency of the sync pulse. Keep narrow.

[0009] The frequency detector may include a filter with a large time constant to eliminate noise from the second control current signal. Since this filter responds to the synchronization pulse and is provided outside the feedback loop of the PLL, there is an advantage that the filter does not affect the transient response of the PLL to the phase change of the synchronization pulse which does not reach the steady-state frequency change. In accordance with another aspect of the invention, the voltage detector comprises a transistor for generating a second control current signal at the collector electrode. The collector electrode of the transistor is coupled to the control terminal of the oscillator and supplies a second control current signal to this terminal and combines it with the first control current signal to generate a combined control current signal. The transistor has the advantage that it does not affect the impedance of the control terminal of the oscillator, since the impedance of the collector electrode of the transistor is substantially higher than that of the control terminal. In addition, there is the advantage that the second control current signal is independent of the voltage at the control terminal, since the transistor operates as an almost ideal current source.

For example, in some television receivers, the retrace pulse generated at the output stage of the horizontal deflection circuit is coupled to a power supply that generates an energizing voltage that energizes other circuitry in the receiver. The frequency of the deflection current and that of the retrace pulse are set below a certain minimum frequency in order to prevent the wrong operation mode of the circuit which may cause trouble to other circuits and to eliminate the possibility of trouble to the deflection circuit. It may be desirable to keep high. Operating at a deflection frequency above this predetermined minimum frequency eliminates the possibility of interference with certain television circuits that may occur at a lower deflection frequency.

According to still another aspect of the present invention, the frequency of the output signal of the oscillator is kept higher than the predetermined minimum frequency even when the frequency of the synchronization pulse is lower. Thus, for example, when no incoming television signal is being received, the frequency of the oscillator output signal is kept above a predetermined minimum frequency.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, deflection circuit 200 for implementing the invention includes a PLL100 which generates a signal V _F of the horizontal frequency f _H. Circuit 200 is used to perform horizontal scanning on a television receiver. In steady state operation, the horizontal synchronizing signal of the signal V _F is the frequency f _H H _S
Will be synchronized. Signal V _F is coupled to a phase control loop circuit 101 of the normal configuration, it controls the horizontal output stage 28 by providing a phase reference. Output stage 28 generates a deflection current i _Y in a deflection winding L _Y.

Output stage 28 also generates a retrace signal V _RT ,
This is supplied to, for example, a switching power supply 60. Power supply 6
0 produces a DC voltage + V. The voltage + V is used to activate other circuits of the television receiver not shown in FIG. The retrace pulse signal V _FB generated in the usual way by the output stage 28 gives the actual phase of the deflection current i _Y and the phase control loop circuit 101 synchronizes the signal V _{FB and the} deflection current i _Y with the signal V _F. . Phase correction circuit 32 is the signal V _F, V _FB
From the phase difference indicating signal 34a. The signal 34a controls the degree of phase shift of the phase shifter 30,
Phase shifter 30 by changing the phase of the signal V _F, generates a signal V _FS of horizontal frequency phase-shifted with respect to the signal V _F at its output terminal, deflection current i _Y in which a result is produced at the output stage Control timing. Signal V _FS is the signal V _F and example phase a deflection current i _Y.

The tracking response time of the phase control loop circuit 101 for the phase change of the retrace signal V _FB is shorter than the corresponding tracking response time of the PLL 100 for the phase change of the sync input signal H _S containing the sync pulse. Phase control loop circuit 101
Is adjusted to accommodate rapid changes in the switching time of the horizontal output stage 28, which can occur, for example, when rapid changes in electron beam current occur, whereas the PLL 100 removes noise or jitter associated with the synchronization signal H _S. Is adjusted as follows.

Synchronization signal H_SIs supplied to the phase detector 21
Signal H_{S (1)}And the signal supplied to the frequency-voltage converter 23
H_{S (2)}Is generated. signal
H_{S (1)}, H _{S (2)}Each have a rectangular waveform, for example.
Each transposition time is signal H _SImmediately after the transition of
Come later. The frequency-voltage converter 23 receives the signal H_{S (2)}Frequency
Signal V representing₁To occur. Signal V₁Is the low pass filter
Input terminal of the voltage-current converter 25 supplied via 24
25a is a low-pass signal V₂To generate. Low-pass filter 2
4 is the signal V₂From the vertical frequency. Da
Iod D_25aIs the voltage V '₂Is applied to the terminal 25a to
Issue V₂Does not fall below a certain level, eg 1.3V
To Signal V₂By maintaining this above this level
As described later, the signal V_FOf the corresponding frequency
Cannot be the lowest frequency. Below this predetermined minimum frequency
The operation is, as described later, performed in a case where the power supply is activated by the voltage + V in FIG.
It may damage the revision circuit. Voltage-current converter 2
5 is signal H_SCurrent signal I representing the frequency of_FGenerate
It Current signal I_FIs supplied to the input terminal 20a of the adder 20
The adder is connected to an output terminal 22a by an oscillator (OSC).
22 that controls the frequency of the current_COccurs
I do. The second input terminal 20b of the adder 20 is described later.
Thus, the current signal Iφ is supplied. Combined current signal I
_CAre the current signals Iφ, I_FRepresents the sum of

The output signal V _F of the oscillator 22 is the phase detector 2
No. 1 terminal 21b. The phase detector 21 is connected to the terminal 2
1a receives the signal H _{S (1)} and generates a signal Vφ1 representing the phase difference between the signal H _S and the output signal V _F of the oscillator 22. The signal Vφ1 is applied through a low-pass filter 26 constituting a loop filter of the PLL 100, and generates a current signal Iφ at the second input terminal 20b of the adder 20 as described above.
Thus, PLL 100 includes phase detector 21, low pass filter 26 and oscillator 22.

The free-running frequency of the oscillator 22 is, for example, the signal Iφ
Is zero, the signal V of that oscillator_FDefined as the frequency of
It Due to the addition operation of the adder 20, the combined current signal
I_CCurrent signal I included in_FIs the free-running circumference of the oscillator 22
Determine the wave number. Current signal I _FIs the synchronization signal H_SGiven
The oscillator 22 outputs the signal H_SFrequency
Oscillate at approximately the same frequency. In steady state, the current
The signal Iφ is the signal H_SOscillation for given frequency
Signal V of the vessel 22_FAnd signal H_SFrequency and phase are equal
Take a value that makes

[0018] For example, the frequency of the signal H _S is 15750Hz der the horizontal frequency of the NTSC standard. The current signal _IF is
When the current signal Iφ changes between its possible minimum and maximum values, the frequency of the signal V _F of the oscillator 22 is, for example, 157.
It is allowed to change from slightly lower than 50 Hz to slightly higher. In another example, the frequency of the signal H _S 31500H
When z, the frequency of the signal V _F of the oscillator 22 is 31500
It can vary from slightly below Hz to slightly above Hz. Since this change is relatively small, it has the advantage of keeping the capture range and capture time small. The acquisition range associated with the signal H _{S at} , for example, 15750 Hz need not overlap the acquisition range associated with, for example, 31500 Hz, so that the entire frequency range that the signal H _S can take for synchronization of the output signal V _F of the oscillator 22 is The advantage is that the capture range associated with any given free running frequency of oscillator 22 is substantially greater.

Another feature of the present invention is that when the frequency of the signal H _S is not higher than a predetermined minimum frequency, the voltage V ′ ₂
The output signal V of the relation without oscillator 22 to the frequency of but signals H _S
A current I _F is generated whose magnitude keeps the frequency of _F above its predetermined minimum frequency. The switchable power supply of FIG. 1, which requires a return signal V _RT with a frequency above this lowest frequency for normal operation, may not operate properly if the frequency of the signal V _RT is too low. Also, a television deflection circuit not shown in FIG. 1 may be damaged if the deflection frequency is too low. Therefore, so as not to impair some of the television receiver circuitry (not shown), it is advantageous to set such a minimum frequency for the signal V _F.

FIG. 2, which implements each feature of the present invention, shows a detailed embodiment of PLL 100 of FIG. Like numbers and symbols in FIGS. 1 and 2 indicate like things or functions.
In FIG. 2, the signal H _S includes an inverter 27a that feeds the inverter 27b to generate the signal H _{S (2)} at the terminal 23c of the frequency-voltage converter 23. The converter 23, which is coupled via the buffer 27, in the embodiment of FIG. 2, is configured using a control circuit NE5560 for the manufacture of the analog part of Signatures Corporation. Transducer 23 produces a signal H _S corresponding rectangular positive voltage pulse of the signal V ₁ to the time the terminal 23a of the leading edge happens terminal 23c of the synchronization pulses _(2). The pulse width T of each pulse of the signal V ₁ was equal to the period between corresponding successive pulses of the signal H _{S (2).} However, since the period between successive pulses of the signal V ₁ was equal to the period between corresponding successive pulses of the signal H _{S (2),} the duty cycle of the pulse of signal V ₁ was directly to the frequency of the signal H _{S (2)} Involved. When there is no voltage V ₁ pulse, the signal V ₁ is approximately zero volts, as described below. The positive, substantially flat level of each pulse of signal V ₁ has a value controlled by clamping the operation of Zener diode 121 coupled between terminal 23a and ground. Signal V ₁
When the pulse of 2 does not occur, the terminal 23a of the converter 23
Are not driven by the converter 23, and the impedance formed at the terminal 23a by the converter 23 is high.

The pulse width of each positive pulse of signal V ₁ is
Capacitor C23 and terminal 2 coupled between 3d and ground
Determined by a manually variable network _R23a coupled between 3e and ground. DC component voltage or average value of signal V ₁ which varies in accordance with the duty cycle of the pulse of signal V ₁ was directly related to the frequency of the signal H _{S (2).} That is, the higher the frequency of the signal H _{S (2),} the higher the DC component or the average value of the signal V ₁ . The pulse width T determines the upper limit of the frequency detection. Above this upper limit, the shock coefficient of the signal V ₁ does not increase when the frequency of the synchronizing input signal H _S increases.

The signal V ₁ is coupled to the base electrode of the transistor T _25a via the low-pass filter 24 comprising a resistor R _24a. Between the terminal 24a and earth resistance R _24a are combined filter capacitor C _24, giving the filtering capacitance of the filter 24. Signal V _"2 DC level of the terminal 24a is proportional to the frequency of the signal H _S. Terminal 24a is coupled to the cathode of the diode D _25b, the anode of the diode D _25b of the terminal 25a is coupled to the base electrode of the transistor T _25a Te to form a signal V ₂ proportional to the frequency of the signal H _S to its base electrode. diode D _25a terminals 24
The voltage of a is given a DC level shift of -0.7V. The cathode of the diode D _25a is coupled to terminal 25a, the clamp voltage V _'2 thereof cathode voltage V _"2 terminal 24a is assume a level of 1.3V to the signal V ₂ when more than a predetermined voltage
Is joined to. When the frequency of the synchronizing signal H _S is lower than the corresponding predetermined minimum deflection frequency required for a successful operation as described above, the voltage V _"2 is lower than the predetermined voltage. For example, shown for use in the generation of signal H _S when there is no synthesis television signal is not the voltage of the signal V ₂ is the voltage VL '
2 clamped to 1.3V.

The voltage V ₂ generated at the terminal 25a is the base voltage of the transistor _T25a of the voltage / current converter 25.
The emitter electrode of the transistor T _25a is grounded through a variable resistor R _25b in series with resistor R _25a, resistors R _25a and R _25b are voltage-current converter, which is defined as the ratio of the output current signal I _F and the voltage of the signal V ₂ Control the ratio. This conversion ratio can be manually adjusted by, for example, a manual adjustment resistor _R25b . Collector current signal I _F of the transistor T _25a represents the level of the signal V _2, thus representing a frequency of the signal H _S. Diode D _25b tracks the temperature-related changes in the base-emitter junction of transistor T _25a ,
_It compensates for the corresponding change in the base-emitter voltage of _25a . In this way, the current signal I _F is made substantially independent of temperature changes. Current signal I _F of the collector electrode of the transistor T _25a is supplied to an input terminal 20a of the adder 20.

In some televisions, the synchronizing signal H _{S (2)} during vertical retrace may not include a horizontal synchronizing pulse, so that the signal V ₁ of the converter 23 does not show the waveform required for normal operation. There is. "In order to prevent a significant change or interference _2, such interference in the signal V" signal V across capacitor C ₂₄ which occur because there is no horizontal sync pulse signal H _S in the vertical blanking _{(2) 2} it may be desirable to use a capacitor C ₂₄ having a large capacity to maintain a relatively constant. This disturbance of signal V " ₂ may cause a transient corresponding to the frequency of signal _VFS of FIG. 1 at the beginning of vertical retrace.

The cathode of the Zener diode D _21a is coupled to the output terminal 23b of the transducer 23, the anode is coupled to the base electrode of the transistor T _25b. Transistor T
_25b emitter electrode is grounded, collector electrode is terminal 2
Bound to 3a. When a positive pulse of the signal V ₁ is generated, the frequency-voltage converter 23 generates a signal whose level is not significantly positive at the terminal 23b and causes the zener diode D
Reverse conduction occurs at _21a . Therefore, no base current is supplied to the transistor _T25b . On the other hand, as described above, the signal V ₁
When the positive pulse is not generated becomes significantly positive level signal V ₄ which has been generated in the transducer 23, the diode D
_This causes reverse conduction of _21a . Therefore, a sufficient base current is supplied to the transistor _T25b to make it conductive. In this way, transistor T _25b acts as a switch that conducts when signal V ₄ causes Zener diode D _21a to conduct.
When a positive pulse of signal V ₁ is produced, since the voltage signal V ₄ is greater than the breakdown voltage to be too low diode D _21a is not generated, the transistor T _25b is nonconductive, the effect on the signal V ₁ Although not exerted, when a positive pulse of signal V ₁ is not generated even without terminal 23a is driven by the converter 23, conducting the transistor T _25b is a signal V ₁ of the terminal 23a of the transducer 23 zero volts To In this way, the peak-to-peak amplitude of the positive pulse of signal V ₁ was equal to the breakdown voltage of the Zener diode D121 for frequencies given signal H _{S (2).}

The PLL 100 is also a synchronous processor TDA2 manufactured by the Linear LSI Products Division of Signatures.
595. The processor TDA2595 is connected to the terminal 21a.
Receives the synchronization signal HS ₍₁₎ supplied from the buffer 27.
Thus, the signal H _{S (1)} is supplied to the input terminal 21a of the phase detector 21 included in the TDA 2595. Oscillator 22 included in the processor TDA2595 generates a signal V _F, which terminal 21b of the phase detector 21
Supply to. The signal Vφ1 at the output terminal 21 of the detector 21 is supplied to the output terminal 20b of the processor TDA2595. Terminal 20b of processor TDA2595 is coupled to low pass filter. Filter 26 is terminal 20b
And an array of resistors R _26b and R _26a and a capacitor C _26a coupled in series between the ground and the ground. Terminal 20b is coupled to a capacitor C _{26b of} filter 26 which filters out high frequencies, and the other end of capacitor C _26b is grounded. Resistor R _26c between the terminal 20b and the transistor T _25a terminal 20a coupled to the collector electrode of which is coupled.
Current signal Iφ generated from the voltage of the terminal 20b by the resistor R _26c represents the phase difference between the signals V _F and the signal H _S of the oscillator 22.

The current signal I _M adjusted by manually adjusting the variable resistor R _m2 is also summed at terminal 20a. Current signal I
_M is adjusted to improve the linearity of the voltage-to-current converter 25 and flows through a resistor _Rm1 coupled to a variable resistor _Rm2 . Terminal 20a of the adder 20 together with acts as an input terminal for the current signal I _F, acts as a current summing junction to form a combined control current signal of the oscillator 22 by adding the current signal I _F, Iø and I _M. This terminal 20a, acting as a current summing connection, has the advantage of simplifying the control of the frequency and phase of the oscillator 22, which is controlled from these three signal sources. Since the impedance of the terminal 20a caused by the transistor _T25a is high, the transistor _T25a is connected to the terminal 20a.
It can be of supplying a current signal I _F that can take a wide range of values without affecting the impedance.

The combined current signal I _C is supplied to the processor TD
It is supplied to the emitter electrode of the transistor T2 included in A2595. The base electrode of the transistor T2 is a current voltage Vre generated inside the processor TDA2595.
f. Because transistor T2 has a common base configuration, the voltage at terminal 20a is substantially the same for a wide range of values of combined current signal I _C. Transistor T
2 of the collector electrode is coupled to the oscillator 22, in accordance with the value of the current signal I _{C (1)} through the collector electrode of substantially equal transistor T2 to a current signal I _C, controls the frequency of the oscillator 22. Since the transistor T2 operates as a common base transistor, its emitter electrode terminal 20
The impedance between a and ground is low. In this way, the combined current signal I _C flowing out of the emitter electrode of the transistor T2 controls the frequency of the oscillator 22 without affecting the voltage at the terminal 20a.

According to another feature of the invention, the signal H_Sof
When the frequency is lower than the predetermined frequency, and when the signal H_SIs the same
When the period information is not included, the voltage V '₂Is the current signal I_FWhere
The free-running frequency of the oscillator 22 to a frequency higher than the specified minimum frequency
To a level that maintains. Manually adjustable current signal I_M
And the combined current signal I_CCurrent signal I included in _FHado
This also controls the free-running frequency of the oscillator 22, but the current signal
Iφ is the signal V of the oscillator 22_FOscillation of the phase and frequency of
Adjust within the capture range of the vessel. The capture range of the oscillator 22 is
Substantially less than the span of frequency, any of which is current
Signal I_F, I_MSelected as the free-running frequency of the oscillator.
It only needs to be within the range of frequencies that can be detected. So for example
Current signal I_FThe given value with
Frequencies within the corresponding acquisition range associated with the free-running frequency
Determine the number. The terminal 70 of the processor TDA2595
Capacitor C coupled between ground_{twenty two}Is the current signal
I _M, I_FThe source obtained in relation to a given set of values of
The maximum frequency of the shaker 22 is determined.

Output signal V of oscillator 22_FIs the processor
The signal V is included in the terminal 71 of the TDA2595._FSDepart
It is supplied to the resulting phase correction network. Return signal V_FBIs usually
Anti-R _FBTo terminal 72 of processor TDA2595
Supplied. As described above, the return signal V_FBIs the deflection in Figure 1
Current i_YIncluding information of. Second signal V_FThe phase of the network
32 is automatically adjusted in the usual manner by the deflection of FIG.
Current i_YAnd the signal V in FIG._FPhase difference or delay time between
Is independent of the change in the delay of the output stage 28 of FIG.
Become. Such a change in delay is caused by, for example, a cathode (not shown).
The beam current of the tube corresponds to the corresponding change in the video signal.
Get up when it changes more.

[0031]

[Effect of the Invention] As described above, the diode D _25a and a signal V ₂ by applying a voltage V _'2 to the terminal 25a so as not fall below a predetermined level for example 1.3V. By keeping the signal V ₂ above this level, the frequency of the signal V _F not become a predetermined minimum frequency corresponding. Operation below this predetermined minimum frequency may damage the television circuit energized at the voltage + V in FIG. Therefore, the television circuit can be prevented from being damaged by preventing the television circuit from operating below the lowest frequency by the function of the diode _D25a .

[Brief description of drawings]

FIG. 1 illustrates a PLL synchronized with a horizontal synchronization input signal and a circuit of a deflection circuit embodying features of the invention, including a phase control loop for synchronizing a deflection cycle generated by an output stage of the deflection circuit with the output signal of the PLL. FIG.

FIG. 2 is a diagram showing a more detailed embodiment of the PLL synchronization circuit of FIG. 1;

[Explanation of symbols]

Reference Signs List 20 combination control means 21 phase detector 22 current controlled oscillator 23 frequency-voltage converter 25 voltage-current converter D _25a diode (limiter)

Claims (1)

[Claims] 1. A video display device for generating an output signal synchronized with the input signal in accordance with a deflection frequency-related synchronization input signal including synchronization phase information, the oscillator including an oscillator for generating the output signal in a controllable phase. A phase detector for generating a first control signal indicative of a phase difference between the synchronization input and output signals, the first control signal being coupled to the oscillator and the phase of the output signal. And a second control signal that represents the frequency of the synchronization input signal in response to the synchronization input signal and that generates a second control signal that changes when the frequency of the input signal changes. Is coupled to the oscillator to control its free-running frequency, and is coupled to the second control signal generating means to limit the second control signal when the frequency of the synchronization input signal deviates from a predetermined value. value Further comprising a video display device a limiter to fit.