JPH08213887A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device in which terminals for a CR oscillator and a reset circuit are used in common to reduce the number of the terminals, much more functions are accommodated and the umber of external components is reduced. CONSTITUTION: A capacitor C used to generate a CR oscillation signal and a reset signal is connected to a CR oscillation control circuit 2 and a reset control circuit 3 in the inside of the semiconductor device 1 via a terminal T and a wiring L1, an output of the CR oscillation control circuit 2 is a clock signal in the inside of the semiconductor device and an output of the reset control circuit 3 is an internal reset signal. The CR oscillation control circuit 2 and the reset control circuit 3 have respectively comparators 4, 6, and a feedback circuit generates hysteresis voltages where low level and high level voltages are respectively Vc1, Vch and Vr1, Vrh.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
Specifically, it relates to a circuit configuration of a semiconductor device having a CR oscillation circuit and a reset circuit.

[0002]

2. Description of the Related Art Conventionally, when high precision is not required for a clock that is an operation timing of a semiconductor device, a CR oscillator circuit to which a capacitor or a resistor is externally attached is used as an inexpensive and simple oscillator circuit. There were many. Further, as a reset signal generation circuit for determining the initial operation when the power is turned on, a reset circuit with an external capacitor or resistor is often used at the same time.

FIG. 4 shows the structure of a conventional semiconductor device, which is C
1 shows a semiconductor device 1 having a capacitor C1 and a resistor R9 for R oscillation, and a capacitor C2 for generating a reset signal. The CR oscillator circuit has a reference potential (GN
D) and a capacitor C connected between the power supply voltage (V _DD )
1 and the resistor R9 are connected to the CR oscillation control circuit 2b of the semiconductor device 1 through the terminal T1, and the output of the CR oscillation control circuit 2b is passed through the buffer circuit 5 and the semiconductor device 1
Is configured to be an internal clock (hereinafter CLK) signal for operating. By controlling the discharge of the capacitor C1 by the CR oscillation control circuit 2b, it operates so as to perform CR oscillation.

Further, in the reset circuit, the other end of the capacitor C2 having one end connected to the reference potential is connected to the reset control circuit 3b of the semiconductor device 1 via the terminal T2, and the output of the reset control circuit 3b is the buffer circuit 7. Via an internal reset (hereinafter referred to as RST) signal for resetting the operation of the semiconductor device 1. When the power supply voltage is not applied, the electric charge of the capacitor C2 is discharged and the voltage of the terminal T2 becomes the reference voltage. After the power is turned on, the capacitor C2 is caused by the current flowing through the pull-up resistor of the reset control circuit (not shown). Are charged and the voltage at the terminal T2 gradually rises, and when the voltage at the terminal T2 rises above the voltage value set by the reset control circuit 3b, the reset control circuit 3b raises the RST signal to a high level, and the semiconductor device 1 It operates to release the reset state of.

As the circuit configurations of the CR oscillation circuit and the reset circuit, various circuits described in literatures and the like can be used and will not be described in detail. Further, when the accuracy of the oscillation frequency is not required, an oscillation circuit in which the resistor R9 is formed inside the semiconductor device 1 and only the capacitor C2 is externally attached is often used.

[0006]

The semiconductor device 1 shown in FIG. 4 can be realized by a simple circuit structure, but a terminal T1 connecting a capacitor C1 and a resistor R9 for CR oscillation is connected.
And a terminal T2 to which a capacitor C2 for generating a reset signal is connected. Therefore, the number of external parts of the semiconductor device 1 is increased and the number of terminals of the semiconductor device 1 is required to be increased. Therefore, a multi-pin package having a large number of terminals is used or terminals for other functions are deleted. I had to ask.

However, if there are many external parts, the board area for external parts becomes large, and the cost of these parts and management costs increase, and a multi-pin package is used. Therefore, there is a problem that the cost may be increased, and when the terminals for other functions are deleted, the required functions may not be sufficiently satisfied. In addition, since the reset signal generation timing and the clock timing due to oscillation are generated independently, there are many problems such as the need to consider synchronization separately.

Therefore, the present invention solves these problems, and
By making the terminals for configuring the R oscillator and the terminals for configuring the reset circuit in common, the number of terminals can be reduced, and more functions can be incorporated in the package with the same number of pins. An object of the present invention is to provide a semiconductor device capable of reducing the number of parts to be attached and the cost of parts and management costs. Furthermore, in the operation after turning on the power supply voltage,
Provided is a semiconductor device in which an oscillation clock is always operated after a reset state is released so that a reliable operation can be performed without worrying about a relation between a timing of a clock signal and a timing of a reset signal. The purpose is to do.

[0009]

In order to solve the above problems, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a CR oscillation circuit and a reset circuit.
The terminal for configuring the oscillator circuit and the terminal for configuring the reset circuit are used as a common terminal, and the voltage level that is in the reset state is lower than the low level voltage of the oscillation waveform, and the reset state is not established during oscillation. It is characterized by Further, the semiconductor device according to the second aspect is characterized in that the voltage level as the reset release voltage of the reset circuit is lower than the high level voltage of the oscillation waveform, and the oscillation is continued after the reset release. A semiconductor device according to claim 3 is a semiconductor device having a CR oscillation circuit and a reset circuit, wherein a terminal for configuring the CR oscillation circuit and a terminal for configuring the reset circuit are common terminals, and The voltage level in the reset state is higher than the high level voltage of the oscillation waveform, and the reset state is not maintained during oscillation. A semiconductor device according to a fourth aspect is the semiconductor device according to the first to third aspects, wherein the CR oscillation circuit and the reset circuit are formed in a CMOS configuration.

[0010]

According to the semiconductor device of the present invention, the semiconductor device according to claim 1 or 3 has a terminal for forming a CR oscillation circuit and a reset circuit. The pin and the pin can be used as a common pin, and the reset state will not occur during oscillation. In addition, the semiconductor device according to the second aspect of the present invention surely operates so as to continue oscillation after the reset is released.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Also, a detailed description will be given with reference to FIG. Throughout the drawings, the same or similar circuit elements are denoted by the same reference numerals throughout the drawings, and duplicated description is omitted. Figure 1 is C
The structural example of the semiconductor device of this invention by MOS structure is shown.
The other end of the capacitor C, one end of which is connected to the reference potential (GND) for CR oscillation and generation of a reset signal, has a terminal T
And for connecting the non-inverting input of the comparator 4 of the CR oscillation control circuit 2 inside the semiconductor device 1 via the wiring L1 and the non-inverting input of the comparator 6 of the reset control circuit 3 and the capacitor C. It is connected to a charge / discharge circuit including resistors R1 and R2 and a transistor Q1. The output of the comparator 4 serves as an internal clock (hereinafter referred to as CLK) signal of the semiconductor device 1 via the buffer 5, and also serves as a gate input of the transistors Q1 and Q2 to control discharge of the oscillation waveform. The inverting input of the comparator 4 has a hysteresis voltage of an oscillating waveform composed of the resistors R3, R4, R5 and the transistor Q2 (a high level voltage is Vc
h, and a hysteresis circuit for generating a low-level voltage as Vcl) is connected by a wiring L2.

The output of the comparator 6 is the buffer 7
It becomes a reset (hereinafter referred to as RST) signal for initializing the internal circuit of the semiconductor device 1 via the gate and also serves as a gate input of the transistor Q3. The inverting input of the comparator 6 includes resistors R6, R7, R8 and a transistor Q3.
Of the reset control circuit 3 consisting of (a high level voltage is Vrh and a low level voltage is Vrl)
A hysteresis circuit for generating is connected by a wiring L3. Each hysteresis voltage is Vrl <Vcl <Vrh <V depending on the combination of the resistors R3 to R8.
It is set so as to have a relationship of ch.

FIG. 2 shows operation waveforms of each part in the embodiment of FIG. The operation of the circuit of FIG. 1 will be described with reference to FIG. Time t1 when the power supply voltage V _DD is applied to the semiconductor device
Up to the point where the capacitor C has been discharged to the reference voltage, the voltage of each wiring L1 to L3 and CLK, RS
Each voltage of the T signal is a reference voltage. V at time t1
_{When DD} is applied, V _DD is also applied to the internal circuit of the semiconductor device 1 to enable operation, and the comparators 4 and 6 have inverting input voltages higher than non-inverting input voltages. Output becomes low level, the transistors Q2 and Q3 are turned off (cut off), and the hysteresis voltages of the CR oscillation control circuit 2 and the reset control circuit 3 are set to Vch and Vrh, respectively. After that, the capacitor C is gradually charged by the current flowing through the resistor R1 with the lapse of time, and the charging voltage rises. However, the voltage at the inverting input of each comparator has a relationship of Vrh <Vch. The RST signal is first inverted to a high level to release the reset state, the transistor Q3 is turned on (conducting), and the hysteresis voltage of the reset control circuit 3 becomes Vrl. When the capacitor C is continuously charged and the charging voltage exceeds Vch, the CLK signal is inverted to the high level and the transistors Q1 and Q2 are turned on.
With the N state, the hysteresis voltage of the oscillation control circuit 2 becomes Vcl, and the capacitor C is discharged by the current flowing through the resistor R2 except the current flowing through the resistor R1.

The capacitor C is continuously discharged and the terminal T
When the voltage of voltage V.sub.1 drops to the voltage of Vcl, the CLK signal is inverted to a low level, the transistors Q1 and Q2 are turned off again, and the hysteresis voltage of the CR oscillation control circuit 2 becomes Vch. C will be charged again by the current flowing through the resistor R1. By repeating this charging / discharging operation, continuous C
The LK signal comes to be output. Since the hysteresis voltage of the inverting input of each comparator has a relationship of Vrl <Vcl, the RST signal does not go to the low level again and the reset state does not occur while the oscillation is continued.

As described above, the operation after turning on the power supply voltage is
Since the oscillation clock operates so as to continue after the reset state is released, it is possible to surely operate without worrying about the relationship between the timing of the clock signal and the timing of the reset signal. Further, since the circuit is formed by the CMOS structure, it is possible to reduce current consumption as compared with the case where the circuit is formed by the bipolar structure.

It is necessary to set the values of the capacitor C and the resistor R1 to values such that the time constant of charging / discharging is sufficiently longer than the rise time of the power supply voltage, and the resistors R3 to R8 should take element variations into consideration. For example, it may be formed by an active resistance of a transistor. When a CR oscillator whose oscillation waveform starts from the power supply voltage is used, each hysteresis voltage is set to Vcl <Vrl <Vch <V.
There is no problem even if the reset state is set at a voltage higher than the high level voltage of the oscillating waveform by setting so as to have the relation of rh. May be provided to reduce current consumption.

FIG. 3 shows another embodiment of the present invention. C
The capacitor C for R oscillation and reset signal generation is
A resistor for charging and discharging the capacitor C while being connected to the input of the Schmitt circuit 4a of the CR oscillation control circuit 2a and the input of the Schmitt circuit 6a of the reset control circuit 3a in the semiconductor device 1 through the terminal T and the wiring L1. R1,
It is connected to a charge / discharge circuit composed of R2 and a transistor Q1. The output of the Schmitt circuit 4a becomes the CLK signal to the inside of the semiconductor through the buffer 5, and becomes the gate input of the transistor Q1 to control the oscillation waveform.
The output of the Schmitt circuit 6a becomes the RST signal via the buffer 7. The hysteresis voltage of the Schmitt circuit 4a is configured so that the high level voltage is Vch and the low level voltage is Vcl by the gate circuits having different input threshold voltages, and the hysteresis voltage of the Schmitt circuit 6a is high level by the same gate circuit. Is set to Vrh, and a low-level voltage is set to Vrl. Each hysteresis voltage is Vrl <Vcl <V.
It is set to have a relationship of rh <Vch.

Since the circuit operation of FIG. 3 is similar to that of FIG. 1 and the operation waveform is partly common to that of FIG. 2, the circuit operation of FIG. 3 will be described based on the operation waveform of FIG. By the time t1 when the power supply voltage V _DD is applied, the electric charge of the capacitor C is discharged to the reference voltage, and the wirings L1 to L
The voltage of 3 and the voltages of the CLK and RST signals are reference voltages.

[0019] V _DD to the semiconductor device 1 at time t1 is applied, together with the V _DD to internal circuit becomes operational is applied, the voltage level of the terminal T is a reference voltage, the output of each Schmitt circuits Low level and transistor Q1 is O
The state becomes the FF state. After that, with time, the capacitor C is gradually charged by the current flowing through the resistor R1 and the charging voltage rises. However, since the input threshold voltage of each Schmitt circuit has a relationship of Vrh <Vch, when Vrh is exceeded, First, the RST signal is inverted to the high level, the reset state is released, and the input threshold voltage of the reset control circuit 3a becomes Vrl. When the capacitor C is continuously charged and the charging voltage exceeds Vch, the CLK signal is inverted to the high level, the transistor Q1 is turned on, the input threshold voltage of the CR oscillation control circuit 2a becomes Vcl, and the capacitor C becomes Among the currents flowing through the resistor R2, the currents other than the current flowing through the resistor R1 are discharged.

The capacitor C is continuously discharged and the terminal T
When the voltage of the C voltage is lowered to the voltage of Vcl, the CLK signal is inverted to the low level, the transistor Q1 is turned off again, and the input threshold voltage of the CR oscillation control circuit 2a becomes Vch. Will be recharged by the current flowing through the resistor R1. By repeating this charging / discharging operation, continuous C
The LK signal comes to be output. Since the input threshold voltage of each Schmitt circuit is in the relation of Vrl <Vcl, the RST signal becomes low level again and does not enter the reset state while the oscillation is continued.

By combining the circuits shown in FIGS. 1 and 3,
Although the oscillation circuit and the reset circuit may be formed, it is better to generate the hysteresis voltage with a similar element configuration in consideration of the temperature characteristics of the hysteresis voltage and the like. Further, in order to improve the accuracy of the oscillation frequency, the resistor R1 may be externally attached. Furthermore, although the present embodiment has been described only with respect to the case where it is formed of a CMOS circuit, it is possible to form a similar circuit with a bipolar circuit.

[0022]

As described above, according to the present invention, claim 1
Alternatively, in the semiconductor device according to the third aspect, the terminal for forming the CR oscillation circuit and the terminal for forming the reset circuit can be common terminals, so that the number of terminals of the semiconductor device can be reduced. Package with the same number of pins,
In addition to the effect that more functions can be incorporated, the number of external parts can be reduced and the cost of parts and management costs can be reduced.

Further, in the semiconductor device according to the second aspect of the present invention, since the operation after the power supply voltage is applied is surely operated so as to continue the CR oscillation after the reset is released, the timing of the clock signal and the timing of the reset signal are There is an effect that a reliable operation can be performed without worrying about the relationship of. The semiconductor device according to claim 4 is C
Since it is formed by the MOS structure, there is an effect that a semiconductor device with low current consumption can be easily used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention,

FIG. 2 is an explanatory diagram showing operation waveforms of the first embodiment,

FIG. 3 is a circuit diagram showing another embodiment according to the present invention,

FIG. 4 is a configuration diagram showing a conventional embodiment.

[Explanation of symbols]

 4, 6: Comparator circuit 5, 7: Buffer circuit Q1, Q2, Q3: MOS transistor element L1, L2, L3: Signal line C: Capacitor T: Input terminal CLK: Internal clock signal RST: Internal reset signal Applicant ROHM stock Company

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 19/0948

Claims (4)

[Claims] 1. A semiconductor device having a CR oscillation circuit and a reset circuit, wherein a terminal for configuring the CR oscillation circuit and a terminal for configuring the reset circuit are common terminals and are in a reset state. A semiconductor device characterized in that a voltage level is lower than a low level voltage of an oscillating waveform and a reset state does not occur during oscillation. 2. The voltage level as the reset release voltage of the reset circuit is lower than the high level voltage of the oscillation waveform,
The semiconductor device according to claim 1, wherein oscillation is continued after reset is released. 3. A semiconductor device having a CR oscillating circuit and a reset circuit, wherein a terminal for forming the CR oscillating circuit and a terminal for forming the reset circuit are common terminals and are in a reset state. A semiconductor device characterized in that a voltage level is higher than a high level voltage of an oscillating waveform and a reset state does not occur during oscillation. 4. The semiconductor device according to claim 1, wherein the CR oscillation circuit and the reset circuit are formed in a CMOS structure.