JPH08213615A - Vertical mos field effect transistor - Google Patents

Abstract

PURPOSE: To make the current flow in a drain region disperse for lowering the ON resistance by providing the second layer of one conductivity type formed directly on the first whole layer having a higher impurity concentration than that of the first layer. CONSTITUTION: The vertical MOSFET is provided with the first layer 1 having a specific impurity concentration forming a drain region and an N-type source regions 3 selectively formed of two parts in P-type diffused regions 2 forming a channel region having the deepest part not exceeding the thickness of the second layer as well as a gate electrode 5 on a gate oxide film between the source regions 3 oppositely holding a high concentration drain region 9, source electrodes 6 formed striding over the source regions 3 and the P-type diffused regions 2 as well as high concentration drain region 7 an a drain electrode 8. Accordingly, the voltage between drain and source is lowered by about 10% but the current flow in the drain region 9 is dispersed thereby enabling the ON resistance to be lowered by 1.5-2 times than the conventional one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS field effect transistor (hereinafter referred to as vertical MOSFET) used in switching equipment and the like, and particularly 30 to 20.
This is effective for a device having a withstand voltage of about 0 V and a further reduction in on-resistance rather than withstand voltage characteristics.

[0002]

2. Description of the Related Art Vertical MOSFETs are not only excellent in high-speed performance, but also have a wide ASO (safe operating area) and are used as ideal power switching devices in a wide range of fields including switching power supplies. Has been done.

A conventional vertical MOSFET has a structural sectional view as shown in FIG. The vertical MOSFET shown is n
The channel type will be described in detail below.

This vertical MOSFET has a drain region 1
A P-type diffusion region 2 for forming a channel region is formed separately in a low-concentration n-type silicon semiconductor substrate that forms the n-type source region 3 of two parts.
And the gate oxide film 4 is formed on the surface of the silicon semiconductor substrate between the source regions 3 facing each other with the drain region 1 interposed therebetween, and the gate electrode 5 is further formed on the gate oxide film 4. And P-type diffusion region 2
In this structure, the source electrode 6 is formed over the surface, the high-concentration n-type layer 7 is provided on the back surface drain side of the silicon semiconductor substrate, and the drain electrode 8 is formed.

In the vertical MOSFET having this structure, a channel is formed at the interface between the P-type diffusion region 2 and the gate oxide film 4, and electrons reach the surface of the drain region 1 from the source region 3 through this channel. Flow toward the drain electrode 8 provided on the back surface side. The low concentration of the drain region 1 is to keep the drain breakdown voltage high.

[0006]

In this structure, the electrons flowing in the drain region concentrate on the surface of the drain position between the P-type diffusion regions, and the voltage drop in the region where the current concentrates becomes large. However, there is an inconvenience that the resistance (ON resistance) during conduction of the vertical MOSFET becomes extremely large.

[0007]

[Means for Solving the Problems] Vertical MOSFE of the present invention
T is intended to eliminate the above-mentioned inconvenience and to disperse the current flow in the drain region to reduce the on-resistance. The one-conductivity-type first layer and the first layer are the same. A semiconductor substrate having a second layer of one conductivity type connected to the entire surface of the first layer with a higher impurity concentration, and the deepest portion selectively formed in the second layer is the second layer. On the channel region between the source region and the second layer, and a reverse conductivity type channel region having a depth not exceeding the thickness of the source region, a source region of one conductivity type selectively formed in the channel region, And a formed gate.

Further, it has a structure in which the second layer is formed of an epitaxial layer.

[0009]

Since the second layer of one conductivity type is formed so as to be connected to the entire surface of the first layer with an impurity concentration higher than that of the first layer, the vertical MOSFET including the peripheral portion of the substrate is in a conductive state. At this time, the current flowing through the drain region flows along the high-concentration second-layer drain region, and since the high-concentration drain region is not separated at the deepest part of the channel region, the current flows uniformly over the entire surface. Concentration between diffusion regions for forming regions is reduced.

However, since the breakdown voltage between the drain and the source is slightly lowered, it is necessary to optimize the interval 10 between the source regions and the like, but the second layer is an epitaxial layer instead of a diffusion layer. As a result, the impurity concentration is high on the surface of the diffusion layer and decreases as the depth increases, and the electric field concentrates on the surface to lower the breakdown voltage, while the impurity concentration is uniformly distributed in the depth direction from the surface. Therefore, the breakdown voltage can be improved. In particular, when the second layer is formed of an epitaxial layer, it is easy to control the impurity concentration over the entire layer, so that the relationship between the resistance value and the breakdown voltage is easily controlled, and the design can be performed according to the purpose.

[0011]

EXAMPLE An example of the vertical MOSFET of the present invention will be described with reference to the cross section of the structure of the n-channel vertical MOSFET shown in FIG.

In the vertical MOSFET of the present invention, the first layer 1 having a predetermined impurity concentration forming the drain region and the second layer 9 connected to the entire surface of the first layer with an impurity concentration higher than that of the first layer 1 are formed. And a P-type diffusion region for forming a channel region in which the deepest part does not exceed the depth of the thickness of the second layer, which is selectively formed in the second layer. The gate oxide film 4 on the surface of the semiconductor substrate between the two n-type source regions 3 and the source regions 3 facing each other with the high-concentration drain region 9 sandwiched therebetween, and the gate electrode 5 on the gate oxide film 4. , A source electrode 6 formed over the source region 3 and the P-type diffusion region 2, and a drain region 7 and a drain electrode 8 having a high concentration on the back surface of the silicon semiconductor substrate. In addition, the gate electrode 5 and the source electrode 6 are connected at one place, and a plurality of vertical MO
This is a structure in which SFETs are connected in parallel.

According to this structure, the high-concentration drain region 9 is formed.
Since the resistance value of is small, the electrons flowing in the drain region are
As shown by the arrow, it does not concentrate between the P-type diffusion regions 2, flows along the high-concentration drain region 9 having a small resistance value, and is dispersed in the entire high-concentration drain region 9, and from here, the drain is uniformly downward. It flows into the electrode 8.

Further, since the high-concentration drain region 9 is formed even up to the periphery of the substrate, the reduction of the on-resistance is added by about several tens of% depending on the area ratio between the substrate and the peripheral portion.

Further, by forming the high-concentration drain region 9 as an epitaxial layer, the breakdown voltage could be improved.

Although the n-channel has been described in the embodiment, all conductivity types may be reversed to form a P-channel.

[0017]

In the vertical MOSFET of the present invention, as shown in FIG. 2, the drain-source voltage decreases by about 10%, but the current flow in the drain region is dispersed,
Since the effective cross-sectional area of the portion through which the drain current flows is increased, the effect of reducing the on-resistance by 1.5 to 2 times that of the conventional one is achieved.

Further, since the high-concentration drain region 9 is formed even up to the periphery of the substrate, the on-resistance can be reduced by a reduction effect of about several tens of% depending on the area ratio between the substrate and the peripheral portion. It

In particular, when the second layer is an epitaxial layer, it is easy to control the impurity concentration over the entire layer, so that the relationship between the resistance value and the breakdown voltage is easily controlled, and the design according to the purpose can be performed. .

[Brief description of drawings]

FIG. 1 is a structural sectional view showing an embodiment of a vertical MOSFET of the present invention.

FIG. 2 is a graph showing on-resistance and drain-source voltage showing effects of the present invention.

FIG. 3 is a structural sectional view showing a conventional vertical MOSFET.

[Explanation of symbols]

 1 low-concentration drain region 2 P-type diffusion region for channel formation 3 source region 4 gate oxide film 5 gate electrode 6 source electrode 7 high-concentration drain region 8 on the back side drain electrode 9 high-concentration drain region 10 interval between P-type diffusion regions 11 Insulating film

Claims (2)

[Claims] 1. A semiconductor substrate comprising a first layer of one conductivity type and a second layer of one conductivity type connected to the entire surface of the first layer with an impurity concentration higher than that of the first layer; A channel region of opposite conductivity type whose deepest part selectively formed in the layer does not exceed the thickness of the second layer, and a source of one conductivity type selectively formed in the channel region. A vertical MOS field effect transistor having a region, a source region, and a gate formed on the channel region between the second layers. 2. The vertical MOS field effect transistor according to claim 1, wherein the second layer is an epitaxial layer.