JPH08213471A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To mount a bipolar transistor requiring high pressure proof and a bipolar transistor requiring high-speed on the same chip. CONSTITUTION: The first bipolar transistor 31 and the second bipolar transistor 51 are mounted on the same chip. The first base area 34 of the first bipolar transistor 31 is formed with lower impurity concentration than that of the second base area 54 of the second bipolar transistor 51, far example, the first bipolar transistor 31 is a bipolar transistor of an output buffer circuit, and the second bipolar transistor is constituted as a bipolar transistor in a circuit other than the output buffer circuit. The first and second base areas 34 and 54 are formed by separate ion implantation processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device equipped with bipolar transistors having different breakdown voltages and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device having a plurality of bipolar transistors having different required breakdown voltages, ion implantation for forming a base region of each bipolar transistor is simultaneously performed. Therefore, the impurity concentration of the base region is the same for each bipolar transistor.

[0003]

However, when the base regions of a plurality of bipolar transistors having different required breakdown voltages are formed by ion implantation of the same specifications, the specifications and the speedup of the bipolar transistors which need to have a high breakdown voltage are required. It has been difficult to satisfy the required bipolar transistor specifications together.

That is, in order to increase the speed of the bipolar transistor, it is required to improve its ft, and it is necessary to narrow the base width. However, if only the base width is narrowed without changing the impurity concentration of the base region, the punch-through breakdown voltage between the emitter and the collector is lowered. Normally, the withstand voltage cannot be lowered so much because a voltage almost equal to the power supply voltage is applied between the emitter and the collector. Therefore, the base width may be narrowed and the base concentration may be increased. However, increasing the base concentration lowers the breakdown voltage between the emitter and the base. For this reason, the withstand voltage specification of the bipolar transistor, which requires a high withstand voltage, cannot be satisfied. As described above, it has been difficult to make a bipolar transistor having a high breakdown voltage and a bipolar transistor having a high speed have the same specification.

An object of the present invention is to provide a semiconductor device in which a bipolar transistor requiring high breakdown voltage and a bipolar transistor requiring high speed are mounted in the same chip, and a manufacturing method thereof. To do.

[0006]

SUMMARY OF THE INVENTION The present invention is a semiconductor device and a method of manufacturing the same which are made to achieve the above object.

A semiconductor device has a first bipolar transistor and a second bipolar transistor mounted in the same chip, and a base region of the first bipolar transistor is formed with an impurity concentration lower than that of the base region of the second bipolar transistor. It has been done. The first
The bipolar transistor is a bipolar transistor forming an output buffer circuit, and the second bipolar transistor is a bipolar transistor forming a circuit other than the output buffer circuit.

In the method of manufacturing a semiconductor device, the base region of the first bipolar transistor and the base region of the second bipolar transistor are formed by separate ion implantation steps, and at that time, the base region of the first bipolar transistor is formed. Ion implantation is performed with a lower dose amount and higher implantation energy than the ion implantation for forming the base region of the second bipolar transistor. The first bipolar transistor is a bipolar transistor forming an output buffer circuit, and the second bipolar transistor is a bipolar transistor forming a circuit other than the output buffer circuit.

[0009]

In the above semiconductor device, since the base region of the first bipolar transistor is formed with an impurity concentration lower than that of the base region of the second bipolar transistor, the first bipolar transistor has a higher breakdown voltage than the second bipolar transistor. Be converted. Further, since the base region of the first bipolar transistor and the base region of the second bipolar transistor have different impurity concentrations, the impurity concentration of the base region of the second bipolar transistor is set higher than that of the first bipolar transistor. 2 The base width of the bipolar transistor can be shortened. Therefore, the speed of the second bipolar transistor is increased.

In the method of manufacturing a semiconductor device described above, the base region of the first bipolar transistor and the base region of the second bipolar transistor are formed by separate ion implantation steps, and at that time, the base region of the first bipolar transistor is formed. Is performed with a lower dose amount and higher implantation energy than the ion implantation for forming the base region of the second bipolar transistor, the base region of the second bipolar transistor is higher than the base region of the first bipolar transistor. It is formed shallowly in concentration. Therefore, the speed of the second bipolar transistor is higher than that of the first bipolar transistor.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic configuration diagram of FIG.

As shown in the figure, the semiconductor substrate 11 is provided with a semiconductor device 1 including a first bipolar transistor 31 and a second bipolar transistor 51.
The first and second bipolar transistors 31, 51 are
For example, it is composed of an NPN vertical bipolar transistor.

That is, the semiconductor substrate 11 is, for example, a P-type semiconductor substrate 12 on which an N-type epitaxial layer 13 is formed.
An N ⁺ -type first buried diffusion layer 32 and an N ⁺ -type second buried diffusion layer 52 are formed between and. Further, a LOCOS oxide film 14 serving as an element isolation region is formed on the epitaxial layer 13.

An N ⁺ type first collector extraction diffusion layer 33 connected to the first buried diffusion layer 32 is formed in the epitaxial layer 13. A first base region 34 is formed in a part of the upper layer of the epitaxial layer 13 above the first buried diffusion layer 32. This first
The first emitter region 3 is formed on a part of the upper layer of the base region 34.
5 is formed.

Further, the epitaxial layer 13 has a second
An N ⁺ -type second collector extraction diffusion layer 53 connected to the buried diffusion layer 52 is formed. A second base region 54 is formed in a part of the upper layer of the epitaxial layer 13 above the second buried diffusion layer 52. A second emitter region 55 is formed in a part of the upper layer of the second base region 54.

The first base region 34 is formed with an impurity concentration lower than that of the second base region 54. It should be noted that the illustration of the interlayer insulating film and the electrodes connected to each region is omitted in the drawing.

In the semiconductor device 1, the second base region 5
Since the first base region 34 is formed with a lower impurity concentration than the fourth base region 34, the first bipolar transistor 31 has a higher breakdown voltage than the second bipolar transistor 51. In addition, the first base region 34 and the second base region 54
Since the impurity concentrations of and are different, the second base region 54 can be formed at a concentration higher than that of the second bipolar transistor 51, and the base width of the first base region 34 can be shortened. Therefore, the second bipolar transistor 5
1 is speeded up.

The semiconductor device 1 having the above structure can be applied to, for example, an input / output circuit using a bipolar transistor as an output buffer for speeding up. For example, the first bipolar transistor 31 constitutes a bipolar transistor of the output buffer circuit, and the second bipolar transistor 51
Constitutes a bipolar transistor for circuits other than the output buffer circuit.

Here, Bi of the Bi-CMOS IC
The CMOS inverter will be described. In the commonly used Bi-CMOS inverter 201 as shown in FIG. 2, two bipolar transistors Q1 and Q2 are used.
Of these, only the bipolar transistor Q1 has an emitter
Reverse bias is applied between bases.

Next, referring to FIG. 3, the waveform of the potential input to the Bi-CMOS inverter 201, the base potential waveform 2 of the bipolar transistor Q1, and the Bi-CM.
The output waveform 3 (= emitter potential of Q1) of the inverter when the input of the OS inverter transits from the low level to the high level will be described. In the figure, the vertical axis represents the potential and the horizontal axis represents the time. As shown in the figure, in the Bi-CMOS inverter, the reverse bias applied between the emitter and the base has a value sufficiently smaller than the power supply voltage. This is a NAND
The same applies to other basic gates such as NOR and NOR. It can be seen that the breakdown voltage between the emitter and the base may be set to a value sufficiently smaller than the breakdown voltage between the emitter and collector because it is sufficient if it is larger than the reverse bias value.

Next, referring to FIG. 4, an input / output circuit 2 using a bipolar transistor as an output buffer for speeding up.
The limit value of the breakdown voltage between the emitter and the base of No. 11 will be described. When the output control signal is C-, the data signal is D, and the input signal is I-, the bases of Q1 and Q2 are 0 V when C- is at a high level, and the output buffer is in the High-Z state. In the case of an IC that allows CMOS level input, it is necessary to ensure that the IC will not be destroyed even if the absolute maximum rated voltage is input in this state. Therefore, the withstand voltage between the emitter and the base of the bipolar transistor of the output buffer must be higher than the absolute maximum rated voltage. Therefore, the reduction of the base width for increasing the speed of the bipolar transistor and the increase of the base concentration are limited by the output buffer rather than the basic gate.

Therefore, in the semiconductor device 1, the first
If the withstand voltage between the emitter and the base of the bipolar transistor (bipolar transistor of the output buffer) 31 is set to, for example, about 7V, the absolute maximum rated voltage is sufficiently higher than 4.6V. Also, even if the emitter-base breakdown voltage of the second bipolar transistor (bipolar transistor other than the output buffer) 51 is set to, for example, about 4.5V, a bipolar other than the output buffer of the 3.3V version IC (absolute maximum rating 4.6V). There is no problem because it is used as a transistor. As described above, since the impurity concentration of the first base region 34 is formed lower than that of the second base region 54, the emitter-base breakdown voltage of the first bipolar transistor (bipolar transistor of the output buffer circuit) 31. Is the second bipolar transistor (bipolar transistor other than the output buffer circuit) 5
It will be higher than 1. As a result, most of the bipolar transistors can have the impurity concentration of the base region suitable for high speed operation.

Next, an embodiment relating to the method of manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process chart of FIG. In the figure, as an example, a method of manufacturing a Bi-CMOS input / output circuit using a bipolar transistor as an output buffer is shown. The same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in (1) of FIG.
Therefore, the P-type semiconductor substrate 12 has N ⁺First and second embedding of mold
The embedded diffusion layers 32 and 52 are formed. Then semiconductor substrate
N-type epitaxial layer 13 is formed on 12 to form a semiconductor
The base 11 is formed. Then, the epitaxial layer 1
LOCOS oxide film 14 for element isolation at a predetermined position on 3
Of the NMOS transistor region after forming the
P-well 15 is formed in the gate layer 13 to form a PMOS transistor.
N well 16 is formed in the epitaxial layer 13 in the star region
I do. Furthermore, the PMOS transistor area and the NMOS transistor area
Each gate 7 on the epitaxial layer 13 with the transistor region.
1, 91 are formed.

Then, for example, phosphorus (P
⁺ ) Is used to perform ion implantation to form an epitaxial layer 1
N ⁺ type source / drain diffusion layers 72 and 73 are formed in the NMOS transistor region 3 of FIG. Along with that, the first
An N ⁺ -type first collector extraction diffusion layer 33 connected to the first buried diffusion layer 32 is formed in the bipolar transistor region. Further, in the second bipolar transistor region, N ⁺ connected to the second buried diffusion layer 52 is connected.
A second collector extraction diffusion layer 53 of the mold is formed.

Next, P ⁺ source / drain diffusion layers 92, 93 in the PMOS transistor region of the epitaxial layer 13 are formed by ion implantation using, for example, boron difluoride (BF ₂ ⁺ ) as a P-type impurity. At the same time, the first external base diffusion layer 36 is formed in a part of the upper layer of the epitaxial layer 13 in the first bipolar transistor region, and the second external base diffusion layer 56 is formed in a part of the upper layer of the epitaxial layer 13 in the second bipolar transistor region. Form. Up to this point, a known method is used.

The LDD diffusion layers of the NMOS transistor and the PMOS transistor may be formed before the above ion implantation.

Thereafter, as shown in FIG. 5B, a mask 111 is formed of, for example, a resist, and a mask is formed on a portion where the base region 54 of the second bipolar transistor (a bipolar transistor other than the output buffer) is formed by lithography. An opening 112 is formed in 111. Then, for example, boron difluoride (BF ₂ ⁺ ) is injected as an impurity into the epitaxial layer 13 from the opening 112 by the ion injection method. The implantation conditions at that time are set such that the implantation energy is, for example, 55 keV, and the dose amount is, for example, 4 × 10 ¹³ cm ⁻² . The second base region (intrinsic base region) connected to the second external base diffusion layer 56
54 is formed. Incidentally. This ion implantation can also be used as an ion implantation for forming a LDD (Lightly Doped Drain) of the PMOS.

Subsequently, the mask 111 is removed by ashing or wet processing. Thereafter, as shown in (3) of FIG. 5, a mask 113 is formed by, for example, a resist, and is formed by lithography on the mask 113 on a portion where the first base region 34 of the first bipolar transistor (the bipolar transistor of the output buffer) is formed. The opening 114 is formed. Then, for example, boron difluoride (BF ₂ ⁺ ) is injected as an impurity into the epitaxial layer 13 from the opening 114 by an ion implantation method. Implantation conditions at that time are set such that the implantation energy is 90 keV and the dose amount is 1 × 10 ¹³ cm ⁻² , for example. Then, a first base region (intrinsic base region) 34 connected to the first external base diffusion layer 36 is formed.

After that, ashing or wet treatment etc.
The mask 113 is removed by. Then in FIG.
As shown in (4), an insulating film (for example, S
iO ₂After film 17 is formed, lithography and etching are performed.
And the first and second base regions 34, 54 by
On the upper insulating film 14, the first and second emitter contacts 37,
57 is opened. Furthermore, by the CVD method, polycrystalline silicon
After depositing a con film, arsenic (A
s⁺) Is, for example, 1 × 10¹⁶cm^-2Io with a dose of about
Patterning this polycrystalline silicon film after
The first emitter connected to the first base region 34
The electrode pattern 38 is formed. Along with that, the second
Second emitter electrode pattern 5 connected to the base region 54
8 is formed.

After further depositing the interlayer insulating film 21, 90
Heat treatment is performed at 0 ° C. for about 30 minutes. Then, arsenic (As) in the first emitter electrode pattern 38 is diffused into the first base region 34 to form the first emitter region 35,
The first bipolar transistor 31 is configured. At the same time, arsenic (As) in the second emitter electrode pattern 58 is diffused into the second base region 54 to form the second emitter region 55, thereby forming the second bipolar transistor 51.
Thereafter, each contact hole 22 for connecting the metal wiring layer and the lower layer is formed in the interlayer insulating film 21 and the insulating film 17 by lithography and etching. Subsequently, a metal wiring layer is formed, and the metal wiring layer is patterned to form each wiring 23 passing through each contact hole 22.

In the above manufacturing method, either the ion implantation in the second step or the ion implantation in the third step may be performed first.

In the method of manufacturing a semiconductor device described above, when the first base region 34 and the second base region 54 are formed by ion implantation, the ion implantation for forming the first base region 34 is performed and the ion implantation for forming the second base region 54 is performed. Since the implantation is performed with a lower dose amount and higher implantation energy than the ion implantation to be formed, the second base region 54 is larger than the first base region 34.
Is more concentrated and shallower. Therefore, the speed of the second bipolar transistor 51 is higher than that of the first bipolar transistor 31.

In the method of manufacturing a semiconductor device described above, the first bipolar transistor 31 is a bipolar transistor of the output buffer, and the second bipolar transistor 51 is a bipolar transistor other than the output buffer.

When such a structure is manufactured by the above manufacturing method, the withstand voltage between the emitter and the base of the first bipolar transistor (the bipolar transistor of the output buffer) 31 is about 7V, which is higher than the absolute maximum rated voltage of 4.6V. Be big enough. In addition, the second bipolar transistor (bipolar transistor other than the output buffer) 51
Since the withstand voltage between the emitter and base is about 4.5V,
Although the withstand voltage cannot be used for the output buffer of 3.3V version IC (absolute maximum rating 4.6V), there is no problem because it is used only for the output buffer.

As described above, the ion implantation for forming the first base region 34 and the second base region 54 of the first bipolar transistor 31 and the second bipolar transistor 51 is performed in a separate process, and the first bipolar transistor (output buffer circuit) is formed. Bipolar transistor of 31)
By setting the inter-base breakdown voltage higher than that of the second bipolar transistor (bipolar transistor other than the output buffer circuit) 51, most of the bipolar transistors can be manufactured under the base ion implantation conditions suitable for speeding up.

In the above embodiment, two kinds of bipolar transistors having different withstand voltages have been described as an example. However, for a plurality of bipolar transistors having different withstand voltages of three kinds or more, similarly, by changing the impurity concentration of the base region. It is possible to form the fastest bipolar transistor within the required withstand voltage tolerance range.
In that case, the ion implantation may be performed under the condition of forming the base region having the impurity concentration corresponding to the required breakdown voltage of each bipolar transistor. At this time, the mask process of forming the ion implantation mask needs to be performed every time the ion implantation conditions are different.

[0038]

As described above, according to the semiconductor device of the present invention, the base region of the first bipolar transistor is formed with a lower impurity concentration than the base region of the second bipolar transistor. The bipolar transistor can have a higher breakdown voltage than the second bipolar transistor. In other words, since the base region of the second bipolar transistor can be formed with a higher concentration and shallower than the base region of the first bipolar transistor, it is possible to shorten the base width of the second bipolar transistor, and thus the second bipolar transistor can be shortened. The transistor speed can be increased. Further, according to the semiconductor device in which the bipolar transistor other than the output buffer is formed by the second bipolar transistor, the bipolar transistor other than the output buffer can be speeded up, so that the operating speed of the IC can be improved.

According to the manufacturing method of the present invention, the ion implantation for forming the base region of the first bipolar transistor is performed.
Since the ion implantation for forming the base region of the second bipolar transistor is performed with a low dose amount and high implantation energy, the base region of the second bipolar transistor is formed with a high concentration and a shallower depth than the base region of the first bipolar transistor. it can. Therefore, the speed of the second bipolar transistor can be made higher than that of the first bipolar transistor. Further, according to the manufacturing method in which the bipolar transistor other than the output buffer is formed by the second bipolar transistor, the bipolar transistor other than the output buffer can be sped up, so that the operating speed of the IC can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment relating to a semiconductor device of the present invention.

FIG. 2 is a circuit diagram of a Bi-CMOS inverter.

FIG. 3 is an input / output waveform diagram of a Bi-CMOS inverter.

FIG. 4 is an input / output circuit diagram of Bi-CMOS.

FIG. 5 is a manufacturing process diagram of an example according to the manufacturing method of the present invention.

[Description of Reference Signs] 1 semiconductor device 31 first bipolar transistor 34 first base region 51 second bipolar transistor 54 second base region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (4)

[Claims] 1. A semiconductor device in which a first bipolar transistor and a second bipolar transistor are mounted in the same chip, wherein a base region of the first bipolar transistor is lower in impurity than a base region of the second bipolar transistor. A semiconductor device, which is formed with a high concentration. 2. The semiconductor device according to claim 1, wherein the first bipolar transistor is a bipolar transistor forming an output buffer circuit, and the second bipolar transistor is a bipolar transistor forming a circuit other than the output buffer circuit. A semiconductor device characterized by the above. 3. A method of manufacturing a semiconductor device in which a first bipolar transistor and a second bipolar transistor are mounted in the same chip, wherein the base region of the first bipolar transistor and the base region of the second bipolar transistor are separately ion-implanted. Characterized in that the ion implantation for forming the base region of the first bipolar transistor is performed with a lower dose amount and higher implantation energy than the ion implantation for forming the base region of the second bipolar transistor. And a method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first bipolar transistor is a bipolar transistor that constitutes an output buffer circuit, and the second bipolar transistor is a bipolar transistor that constitutes a circuit other than the output buffer circuit. A method of manufacturing a semiconductor device, which is a transistor.