JPH08213391A - Multilayer interconnection device and its manufacture - Google Patents

Abstract

PURPOSE: To suppress the occurrence of stress migration in second wiring which is formed on an insulating film, connected to first wiring through a contact section, composed mainly of aluminum, and contains crystal grains to prevent the formation of aluminum voids by specifying the orientation of the crystal plane of the second wiring. CONSTITUTION: First Al-Si wiring 103 is formed by forming an Al-Si alloy film on the surface of a first PSG film 102 or silicon substrate 100 by sputtering. When the wiring 103 is formed, almost all the crystal grains on the crystal plane of the Al-Si alloy are oriented in (111)-plane, because the temperature of the substrate 100, pressure of an Ar gas, depositing speed of the Al-Si alloy, etc., are controlled at the time of performing the sputtering. After forming the wiring 103, a second PSG film 104 is formed to cover the wiring 103 and second Al-Si wiring 105 is formed in the same way as that used for the wiring 103 so that the wiring 105 can be electrically connected to the wiring 103 in a contact section. Finally, a surface protective film 106 is formed to stabilize the surface.

Description

Detailed Description of the Invention [0001] TECHNICAL FIELD The present invention is formed in an LSI or the like.
Related to multi-layer wiring, especially tensile stress to the wiring
When miniaturizing an element using a large protective film
Missing that easily occurs in the upper layer wiring (hereinafter referred to as "AL void")
And a method of manufacturing the same
About. [0002] 2. Description of the Related Art In recent years, with the high integration of elements, miniaturization and
Multi-layering has become an essential technology, and as it becomes smaller,
The width of the aluminum wiring is also designed to be thin, and the line width
Becomes less than 2 ~ 3μm, the aluminum wiring
Aluminum (AL) voids are generated. Also, for multiple layers
Therefore, in order to stack various thin films, the internal structure of the device is
When the tress is added, the above-mentioned AL void is generated. This
AL void is commonly known as Electromy
Not caused by abrasion, but stress
It is caused by a new phenomenon called ignition
Of. What is stress migration?
This occurs only on aluminum wiring with a strong protective film.
It is a phenomenon of swelling. The larger the tensile stress, the more aluminum
This phenomenon is more noticeable as the line width of the um wiring becomes narrower.
It Further, in a multi-layer wiring device, the wiring of the upper layer
Is closer to the protective film than the wiring in the lower layer,
It is susceptible to tensile stress, and the lower layer is below the upper layer wiring.
Since there are often steps due to wiring etc., there is a step
And the tensile stress from the protective film acts locally.
In addition, AL voids are more likely to occur. And this
Large AL void caused by tres migration
When it gets worse, it becomes a very big problem in reliability.
For example, aluminum distribution
Wiring due to wire breakage and reduction of aluminum wiring cross-sectional area
Increased resistance, element destruction due to heat generation, delay in operation speed
Etc., and when a large current is applied by operating the element,
Accelerating failure due to electromigration
It becomes easier to mix. This AL void has a large internal stress.
The tensile stress from the ivitation film etc.
The stress is concentrated on the crystal grain boundaries when it is applied to the line and relaxes the stress.
In order to start the movement of AL atoms from grain boundaries, crystals
It is thought to occur when cracks spread from grain boundaries
Have been. On the other hand, the movement of AL atoms at grain boundaries is reduced.
In order to reduce the amount of Cu, Cu, which is easily precipitated at the grain boundary,
Mixing with gold wiring (hereinafter referred to as "AL-Si wiring")
AL-Si-Cu wiring is formed by
Acts as an obstacle against the movement of AL atoms
However, there are reports that the generation of AL voids can be suppressed.
It This is because stress migration from the protective film
Due to the stress received, AL atoms move from inside the crystal grain to the grain boundary.
To move to and migrate due to grain boundary diffusion
It is considered that the addition of Cu is aimed at suppressing the diffusion of
It seems that. [0005] [Problems to be Solved by the Invention]
According to the AL-Si-Cu wiring, there is no occurrence of AL voids.
However, the void ratio Lv is 30 to
Occurrence of 40% AL voids can still be avoided
Aluminum distribution that can further reduce the generation of AL voids
A line is desired. The void ratio Lv referred to here is shown in FIG.
As shown in the perspective view of Fig.
A value expressed by Lv = d / W when the large void value is d
Needless to say, the smaller this void value Lv is,
The occurrence of AL voids is suppressed. Book there
The invention is a multi-layered structure in which a protective film with large tensile stress is formed.
Line, control the film quality of the upper aluminum wiring
By doing so, stress migration is suppressed and AL boy
The purpose is to further reduce the occurrence of dead. [0007] Means for Solving the Problems To achieve the above object,
Therefore, in the first invention of the present application, the semiconductor substrate and the half
A first wiring partly formed on the conductor substrate;
Contact formed on the first wiring and partially removed
Part of the insulating film and its main component is aluminum.
Formed on the insulating film, and through the contact portion.
A second wiring electrically connected to the first wiring,
It is formed on the second wiring and can be stretched by the second wiring.
A protective film that exerts a force, and the second wiring is a crystal
With grains, aluminum atoms move to grain boundaries
The crystal plane is mainly oriented to the (111) plane in order to suppress
A multi-layer wiring device is provided. In the second invention of the present application, on the semiconductor substrate
A first step of partially forming a first wiring on the
Forming an insulating film on the wiring of No. 1 and
A second step of forming a contact portion by removing it partially;
The main component is aluminum, and the crystal faces of the crystal grains are
The second wiring, which is mainly oriented in (111), is connected to the contact.
Front so that it is electrically connected to the first wiring
The third step of forming on the insulating film and the second wiring
A protective film acting on tensile stress is formed on the second wiring.
And a fourth step of forming
A method for manufacturing a device is provided. In the above first and second inventions,
Forming the protective film on the second wiring layer means directly or
The protective film is indirectly connected to the second wiring layer by interposing another layer.
Means forming on top. [0010] [Operation and effect of the invention] Usually, there is a step under the wiring.
Then, crystal planes with various orientations are generated in the step portion.
According to the first invention of the present application, it is easier to connect the second wiring.
This is because the crystal plane is forcibly oriented mainly in the (111) plane.
In the (111) plane, since the AL atoms are the closest packed layer,
Even if tensile stress is applied from the protective film,
It becomes difficult for AL atoms to move from inside the crystal grain to the grain boundary,
No voids on the top, and therefore stress my gray
Can reduce the generation of AL voids
Has the effect of According to the second invention of the present application, the strike
Manufacturing multi-layer wiring device with less migration
There is an effect that can be. [0012] BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention shown in the drawings are as follows.
Will be described in detail. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor device for explaining
100 is a silicon substrate, 101 is a silicon substrate 100
Partially on the silicon nitride film (Si₃N _Four) Form
Formed by thermal oxidation using the silicon nitride film of
LOCOS as a formed field insulating film.
After removing the silicon nitride film, vapor deposition or CV
As an insulating film by D (Chemical Vapor Deposition) method
Of, for example, a first PSG (phosphorus glass) film 102 is formed.
Then, the first AL
-Si wiring 103 is partially electrically connected to the silicon substrate 100.
It is formed so as to be electrically connected. Here, the first AL, which is the main part of this embodiment,
First, the Si wiring 103 is made of AL by the sputtering method.
-Si alloy film as the first PSG film 102 or silicon
It is formed on the substrate 100. At that time, the AL-Si alloy
The crystal plane is the substrate heating temperature during sputtering, Ar gas
Pressure, AL-Si alloy deposition rate, type and amount of residual gas, etc.
Most of the crystal grains become (111) plane by controlling
It is oriented. And the AL-Si alloy is
For example, the line width is 2 μm and the AL crystal grains
The grain size of 0.7 μm, which is about 1/3 of the line width,
By patterning and then performing heat treatment for a predetermined time
Formed. In order to orient the crystal plane to the (111) plane
For example, when focusing on substrate heating as a
5 Add the substrate as shown in the graphs of (a) and (b).
When heated (Fig. (A)), it has various crystallographic orientations.
On the other hand, when the substrate is not heated ((b) in the figure),
It is oriented in the (111) plane. However, do not heat the substrate
Step coverage of aluminum alloy wiring deteriorates
In addition, since the grain size of AL crystal grains is very small, Si
Will start to become a problem. Therefore, a suitable group
It is necessary to perform sputtering at the plate temperature. Then, the first AL-Si wiring 103 is formed.
The second layer is formed by vapor deposition or CVD so as to cover the top.
The PSG film 104 is formed and the first AL-Si alignment line 10 is formed.
The part that corresponds to the contact part for making electrical connection with 3
Partially etched away. Next, at the contact part
In order to electrically connect with the first AL-Si wiring 103
The second AL-Si wiring 105 is replaced with the first AL-Si wiring 1
It is formed in the same way as 03, and finally, to stabilize the surface,
A table formed of, for example, a silicon nitride film or the like by the Zuma CVD method or the like.
The surface protection film 106 is formed. In addition, 107 is a polycrystalline silicon
Is a wiring layer composed of Therefore, according to this embodiment, the AL-Si alloy is used.
Most of the crystal planes during deposition of (111)
As described above, the (111) plane is the closest packed plane.
Therefore, the AL atom is restrained from moving by other AL atoms.
Which reduces the internal stress of aluminum alloy wiring.
The movement of AL atoms to grain boundaries for
There is an effect that the occurrence of can be almost eliminated.
Next, the above will be explained based on the experimental results of the present inventor.
It In FIG. 4, the horizontal axis represents the angular position 2θ and the vertical axis represents the diffraction intensity.
The magnitude of the diffraction intensity due to the orientation of the crystal plane and the
FIG. 4 is a graph showing the value of void ratio Lv, and FIG.
(A) is the value of the first embodiment. The high diffraction intensity
The size is, for example, as shown in the schematic top view of FIG.
It was measured by a fractometer. This diffractome
In brief, the flat sample 10 (in this example,
AL-Si alloy is formed on the mating surface)
Mounted on a table 11 that rotates around a vertical axis O
On the target 13 of the X-ray tube 12 as an X-ray source.
The divergent X-ray emitted from the linear focus 14 is passed through the slit 15.
After diffracted by the flat sample 10, the slit 16 is focused.
It is configured to connect points and enter the counting tube 17,
Run by moving the degree position 2θ in a direction that increases at a constant angular velocity
X-ray diffraction that enters the counter 17 at that time
It measures the strength. The angle position 2θ is the scale plate.
Read at 18. The diffraction intensity of this embodiment is measured by using such an apparatus.
As a result of the measurement, as shown in the graph of FIG.
The diffraction intensity is highest when the crystal plane is the (111) plane.
Therefore, the diffraction intensity on other crystal planes is small on the (200) plane.
The values were only measured, and the diffraction intensity of the (111) plane
I₁₁₁, The highest diffraction intensity in other crystal planes (in this case
Diffraction intensity of (200) plane is 1_abcAnd then I₁₁₁
/ I_abc= 510, and the void rate Lv at that time is Lv
= 0%, which is an epoch-making value.
Most of the crystal faces are (111) faces,
It has an excellent effect that it can be almost eliminated.
Becomes FIG. 4 (b) shows the crystal of AL-Si alloy.
In this example, the planes are mainly oriented to the (111) plane,
I₁₁₁/ I_abc= 2.1. Also in this example
Depletion rate Lv = 10%, and the occurrence of AL voids is compared with the conventional
The effect is that it can be significantly reduced. Fig. 4 (c)
Indicates the value of the conventional AL-Si alloy for reference,
It has various crystallographic orientations and its diffraction intensity is (220)
Largest in terms of size, I₁₁₁/ I_abc= 0.7, Lv = 43
%. I in FIG.₁₁₁/ I_abcAnd the void rate Lv
The graph which shows a relationship is shown. As you can see from the graph
I₁₁₁/ I_abcIf ≧ 1, the void ratio Lv is approximately 30% or less
Since it is below, some effect can be obtained, and I₁₁₁/ I_abc
If ≧ 2, the void ratio Lv is about 10% or less, which is considerably
The effect of is obtained. The diffraction intensity in the above invention is
In the process of forming the AL-Si wiring,
AL-Si, which is the value when the L-Si alloy was deposited.
The diffraction intensity or the crystal plane after forming the wiring may be used.
FIGS. 5 (b) and 5 (c) respectively show sputtering.
Deposition of AL-Si alloy containing 3% Si without heating the substrate
The value of diffraction intensity ((b) in the same figure) when
The L-Si alloy has undergone a photo-etching process and a heat treatment process.
In the graph which shows the value of the diffraction intensity after that ((c) in the same figure)
Yes, the diffraction intensity on the (111) plane is small after heat treatment.
Although it is getting smaller, the crystal plane is still mainly (11
1) It is oriented in the plane and the void ratio Lv at this time is also during deposition
It is almost the same as the void ratio Lv. According to the first embodiment, the AL crystal grains are
Particle size (hereinafter referred to as "AL particle size") of AL-Si wiring
Since it is about 1/3 of the line width, the grain boundary in the AL-Si wiring
It can be reduced, and the movement of AL atoms can be suppressed accordingly.
Wear. FIG. 9 shows the results of experiments conducted by the present inventor.
It is a graph which shows the value of the void rate Lv with respect to it. Graph
As can be seen, the AL particle size is larger than the void ratio Lv.
The larger the AL particle size is, the more the void ratio Lv becomes.
Get smaller. For example, in this experiment, the base material is the CVD method.
The line width of the silicon nitride film and the AL-Si wiring by 3.6 is 3.6.
μm, and the AL particle size is 0.8 μm, that is, about 1 / the line width.
When it is 4 or more, the void ratio Lv = 0%. or,
AL particle size is 0.25 μm, that is, about 1/14 or more of line width
If so, the void ratio Lv will be 30% or less, so
The effect is obtained. Here, if the AL particle size is too large, crystals
There is a possibility that the grain boundaries of the grains will cross the wiring, and conversely, slit-like
AL void will occur. Therefore, on the AL particle size
The limit is about the same as the line width, and the occurrence of AL voids
The range of AL particle size that can be suppressed is AL particle size L, line width
If W is Further, according to the first embodiment, the first A
Under the L-Si wiring 103 and the second AL-Si wiring 105
A first PSG film 102 and a second P
The SG film 104 is formed, and both are oxide films.
To A formed thereon as shown in FIGS. 6 and 7.
It is easy to orient the crystal plane of the L-Si alloy mainly to the (111) plane
In addition, the oxide film has a higher binding energy than the nitride film.
Since the size is small, the bond can be easily broken and bonded to the AL atom.
The energy consumption of AL atoms is small
Therefore, it becomes easy to increase the crystal grain size. In addition, the acid
The internal stress of the oxide film is smaller than that of the nitride film.
The stress applied to the i wiring is also reduced and the AL voids are not generated.
The effect is that it can be reduced. Figures 6 and 7 are below
Due to the difference in the crystal plane of AL-Si wiring deposited on the ground material
Is a graph showing the value of the diffraction intensity,
In FIG. 6 (a), nitriding formed by plasma CVD method
The film P-SiN, FIG. 6 (b), is formed by the CVD method.
Silicon nitride film Si₃N _Four, FIG. 7 (a) is a CVD method.
The PSG film formed by
Is a BPSG film formed by FIG. 6 (a),
In the nitride film shown in (b), I₁₁₁/ I_abcThe value of
0.6 and 0.58, while FIG. 7 (a),
The oxide film shown in (b) is relatively large, 2.1 and
1.2, and if the underlying material is an oxide film, the (111) plane
It can be seen that the orientation is easy. The oxide film is not limited
SiO by the CVD method without₂Film, plasma CVD method
It may be an oxide film or the like formed by. Next, a second embodiment of the present invention will be described with reference to FIG.
It demonstrates using the cross-sectional view of a body device. The configuration shown in FIG. 1 is required.
Components that can be formed by the same manufacturing method as
No., and detailed description thereof is omitted. In this example
However, the first AL-Si wiring 103 is crystallized as described above.
Planes are mainly oriented in the (111) plane, and
The particle size should be within the range of 1/4 to 1 / 1.5 of the line width.
Is formed in. The present embodiment is adopted for a large aspect ratio.
It is effective when used, and the first AL-Si wiring 10
3 and the plasma CVD method on the first PSG film 102.
Forming a P-SiN film 1041 and applying a resist
If the entire surface is dry-etched after flattening the surface
So-called etch back is performed, and the P
A PSG film on the SiN film 1041 by, for example, a CVD method
After forming 1042, the contact portion is partially removed.
Then, as in the first embodiment, the second AL-Si wiring 10 is formed.
5 is formed. Therefore, also in this embodiment, the crystal plane is mainly used.
Since it is oriented in the (111) plane and its grain size is controlled,
Although the same effect as the first embodiment can be obtained,
Normally, when performing etch back, etch with the resist
The material under the resist is a nitride film to equalize the etching speed.
This nitride film is used as a base material for the second AL-Si wiring.
Is formed, but in this embodiment, as the nitride film
Forming a PSG film 1042 on the P-SiN film 1041 of
The PSG film 1042 as a base material
Since the AL-Si wiring 105 is formed, as described above.
Since the AL-Si wiring 105 is formed on the
The crystal plane of AL-Si alloy is mainly oriented to the (111) plane
There is an effect that it becomes easier to do. Next, a third embodiment of the present invention will be described with reference to FIG.
It demonstrates using the cross-sectional view of a body device. In this example
Is the first AL-Si wiring 103 and the first PSG film.
A thin silicon nitride film (Si₃N_Four) 104
3 was formed, and ethanol and S were added to the recesses present at this time.
iO₂On Glass (SOG) 10
44 is applied and then heat-cured. And P on it
SG film 1045 is formed and the contact part is partially removed.
Then, the second AL-Si wiring 105 is formed. Book there
Even in the structure as in the example, the crystal plane of the AL-Si alloy
Is mainly oriented in the (111) plane, and the grain size is 1/4 to 1
/1.5, the first and second AL-Si
Since the underlying material of the wirings 103 and 105 is an oxide film, the first
The same effect as the embodiment can be obtained. The present invention is limited to the above-mentioned first to third embodiments.
Various modifications are possible without departing from the spirit of the policy
For example, the component of the second wiring according to the present invention is
If the main component of AL is AL, then the E-gun method
Aluminum wiring or AL-Si wiring
Wire, AL-Si-Cu wiring, AL-Si-Ti wiring, etc.
There may be. In addition, in the above-mentioned embodiment, although the two-layer wiring is used,
A wiring structure of more than one layer may be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device for explaining a first embodiment of the present invention. FIG. 2 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor device for explaining a third embodiment of the present invention. FIG. 4A is a graph showing the magnitude of diffraction intensity due to the orientation of the crystal plane and the value of the void ratio Lv at that time. (B) A graph showing the magnitude of diffraction intensity due to the orientation of the crystal plane and the value of the void ratio Lv at that time. (C) A graph showing the magnitude of diffraction intensity due to the orientation of the crystal plane and the value of the void ratio Lv at that time. FIG. 5 (a) is a graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. (B) A graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. (C) A graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. FIG. 6A is a graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. (B) A graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. FIG. 7A is a graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. (B) A graph showing the magnitude of diffraction intensity due to the orientation of crystal planes. FIG. 8 is a graph showing the relationship between I ₁₁₁ / I _abc and the void ratio Lv. FIG. 9 is a graph showing the relationship between the AL particle size and the void ratio Lv. FIG. 10 is a schematic top view of a diffractometer. FIG. 11 is a perspective view for explaining a void rate. [Description of Reference Signs] 100 Silicon substrate 101 LOCOS 102 First PSG film 103 First AL-Si wiring 104 Second PSG film 105 Second AL-Si wiring 106 Surface protective film 1041 P-SiN film 1042 PSG film 1043 Silicon nitride film 1044 SOG 1045 PSG film

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[Procedure amendment] [Date of submission] February 21, 1996 [Procedure amendment 1] [Document name for amendment] Statement [Item name for amendment] Figure 4 [Correction method] Change [Correction content] [Figure 4] 6 is a graph showing the magnitude of diffraction intensity due to the orientation of crystal planes and the value of void ratio Lv at that time.

Claims (1)

What is claimed is: (1) A semiconductor substrate, a first wiring partially formed on the semiconductor substrate, and a contact portion formed on the first wiring and partially removed. An insulating film, a second wiring whose main component is aluminum, which is formed on the insulating film, and which is electrically connected to the first wiring through the contact portion, and on the second wiring And a protective film that acts on the second wiring to exert a tensile stress, and the second wiring has crystal grains and its crystal is formed to prevent aluminum atoms from moving to grain boundaries. A multilayer wiring device in which the planes are mainly oriented in the (111) plane. (2) The multilayer wiring device according to claim 1, wherein the insulating film is a film whose surface is flattened. (3) The multi-layer wiring device according to claim 2, wherein the insulating film is composed of a silicon nitride film whose surface is flattened and a silicon oxide film formed on the silicon nitride film. . (4) The multilayer wiring device according to claim 2, wherein the insulating film is formed by forming a silicon oxide film on spin-on-glass. (5) Patent Document wherein the grain diameter of the second wiring is adjusted so that (W / 14) <L <W is satisfied, where L is the grain diameter and W is the wiring width. The multilayer wiring device according to any one of claims 1 to 4. (6) The multilayer according to claim 5, wherein the grain size of the crystal grains is adjusted so that the grain size satisfies (W / 4) <L <(W / 1.5). Wiring device. (7) the crystal, if the diffraction intensity at (111) plane by X-ray diffraction I _111, the the largest among the diffraction intensity of the other plane was I _abc, satisfying the I ₁₁₁ / I _abc ≧ 2 7. The multi-layer wiring device according to claim 1, wherein the multi-layer wiring device is oriented as described above. (8) The multilayer wiring device according to any one of claims 1 to 7, wherein the protective film is a silicon nitride film. (9) The multilayer wiring device according to any one of claims 1 to 8, wherein the wiring width of the second wiring is 3 μm or less. (10) A first step of partially forming a first wiring on a semiconductor substrate, forming an insulating film on the first wiring, and partially removing the insulating film to form a contact portion. The second step of forming and the second wiring whose main component is aluminum and whose crystal faces of crystal grains are mainly oriented in (111) are electrically connected to the first wiring through the contact portion. A third step of forming on the insulating film so as to make a physical connection, and a fourth step of forming on the second wiring a protective film that exerts a tensile stress on the second wiring. And a method for manufacturing a multilayer wiring device. (11) The method of manufacturing a multilayer wiring device according to claim 10, wherein the second step is a step including a step of flattening a surface of the insulating film. (12) In the second step, a silicon nitride film is formed on the first wiring, a resist is applied on the silicon nitride film to flatten the surface, and then dry etching is performed to perform the silicon nitride film. The method for manufacturing a multilayer wiring device according to claim 11, which is a step of flattening a surface of the substrate and further forming a silicon oxide film on the silicon nitride film. (13) The second step is a step of applying spin-on glass to the recesses existing after the first step and curing the spin-on glass to form a silicon oxide film on the spin-on glass. A method for manufacturing the multilayer wiring device described. (14) In the third step, when the grain diameter of the second wiring is L and the wiring width is W, the grain diameter of the crystal grains is set to satisfy (W / 14 <L <W). The process according to claims 10 to 13 which is a step of forming the film to be adjusted.
Item 8. A method for manufacturing a multilayer wiring device according to any one of items. (15) The method for manufacturing a multilayer wiring device according to any one of claims 10 to 14, wherein the fourth step is a step of forming a silicon nitride film as the protection by plasma CVD. (16) The third step is a step of forming the second wiring by sputtering.
Item 16. A method for manufacturing a multilayer wiring device according to any one of items 1 to 15.