JP2815831B2 - Multilayer wiring device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to an LSI and the like.
The multi-layer wiring, especially the tensile stress on the wiring
When miniaturizing devices using protective films with large
Missing easily occurring in the upper wiring (hereinafter referred to as “AL void”
) And a method for manufacturing the same
About. [0002] 2. Description of the Related Art In recent years, along with the high integration of elements, miniaturization and
Multilayering has become an essential technology, and as miniaturization continues,
And the line width of the aluminum wiring is designed to be narrow,
Becomes smaller than 2-3 μm,
Aluminum (AL) voids are generated. Also for multi-layer
Therefore, in order to stack various thin films, the internal structure of the device must be adjusted.
The tress is added, and the above-described AL void occurs. This
AL void is commonly called Electromy
It is not caused by
It is caused by a new phenomenon called irrigation
It is. Stress migration is
Only occurs on aluminum wiring with a strong protective film.
This is the phenomenon. The higher the tensile stress, the more aluminum
This phenomenon is more noticeable as the line width of the
You. In a multi-layer wiring device, an upper wiring
Is closer to the protective film than the underlying wiring,
It is susceptible to tensile stress, and the lower layer is located below the upper layer wiring.
There is often a step due to the wiring of
And the tensile stress from the protective film acts locally.
And AL voids are more likely to occur. And this
Large AL void caused by tress migration
When it becomes difficult, it becomes a very big problem in reliability.
For example, even if the element is not operated (energized),
Wire breakage, wiring due to reduction in cross-sectional area of aluminum wiring
Increase in resistance, element destruction due to heat generation, delay in operation speed
Etc., and when the element is operated and a large current is applied,
Electromigration causes accelerated failure
It becomes easy to read. [0004] This AL void has a large internal stress.
The tensile stress from the passivation film
The stress concentrates on the grain boundaries in addition to the wire, relieving the stress
As AL atoms begin to move from grain boundaries
It is thought to be caused by the spread of cracks from grain boundaries
Have been. In contrast, the movement of AL atoms at grain boundaries is reduced.
To reduce the amount of Cu, which is likely to precipitate at the grain boundaries,
Mix with gold wiring (hereinafter referred to as “AL-Si wiring”)
To form an AL-Si-Cu wiring, and convert Cu to an AL atom.
Acts as an obstacle to the air and suppresses the movement of AL atoms
However, there are reports that the generation of AL voids can be suppressed.
You. This is because the stress migration
Due to the stress received, AL atoms are converted from grain boundaries to grain boundaries.
Migration due to grain boundary diffusion
It is considered that the addition of Cu is intended to suppress the diffusion of Cu.
Seems to be. [0005] SUMMARY OF THE INVENTION
According to the AL-Si-Cu wiring, the generation of AL voids
Although the degree can be suppressed, the void ratio Lv is 30 to
The generation of 40% AL voids can still be avoided
Aluminum distribution that can further reduce the occurrence of AL voids
Lines are desired. Incidentally, the void ratio Lv mentioned here is shown in FIG.
As shown in the perspective view of FIG.
When the large void value is d, a value represented by Lv = d / W
Needless to say, the smaller the void value Lv is,
This means that the occurrence of AL voids is suppressed. So book
The present invention relates to a multilayer arrangement in which a protective film having a large tensile stress is formed.
Control of film quality of upper layer aluminum wiring
By reducing stress migration, AL Boy
The purpose is to further reduce the occurrence of noise. [0007] Means for Solving the Problems To achieve the above object,
Therefore, in the first invention of the present application, the semiconductor substrate and the semiconductor substrate
A first wiring partially formed on a conductive substrate;
Contact formed on one wiring and partially removed
Part of the insulating film and its main component is aluminum
Formed on the insulating film, and through the contact portion.
A second wiring electrically connected to the first wiring by
The second wiring is formed on the second wiring, and is pulled by the second wiring.
And a protective film acting on the second wiring.
Aluminum particles move to the grain boundaries
The crystal plane is mainly oriented to the (111) plane in order to suppress
The present invention provides a multilayer wiring device characterized in that: [0008] In the second invention of the present application, on a semiconductor substrate
A first step of partially forming a first wiring in the
And forming an insulating film on the wiring of the first wiring.
A second step of forming a contact portion by separating the contact,
The main component is aluminum, and the crystal plane of the crystal grains is
The second wiring mainly oriented to (111) is formed by the contactor
Before being electrically connected to the first wiring through the
Forming a third step on the insulating film;
Forming a protective film for applying a tensile stress on the second wiring;
And a fourth step of forming
An apparatus manufacturing method is provided. In the first and second aspects of the present invention,
Forming the protective film on the second wiring layer means directly or
Indirectly through another layer, a protective film is formed on the second wiring layer.
It means to form on. [0010] [Operation and Effect of the Invention] Usually, there is a step under the wiring.
And crystal planes of various orientations are generated at the steps
According to the first invention of the present application, the connection of the second wiring is facilitated.
The crystal plane was forcibly oriented mainly to the (111) plane.
In the (111) plane, AL atoms become the densest surface film.
Even when tensile stress from the protective film is applied,
It becomes difficult for AL atoms to move from inside the crystal grain to the grain boundary.
No voids on the socket
And reduce the occurrence of AL voids
It has the effect of According to the second aspect of the present invention, the strike
Manufacture multilayer wiring equipment with less migration
It has the effect of being able to do so. [0012] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described in detail with reference to FIG. FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor device for explaining
100 is a silicon substrate, 101 is on the silicon substrate 100
Partially silicon nitride film (Si_ThreeN _Four) To form
Thermal oxidation using the silicon nitride film
LOCOS as a field insulating film to be formed.
Then, after removing the silicon nitride film, vapor deposition or CV
As an insulating film by D (Chemical Vapor Deposition) method
For example, the first PSG (phosphorus glass) film 102 is formed.
Then, the first AL is formed, for example, by a sputtering method.
A part of the Si wiring 103 is connected to the silicon substrate 100;
It is formed so as to be air-connected. Here, the first AL which is a main part of this embodiment is
-Si wiring 103 is formed by AL
The first PSG film 102 or silicon
Formed on the substrate 100. At that time, the AL-Si alloy
The crystal plane is the substrate superheating temperature during sputtering, Ar gas
Pressure, deposition rate of AL-Si alloy, type and amount of residual gas, etc.
By controlling the temperature, most of the crystal grains become (111) plane.
Oriented. Then, the AL-Si alloy is
For example, the line width is 2 μm and AL crystal grains
Is 0.7 μm, which is about 1/3 of the line width.
Pattern and then heat treatment for a predetermined time.
Formed. In order to orient the crystal plane to the (111) plane,
For example, if attention is paid to substrate heating,
5 As shown in the graphs of FIGS.
When heated (Fig. (A)), it has various crystal orientations.
On the other hand, when the substrate is not heated (FIG. 4B),
Orient to the (111) plane. However, do not heat the substrate
Coverage of aluminum alloy wiring deteriorates
In addition, since the grain size of AL crystal grains becomes very small,
Is a problem. Therefore, a suitable group
It is necessary to perform sputtering at the plate temperature. The first AL-Si wiring 103
The second is formed by vapor deposition or CVD so as to cover the top.
A PSG film 104 is formed, and the first AL-Si alignment line 10 is formed.
The part corresponding to the contact part for making the electrical connection with 3
Partially etched away. Next, at the contact part
In such a way as to be electrically connected to the first AL-Si wiring 103
The second AL-Si wiring 105 is connected to the first AL-Si wiring 1
03, and finally a plastic to stabilize the surface.
A table made of, for example, a silicon nitride film by a plasma CVD method or the like.
The surface protection film 106 is formed. 107 is a polycrystalline silicon
This is a wiring layer composed of components. Therefore, according to the present embodiment, the AL-Si alloy
Crystal plane at the time of deposition is almost oriented to (111) plane
And the (111) plane is the closest plane as described above.
For this reason, AL atoms are restrained from moving by other AL atoms.
Thereby alleviating the internal stress of aluminum alloy wiring
Movement of AL atoms to the grain boundary due to neutrons is suppressed and AL voids
This has the effect of almost eliminating the occurrence.
Next, the above will be described based on the experimental results of the inventor.
You. FIG. 4 shows the angular position 2θ on the horizontal axis and the diffraction intensity on the vertical axis.
The magnitude of the diffraction intensity due to the orientation of the crystal plane and the
FIG. 4 is a graph showing the value of void ratio Lv, and FIG.
(A) is the value of the first embodiment. In addition, large diffraction intensity
The size is, for example, as shown in the schematic top view of FIG.
It was measured by a fractometer. This diffractome
A brief description of the sampler is as follows.
(AL-Si alloy is formed on the joint surface)
Mounted on a platform 11 that rotates about a vertical axis O
On the target 13 of the X-ray tube 12 as an X-ray source
Divergent X-rays emitted from the linear focus 14 are passed through the slit 15
After being diffracted by the flat sample 10, the slit 16 is focused.
It is configured to connect the points and to enter the counter tube 17,
Angle position 2θ at constant angular velocity
The X-ray diffraction that enters the counter tube 17 at that time
It measures the strength. The angle position 2θ is a scale plate
Read at 18. Using such an apparatus, the diffraction intensity of this embodiment can be reduced.
As a result of the measurement, as shown in the graph of FIG.
The diffraction intensity is highest when the crystal plane is the (111) plane.
And the diffraction intensity at other crystal planes is slight at the (200) plane.
The value was only measured, and the diffraction intensity of the (111) plane was
I₁₁₁, The highest diffraction intensity on other crystal planes (in this case
(Diffraction intensity of (200) plane)_abcThen I₁₁₁
/ I_abc= 510, and the void ratio Lv at that time is Lv
= 0%, an AL-Si alloy
By making the crystal plane almost (111) plane, AL void
It has the excellent effect that generation can be almost eliminated.
And FIG. 4 (b) shows the AL-Si alloy as a crystal.
This is an example in which the plane is mainly oriented to be a (111) plane,
I₁₁₁/ I_abc= 2.1. Boy in this example
Rate Lv = 10%, and comparison of AL void generation with conventional
This has the effect that it can be considerably reduced. Fig. 4 (c)
Indicates the value of the conventional AL-Si alloy for reference,
It has various crystal orientations and its diffraction intensity is (220)
The largest in terms of I₁₁₁/ I_abc= 0.7, Lv = 43
%. FIG.₁₁₁/ I_abcAnd the void fraction Lv
3 shows a graph showing the relationship. As you can see from the graph
I₁₁₁/ I_abcIf ≧ 1, the void ratio Lv is approximately 30% or less.
As a result, a certain effect can be obtained.₁₁₁/ I_abc
If ≧ 2, the void ratio Lv is substantially less than 10%,
The effect of is obtained. The diffraction intensity in the above invention is
Alternatively, the crystal plane may cause A-Si wiring during the formation process.
The value at the time of deposition of the L-Si alloy is AL-Si
The diffraction intensity or the crystal plane after forming the wiring may be used.
FIGS. 5 (b) and (c) show the results at the time of sputtering, respectively.
Deposit AL-Si alloy containing 3% Si without heating the substrate
The value of the diffraction intensity at the time of
L-Si alloy passed through photo-etching process and heat treatment process
A graph showing the value of the diffraction intensity after that (FIG. 3 (c)).
And the diffraction intensity on the (111) plane is low after heat treatment.
Despite the small size, the crystal face is still mainly (11
1) It is oriented on the plane, and the void ratio Lv at this time is also
Is substantially the same as the void ratio Lv. According to the first embodiment, AL crystal grains
Particle diameter (hereinafter referred to as “AL particle diameter”) of the AL-Si wiring
Since it is about 1/3 of the line width, the grain boundary in the AL-Si wiring
Can be reduced and the movement of AL atoms can be suppressed
Wear. FIG. 9 shows the experimental results of the present inventors.
It is a graph which shows the value of the void ratio Lv with respect to. Graph
As can be seen, the AL particle size is large with respect to the void fraction Lv.
The larger the AL particle size, the larger the void fraction Lv
Become smaller. For example, in this experiment, the base material was CVD
Line width of silicon nitride film and AL-Si wiring is 3.6
μm, and the AL particle size is 0.8 μm, that is, about 1 / l of the line width.
When it is 4 or more, the void ratio Lv = 0%. or,
AL particle size is 0.25μm, more than about 1/14 of line width
Then, the void ratio Lv becomes 30% or less.
The effect is obtained. Here, if the AL particle size is too large,
There is a possibility that grain boundaries may cross the wiring, and conversely, slit-like
AL voids occur. Therefore, AL particle size
The limit is about the same as the line width, and the occurrence of AL voids
The range of AL particle size that can be suppressed is AL particle size L, line width
Is W,Further, according to the first embodiment, the first A
Below the L-Si wiring 103 and the second AL-Si wiring 105
The first PSG film 102 and the second P
SG film 104 is formed, and both are oxide films
6A and 6A to 7C.
The crystal plane of the L-Si alloy is easily oriented mainly to the (111) plane.
The oxide film has a higher binding energy than the nitride film.
Easily breaks the bond due to small size and bonds with AL atom
Energy consumption of the AL atom is small.
Therefore, it is easy to increase the crystal grain size. In addition, acid
Since the internal stress of the oxide film is smaller than that of the nitride film, AL-S
The stress applied to the i-wiring is also reduced and the generation of AL voids
This has the effect of being able to reduce the Figures 6 and 7 are below
Due to the difference in crystal plane of AL-Si wiring deposited on the ground material
FIG. 6 is a graph showing the value of the diffraction intensity.
FIG. 6 (a) shows a nitride formed by a plasma CVD method.
The film P-SiN, FIG. 6 (b) is formed by the CVD method.
Silicon nitride film Si_ThreeN _FourFIG. 7 (a) shows the CVD method.
FIG. 7 (b) shows a PSG film formed by CVD.
This is a BPSG film formed from FIG. 6 (a),
In the nitride film shown in FIG.₁₁₁/ I_abcIs the value of
In contrast to 0.6 and 0.58, FIG.
The oxide film shown in FIG.
1.2 if the underlying material is an oxide film (111) plane
It can be seen that orientation is easy. The oxide film is limited.
SiO without CVD_TwoFilm, plasma CVD method
An oxide film formed by the method described above may be used. Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to a cross-sectional view of the body device. The configuration shown in FIG.
Components that can be formed by the same manufacturing method as
Numbers are attached and detailed description is omitted. In this embodiment
However, the first AL-Si wiring 103 is crystallized as described above.
So that the plane is mainly oriented to the (111) plane, and
Particle size should be in the range of 1/4 to 1 / 1.5 of line width
Is formed. This embodiment is applied to the case where the aspect ratio is large.
The first AL-Si wiring 10 is effective when used.
3 and the plasma CVD method on the first PSG film 102
To form a P-SiN film 1041 and apply a resist.
Dry etching the entire surface after flattening the surface
So-called etch back,
-PSG film on SiN film 1041 by, for example, CVD method
After forming 1042, the contact portion is partially removed.
Thus, the second AL-Si wiring 10 is formed in the same manner as in the first embodiment.
5 are formed. Therefore, also in this embodiment, the crystal plane is mainly
Since it is oriented on the (111) plane and its grain size is controlled
Although the same effects as in the first embodiment can be obtained,
Normally, when performing etch back, etch back with resist
The material under the resist is a nitride film to equalize the
The second AL-Si wiring is formed using this nitride film as a base material.
Is formed, but in this embodiment, the nitride film is
A PSG film 1042 on the P-SiN film 1041 of FIG.
And using the PSG film 1042 as a base material for the second
As described above, since the AL-Si wiring 105 is formed.
Since the AL-Si wiring 105 is formed in
The crystal plane of AL-Si alloy is mainly oriented to (111) plane
There is an effect that it becomes easy to perform. Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to a cross-sectional view of the body device. In this embodiment
Denotes a first AL-Si wiring 103 and a first PSG film
102, a thin silicon nitride film (Si_ThreeN_Four) 104
3 is formed, and ethanol and S
iO_TwoSpin-on-Glass (SOG) 10
44 is applied and then thermally cured. And P on it
An SG film 1045 is formed, and a contact portion is partially removed.
Then, a second AL-Si wiring 105 is formed. So book
The crystal plane of the AL-Si alloy also in the structure as in the embodiment
Are mainly oriented to the (111) plane, and the grain size is 1/4 to 1
/1.5 and the first and second AL-Si
Since the underlying material of the wirings 103 and 105 is an oxide film, the first
The same effect as that of the embodiment can be obtained. The present invention is limited to the first to third embodiments.
Various modifications are possible without deviating from the gist without being specified
For example, the component of the second wiring according to the present invention is
Should be AL as the main component, and therefore the E-gun method
Aluminum wiring or AL-Si wiring
Wire, AL-Si-Cu wiring, AL-Si-Ti wiring, etc.
There may be. In the above embodiment, the wiring is a two-layer wiring.
A wiring structure having more than one layer may be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device for explaining a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor device for describing a third embodiment of the present invention. FIG. 4 is a graph showing the magnitude of diffraction intensity depending on the orientation of a crystal plane and the value of void ratio Lv at that time. FIG. 5A is a graph showing the magnitude of diffraction intensity depending on the orientation of a crystal plane. (B) A graph showing the magnitude of the diffraction intensity depending on the orientation of the crystal plane. (C) is a graph showing the magnitude of the diffraction intensity depending on the orientation of the crystal plane. FIG. 6A is a graph showing the magnitude of diffraction intensity depending on the orientation of a crystal plane. (B) A graph showing the magnitude of the diffraction intensity depending on the orientation of the crystal plane. FIG. 7A is a graph showing the magnitude of diffraction intensity depending on the orientation of a crystal plane. (B) A graph showing the magnitude of the diffraction intensity depending on the orientation of the crystal plane. FIG. 8 is a graph showing a relationship between I ₁₁₁ / I _abc and a void fraction Lv. FIG. 9 is a graph showing the relationship between the AL particle size and the void fraction Lv. FIG. 10 is a schematic top view of the diffractometer. FIG. 11 is a perspective view for explaining a void ratio. [Description of Reference Numerals] 100 Silicon substrate 101 LOCOS 102 First PSG film 103 First AL-Si wiring 104 Second PSG film 105 Second AL-Si wiring 106 Surface protection film 1041 P-SiN film 1042 PSG film 1043 silicon nitride film 1044 SOG 1045 PSG film

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kazunori Kawamoto               1-1-1 Showa-cho, Kariya-shi, Aichi Japan               Denso Co., Ltd.                (56) References JP-A-63-152147 (JP, A)

Claims (1)

(57) Claims: (1) a semiconductor substrate; a first wiring partially formed on the semiconductor substrate; and a contact partially formed on the first wiring and partially removed. An insulating film having a portion, a main component of which is aluminum, a second wiring formed on the insulating film, and electrically connected to the first wiring via the contact portion; A protective film formed on a wiring and acting on the second wiring to apply a tensile stress, wherein the second wiring has crystal grains and suppresses movement of aluminum atoms to grain boundaries. A multilayer wiring device characterized in that its crystal plane is mainly oriented to the (111) plane. (2) The multilayer wiring device according to claim 1, wherein the insulating film is a film whose surface is planarized. 3. The multilayer wiring device according to claim 2, wherein said insulating film comprises a silicon nitride film having a planarized surface and a silicon oxide film formed on said silicon nitride film. . (4) The multilayer wiring device according to claim 2, wherein the insulating film is formed by forming a silicon oxide film on spin-on glass. (5) A patent wherein the grain size of the crystal grains of the second wiring is adjusted so as to satisfy (W / 14) <L <W, where L is the particle size and W is the wiring width. The multilayer wiring device according to claim 1. (6) The multilayer according to claim 5, wherein the grain size of the crystal grains is adjusted so as to satisfy (W / 4) <L <(W / 1.5). Wiring device. (7) The crystal satisfies I ₁₁₁ / I _abc ≧ 2 when the diffraction intensity on the (111) plane by X-ray diffraction is I ₁₁₁ and the largest one among the diffraction intensities on other planes is I _abc. The multilayer wiring device according to any one of claims 1 to 6, wherein the multilayer wiring device is oriented so as to perform. (8) The multilayer wiring device according to any one of claims 1 to 7, wherein the protective film is a silicon nitride film. (9) The multilayer wiring device according to any one of claims 1 to 8, wherein a wiring width of the second wiring is 3 µm or less. (10) a first step of partially forming a first wiring on a semiconductor substrate; forming an insulating film on the first wiring; and partially removing the insulating film to form a contact portion. Forming a second wiring, in which a main component is aluminum, and a second wiring in which a crystal plane of a crystal grain is mainly oriented to (111) is electrically connected to the first wiring via the contact portion. And a fourth step of forming a protective film on the second wiring, which applies a tensile stress to the second wiring, so that the third wiring is formed on the insulating film so as to make an electrical connection. A method for manufacturing a multilayer wiring device, comprising: 11. The method according to claim 10, wherein the second step includes a step of flattening a surface of the insulating film. (12) In the second step, a silicon nitride film is formed on the first wiring, a resist is applied on the silicon nitride film, the surface is flattened, and dry etching is performed. 12. The method for manufacturing a multilayer wiring device according to claim 11, further comprising the step of flattening the surface of said silicon nitride film and forming a silicon oxide film on said silicon nitride film. (13) The second step according to claim 11, wherein the second step is a step of applying and curing a spin-on glass on a concave portion existing after the first step, and forming a silicon oxide film on the spin-on glass. A manufacturing method of the multilayer wiring device according to the above. (14) In the third step, assuming that the particle size of the second wiring is L and the wiring width is W, the particle size of the crystal grains is set so as to satisfy (W / 14 <L <W). Claims 10 to 13 which are a step of forming so as to be adjusted.
13. The method for manufacturing a multilayer wiring device according to any one of the above items. (15) The method according to any one of claims 10 to 14, wherein the fourth step is a step of forming the silicon nitride film as the protection by plasma CVD. (16) The third step is a step of forming the second wiring by sputtering.
Item 16. The method for manufacturing a multilayer wiring device according to any one of Items 15 to 15.