JPH08212715A - Modulating method for digital data - Google Patents

Abstract

PURPOSE: To decrease the probability of the occurrences of synchronization errors and to prevent the reduction in error correcting capability by providing the synchronization patterns continuously. CONSTITUTION: As shown in Ca, the sector from the starting edge to 2 deg. in a sector SECT is made to be a gap sector CAP1, and the remaining part is equally divided into 131 parts. The first one is made to be a preamble sector PRAM. Furthermore, a sector synchronization sector S-SYNC is equally divided into 11 parts as shown in Cb. Four-channel bytes are recorded and reproduced, respectively. Synchronization signals SYNC are repeatedly provided in the first two channel bytes. The data signal, which undergoes increment one by one from source data F5H, is provided in the next one-channel byte. A parity signal PRTY is provided in the last one-channel byte. Frames FRAM of 128 are provided in a sector, which is continued to the sector synchronizing sector S-SYNC. In the last one sector, a post-amble sector PSAM is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of modulating digital data with a limited running length, which is suitable for recording data on, for example, a small floppy disk.

[0002]

2. Description of the Related Art As a small floppy disk, a video floppy for an electronic still camera has been considered (see: Nihon Keizai Shimbun, June 1, 1984, morning edition, etc.).

That is, in FIG. 3, 1 indicates the video floppy as a whole and 2 indicates the rotating magnetic disk. This disk 2 has a diameter of 47 mm and a thickness of 40 μm.
The center of the disk is provided with a center core 3 to which a spindle of a drive mechanism (not shown) is fitted, and the core 3 is provided with a reference angular position when the disk 2 rotates. Are provided.

A storage jacket 5 has a size of 60 × 54 × 3.6 mm, in which a disk 2 is rotatably stored, and a core 3 and a magnetic piece 4 are formed by a jacket. 5 from the central opening 5A. Further, the jacket 5 has an opening 5B when the magnetic head comes into contact with the disk 2, and when the disk 1 is not used, the opening 5B is covered with a sliding dustproof shutter 6. Reference numeral 7 denotes a counter dial for displaying the number of images that have been captured, 8 denotes a nail for preventing erroneous recording, and when the recording is prohibited, the nail 8 is removed.

Further, on the disk 2, 50 magnetic tracks can be formed concentrically on one surface, the outermost track being the first track, and the innermost track being the 50th track. The track width is 60
μm and the guard band width is 40 μm. At the time of imaging, the disk 2 is rotated at 3600 rpm (field frequency), and a video signal of one field is still-recorded as one magnetic track.

In this case, the signal to be recorded is as shown in FIG. 4, that is, the luminance signal Sy has a sync tip of 6 MHz and a white peak of 7.5 MHz.
An FM signal Sr (center frequency 1.2 MHz), which is converted into an FM signal Sf and is FM-modulated by a red color difference signal,
A line-sequential signal Sc with an FM signal Sb (center frequency 1.3 MHz) FM-modulated by the blue color difference signal is formed,
An addition signal Sa of the FM color signal Sc and the FM luminance signal Sf is recorded.

Thus, the video floppy 1 has an appropriate size, function or characteristics as a recording medium for video signals.

Furthermore, it is considered that the video floppy 1 is used as a recording medium for digital data.

FIG. 5 shows a physical format for recording and reproducing digital data on the video floppy 1. In FIGS. 7A and 7B, TRCK indicates an arbitrary track on the magnetic disk 2, and this track TRCK is a gap section GAP2 of 2 ° and an index section INDX of 2 ° in the longitudinal direction with respect to the magnetic piece 4. Is provided, and the remainder is divided into four equal portions at 89 ° intervals, and each of the divided intervals is called a sector SECT.

The sector SE in the section immediately after the magnetic piece 4
CT is the 0th sector, and the first, second, and third sectors are in order. When accessing data from the host device to the floppy 1, access is performed in units of one sector SECT. The index section INDX is composed of about three frame sections FRA of data described later.
Equivalent to M, T _max signal of digital signal "1000"
Is provided over the entire section.

Then, as shown in FIG.
In CT, a section of 2 ° from the start end is a gap section GAP1 for obtaining a read / write margin,
The remainder is divided into 131 equal parts. In each of these equally divided sections,
44 channel bytes (a channel byte is a unit of a signal formed by a predetermined conversion described later and corresponds to a byte of source data, which corresponds to 10 bits in so-called 8-10 conversion) are recorded and reproduced.

The first two equally divided sections are used as a preamble section PRAM. In this preamble section, for example, a signal of "0101010101" corresponding to 00H (H indicates a hexadecimal value) in source data is repeatedly provided. , Are used for pulling in the PLL at the time of reproduction. further,
The 128 section following this section PRAM is the frame FRA
A section called a signal M is recorded and reproduced.
The last one section is a postamble section PSAM equivalent to the preamble section PRAM.

As shown in FIG. 1D, the one-frame FRAM includes, in order from the top, a one-channel byte synchronization pattern signal SYNC (“0100010001” or “1100010001”), a frame address signal FADR, and an undefined signal. FRSV and check signal F
It has a PTY, data DATA of 32 symbols (1 symbol = 1 channel byte), and first and second redundant data PRT1 and PRT2 of 4 symbols each. In this case, the check signal FPTY is a parity for the frame address signal FADR and the signal FRSV.

Further, the data DATA is the original digital data accessed by the host device, but the data DATA is the interleaved data which is completed within the digital data of one sector SECT, and is redundant data. PRT1 and PRT2 have one sector (32
This is parity data generated by the Reed-Solomon encoding method with a minimum distance of 5 for digital data of (symbol x 128 frames).

Therefore, the capacity of digital data in one sector SECT, track TRCK and floppy 1 is: 1 sector: 4096 bytes (= 16 symbols × 2 × 12)
1 track: 16 Kbytes (= 4096 bytes x 4 blocks) 1 floppy: 800 Kbytes (for one side) (= 16
(K bytes x 50 tracks).

When the digital data is accessed to the floppy 1, the access is made in units of one sector SECT, so the access to the digital data to the floppy 1 is in units of 4 Kbytes.

The number of bits in one frame FRAM and one sector SECT is as follows: one frame: 352 source bits (= (4 + 32 + 4 +
4) × 8 source bits) 1 sector (excluding gap section GAP1): 46464
Source bits (= 352 bits × (128 + 4 frames)) However, in actuality, when a digital signal is recorded / reproduced on the floppy 1, a small DSV is required, and T _min / T _max is small. _{Since W} needs to be large, all the above digital signals have T _max = 4
After the 8-10 conversion of T is performed, it is recorded on the floppy disk 1. At the time of reproduction, the inverse conversion is performed and then the original signal processing is performed.

Therefore, in the case of the above data density, the actual number of bits in the floppy 1 is multiplied by 10/8, and 1 frame: 440 channel bits 1 sector (excluding the gap section GAP1): 58080
Channel bits.

Thus, the entire section of one sector is equivalent to 59415 channel bits (≒ 58080 channel bits × 89 ° / 87 °) (actually, the length of each section is determined from the number of channel bits as described above). , The total length of the frame section is slightly shorter than 87 °).

Therefore, the bit rate when accessing the digital signal (the signal after the 8-10 conversion) to the floppy 1 is 14.32 Mbit / sec (≈59415 bits × 4 blocks × field frequency × 360 ° / 356 °). ), And 1 bit corresponds to 69.8 ns (≈ 1 / 14.32 Mbits).

It is recognized that video signals and digital data can be mixed on a floppy disk 1 in track units.

Thus, according to this format, 2
800 inches per side with inch size video floppy 1
K-byte digital data can be read and written, which is more than twice the general capacity (320 Kbytes) of a conventional 5-inch floppy disk, and is large in spite of its small size.

Since the rotation speed of the disk 2 is the same as that of the video signal, the video signal and the digital data can be mixedly recorded and reproduced. In this case, both signals recorded and reproduced on the disk 2 can be reproduced. The frequency spectrum and the like become similar, and recording and reproduction can be performed under conditions suitable for electromagnetic conversion characteristics, head contact, and the like.

Further, even when recording / reproducing two signals mixedly, it is not necessary to switch the rotation speed of the disk 2, so that it is not necessary to consider the time required for switching the servo circuit, and the two signals are immediately converted. You can use them properly. Further, since the number of rotations is single and the mechanism such as the electromagnetic conversion system may have a single characteristic or function, it is advantageous in terms of cost.

As described above, the video floppy 1 has a new effect as a medium for recording and reproducing video signals or for storing digital data, and as a medium capable of recording and reproducing mixed video signals and digital data. Have.

[0026]

The above-mentioned 8-1
In the 0 conversion, for example, 84H is “10” in the source data.
10001001 ", 80H is" 101001010 "
Considering the case where these are consecutive as "1", when "1" at the end of 84H is wrongly changed to "0", "X100010"
A bit stream of "001" is generated, which coincides with the synchronization pattern, so that a synchronization error occurs.

Here, the probability Pse of this synchronization error is a naked bit error rate: Pbe Probability of occurrence in 8-10 conversion with 4-bit running length: Prl4 Probability of occurrence in 8-10 conversion of 3-bit running length: Prl3 Then, Pse≈Pbe * Prl4 * Prl3, and in one example, Pbe = 10 ⁻⁴ and Prl4 = 0.06.
2. Assuming that Prl3 = 0.213, Pse ≒ 1.3 × 10 ⁻⁶ .

This is inconvenient because Pse greatly falls below this if the error correction capability of each redundant bit is 10 ^-12 at Pbe = 10 ^-4. .

That is, if the probability of occurrence of a synchronization error is significantly higher than the error correction capability of data, the capability of the system is constrained by the higher probability, so that the above error correction capability is completely wasted. Had become. The present invention has been made in view of such a point.

[0030]

Therefore, according to the present invention, a predetermined number of synchronization patterns are continuously provided. According to this, the probability of occurrence of a synchronization error is reduced and the error correction capability is improved. It can be an approximate value.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION That is, according to the present invention, in a modulation method for converting digital data from m bits to n bits based on a synchronization pattern repeatedly inserted in digital data, the synchronization pattern is a digital signal having a finite running length. A pattern that represents a bit synchronization signal and an n-bit synchronization signal that has a running length equal to that of the data and that has a pattern different from that of the digital data. Are formed respectively, the patterns representing the bit synchronization signal are detected, the bit synchronization signal is output only when all the synchronization patterns included in the bit synchronization signal are correct, and the n-bit synchronization signal is represented based on the bit synchronization signal. The pattern is detected and all the sync patterns included in the n-hit sync signal are correct. Outputs n bit synchronization signal for each Itokinomi n bits, on the basis of the n-bit synchronization signals, in which the digital data obtained by modulating the m bits to n bits.

An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a physical format of recording and reproduction on a small floppy disk applied to the digital data modulation method of the present invention. In this format, the format of the track TRCK is the same as the conventional one as shown in FIGS.

Then, as shown in FIG.
In CT, the interval of 2 ° from the start end is the gap interval CAP.
1 and the remainder is divided into 131 equal parts, and the first one is a preamble section PRAM. In this preamble section, for example, a signal of “1111111111” corresponding to EBH in source data is repeatedly provided,
It is used for pulling in the PLL at the time of reproduction. Further, a section following the preamble section PRAM is defined as a sector synchronization section S-SYNC.

Then, as shown in FIG. 3C, the sector synchronization section S-SYNC is divided into 11 equal parts, 4 channel bytes are recorded and reproduced, and a synchronization pattern signal SYNC is repeatedly provided in the first 2 channel bytes. Can be Further, a data signal which is incremented by one from F5H of the source data is provided in the next one channel byte, and the parity signal PRTY is provided in the last one channel byte.

Further, the sector synchronization section S-SYNC
Are provided in the section following the, and the last section is a postamble section PSAM, which is “111” corresponding to the EBH similarly to the preamble section PRAM.
The signal of 1111111 ″ is repeatedly provided.

Then, as shown in FIG. 3D, the 1-frame FRAM has a 2-channel byte sync pattern signal SYNC repeated, a 1-channel byte frame address signal FADR, and a 1-channel byte check signal in order from the beginning. FPTY, data DATA of 32 symbols, and first and second symbols of 4 symbols each.
Of redundant data PRT1 and PRT2.

In this case, the frame address signal FADR
Is 1 channel byte and source data is 1 byte = 8 bits. Since the number of frame FRAMs in one sector SECT is 128 as described above, the frame address is determined by 7 bits, and the remaining MSB, for example, is It can be used to record information. The check signal FPTY is a parity for the frame address signal FADR. Further, the data DATA and the redundant data PRT1, PRT2
Is the same as in the prior art.

Therefore, in this format,
It is possible to perform recording / reproducing with exactly the same storage capacity as the above-mentioned conventional format.

In this case, the probability of the synchronization error is: Pse = (10 ⁻⁴ × 0.062 × 0.213) ² 21.
It becomes 7 × 10 ⁻¹² , which is equivalent to the error correction capability, and the error correction capability of the entire system by this method can be greatly increased.

FIG. 2 shows a circuit for detecting the synchronization recorded in the above-mentioned manner. In the figure, the disk 2 of the floppy 1 is rotated at a rate of 60 times per second by a motor (not shown), and the target track TRCK of the disk 2 is contacted with the magnetic head 11 so that the channel of the track TRCK is The data CHND is reproduced,
The data CHND is supplied to the first synchronization pattern detection circuit 13 through the reproduction amplifier 12.

The detection circuit 13 compares a 10-bit serial input and a parallel output shift register supplied with the data CHND with a parallel output of this register and a pattern of a normal synchronization signal SYNC. The output of the detection circuit 13 becomes "1" when the synchronizing signal SYNC is correctly reproduced when the coincidence signal is output.

The detection output is supplied to the AND circuit 15 and the serial output of the shift register of the detection circuit 13 is supplied to the detection circuit 14 having the same second synchronization pattern. Supplied to Therefore, when the synchronization signal SYNC that is correctly reproduced two consecutive output P ₁₅ of the AND circuit 15 becomes "1".

Further, the data CHND from the amplifier 12
Is supplied to the PLL 16 to form a channel clock φ bit-synchronized with the data CHND.
There is supplied as a count input to the 10-bit counter 17, and the output P ₁₅ is supplied as a reset input to the counter 17. Then, the carry output of the counter 17 and the AND output P ₁₅ are taken out through the OR circuit 18.

Therefore, carry output is obtained from counter 17 every 10 bits of channel clock φ. At this time, the counter 17 outputs the sync signal SYNC of 2
One is reset by the AND output P ₁₅ each followed, since the counter starts counting from that reset time,
OR output P ₁₈ of the OR circuit 18 will from the synchronizing signal SYNC is obtained every 10 bits counted at the channel clock phi.

That is, the OR output P ₁₈ is a synchronization signal indicating a 10-bit segment of the channel data CHND. Note that 10-bit channel data CHND corresponds to 8 bits of the source data, therefore, the OR output P ₁₈ is also a signal indicating a break in the source data, hereinafter referred to as the OR output P ₁₈ and byte synchronous signals .

Further, channel data CHND is serially extracted from a predetermined stage of the shift register of the detection circuit 14, and the data CHND is serially extracted. The data CHND is supplied to a 10-bit serial input / parallel output shift register 21, and a clock φ is supplied to the register 21 to output the data CH.
NDs are fetched in 10-bit units in parallel.

[0047] together with the data CHND is supplied to the latch 22, the byte synchronization signal P ₁₈ is supplied with data CHND is latched by the latch 22 when separated correctly 10 bits as a latch enable input to the latch 22. The latched data CHND is the decoder 23.
And is decoded (10-8 conversion) into 8-bit source data SRCD. And this data SRC
D is taken as a read output after being once latched in the latch 24 by the synchronizing signal P _18.

That is, according to this circuit, the reproduction probability of a synchronization error can be greatly reduced by reproducing the format in which the above-mentioned two synchronization patterns are provided in succession, and the synchronization detection signal corresponds to the running length. Counter 17
Is reset, and synchronization is achieved with the output of the counter 17, so that stable synchronization can always be achieved.

In the above description, the source data SR
In the case where the CD is converted to 8-10 and recorded on the floppy disk 1, the run length is limited and the mn conversion (m
The present invention can be applied to the case where the data is <n) data and a bit synchronization signal and an n-bit synchronization signal are sequentially included in the preamble portion at the head of the packet of the data.

[0050]

According to the present invention, by providing a plurality of synchronization patterns in succession, the probability of occurrence of a synchronization error can be reduced and the value can be approximated to the error correction capability.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a format of a small floppy disk to which the present invention is applied.

FIG. 2 is a circuit diagram of the detection circuit.

FIG. 3 is a diagram for explaining a conventional technique.

FIG. 4 is a diagram for explaining a conventional technique.

FIG. 5 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 1 Video Floppy 13, 14 Detection Circuit 17 Counter 21 Shift Register 23 Decoder

Claims (1)

[Claims] 1. A method of modulating digital data in which the digital data is modulated from m bits to n bits based on a synchronization pattern repeatedly inserted in the digital data, wherein the synchronization pattern is equal to digital data having a finite running length. A pattern that represents a bit synchronization signal and an n-bit synchronization signal that has a running length and is composed of a pattern different from that of the digital data, and the synchronization pattern is continuously arranged at a predetermined number at the beginning of the packet of the digital data. Respectively, the patterns representing the bit synchronization signals are detected, and the bit synchronization signals are output only when all the synchronization patterns included in the bit synchronization signals are correct. The pattern representing the bit synchronization signal is detected, and the n-bit synchronization signal is detected. Only when all the included synchronization patterns are correct, an n-bit synchronization signal is output every n hits, and the digital data is modulated from m bits to n bits based on the n-bit synchronization signal. Modulation method.