JPH0820952B2 - Data processing device with pipeline processing mechanism - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device that realizes a high processing capacity by an advanced pipeline processing mechanism, and particularly in a pipeline processing even for a subroutine return instruction. The present invention relates to a data processing device capable of performing preceding branch processing to a return address at an initial stage.

[Conventional technology]

FIG. 7 is a diagram showing a typical pipeline stage of a conventional data processing apparatus. In the figure, (1) is an instruction fetch stage, (2) is an instruction decode stage,
(3) is an address calculation stage, (4) is an operand fetch stage, (5) is an execution stage, and (8) is an operand write stage.

Next, the operation will be described. The data processing device shown in FIG. 7 uses an idle time of the bus to fetch the instruction data (1), an instruction decoding stage (2) for analyzing the instruction data, an operand, etc. Six stages: an address calculation stage (3) for address calculation, an operand fetch stage (4) for fetching operand data, an execution stage (5) for processing data, and an operand write stage (8) for writing operand data. Of pipeline stages, each stage can process different instructions simultaneously. However, in the case where a conflict has occurred with respect to operands or memory access, the process with a low priority is suspended until the conflict is resolved.

As described above, in the pipelined data processing device, the processing is divided into a plurality of stages according to the flow of data processing, and each stage is operated at the same time to reduce the average processing time required for one instruction. To improve the overall performance.

However, in such a pipelined data processing device, when an instruction that disturbs the flow of instructions such as a branch instruction is executed in the execution stage (5), the processing performed in the previous stage is executed. Are all canceled and the next instruction to be executed must be from the instruction fetch. In this way, when an instruction that disturbs the processing flow is executed, the overhead of pipeline processing becomes large, and the execution speed of the data processing device cannot be increased. In order to improve the performance of the data processing device, various measures have been made to reduce the overhead related to instruction execution such as unconditional branch instructions and conditional branch instructions. For example, a branch target buffer that stores the address of a branch instruction and the address of a branch destination as a pair is used to predict the flow of instructions at the instruction fetch stage and perform processing. (JK
F. Lee and AJ Smith, “Branch Prediction Strategies
and Branch Target Buffer Design, “IEEE COMPUTER V
ol.17, No.1, January 1984, pp.6-22.) As described above, the flow of processing is predicted at the initial stage of pipeline processing, and the instruction predicted to be executed next is calculated. The overhead at the time of executing a branch instruction is reduced by flowing it to the pipeline (hereinafter referred to as the preceding branch processing). However,
With respect to the return instruction from the subroutine, it is difficult to predict the flow of processing because the return address from the subroutine depends on the address of the corresponding subroutine call instruction.

[Problems to be Solved by the Invention]

As described above, in the conventional data processing device, since the return address from the subroutine depends on the address of the corresponding subroutine call instruction with respect to the return instruction from the subroutine, an effective means for predicting the processing flow is provided. There wasn't.

The present invention has been made in order to solve the above problems, and it is possible to obtain a data processing device capable of performing a pre-branch processing to a return destination address even in the case of a subroutine return instruction at an early stage of pipeline processing. With the goal.

[Means for solving the problem]

The data processing device according to the present invention includes a stack memory (hereinafter referred to as a PC stack) dedicated to a program counter (PC) that stores only the return address of a subroutine call instruction.

[Operation] In the data processing device according to the present invention, the return address from the subroutine is pushed onto the PC stack when the subroutine call instruction is executed in the execution stage, and the subroutine return instruction is decoded in the instruction decode stage.
Performs pre-branch processing to the address popped from the PC stack.

Example of Invention

(1) Pipeline Mechanism The pipeline processing of the data processing apparatus of the present invention has the configuration shown in FIG. Instruction fetch stage for prefetching instructions (IF stage (1), decode stage for decoding first instruction (D stage (2), operand address calculation for second instruction decoding and operand address calculation) A stage (A stage (3)), a micro-ROM access (especially called R stage (6)) and an operand fetch stage (especially called OF stage (7)) for performing an operand prefetch (F stage (4)), The pipeline processing is based on a five-stage configuration of an execution stage (E stage (5)) for executing instructions.In the E stage (5), there is a one-stage store buffer, and some high-performance instructions include instructions. Since the execution itself is pipelined, there are actually five or more pipeline processing effects.

Each stage operates independently of the other stages, and theoretically five stages operate completely independently. Each stage can perform one processing in a minimum of 2 clocks. Therefore, ideally, pipeline processing proceeds every two clocks.

Although the data processing device of the present invention has instructions that cannot be processed by only one basic pipeline process such as memory-memory operation and memory indirect addressing, the data processing device of the present invention also handles these processes. It is designed so that balanced pipeline processing is possible.
For an instruction having a plurality of memory operands, the pipeline processing is performed by decomposing into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands. The method of disassembling the pipeline processing unit is described in detail in Japanese Patent Application No. 61-236456.

The information passed from the IF stage (1) to the D stage (2) is the instruction code (11) itself. The information passed from the D stage (2) to the A stage (3) relates to the operation specified by the instruction (called the D code (12)).
And those related to operand address calculation (called A code (13)). The information passed from the A stage (3) to the F stage (4) is an R code (14) including an entry address of a microprogram routine and a parameter to the microprogram, and an F code including an operand address and access method instruction information. Code (15)
And two. Information passed from the F stage (4) to the E stage (5) is an E code (16) including operation control information and a literal and an S code (17) including operands and operand addresses.

(1.1) Processing of each pipeline stage (1.1.1) Instruction fetch stage The instruction fetch stage (IF stage (1)) fetches an instruction from external memory, inputs it to the instruction queue, and
The instruction code (11) is output to the stage (2).

Input to the instruction queue is performed in aligned 4-byte units.
Fetching instructions from memory requires a minimum of 2 clocks for every 4 bytes aligned. When the branch buffer is hit, it is possible to fetch the aligned 4 bytes in 1 clock.

The output unit of the instruction queue is variable every 2 bytes,
Up to 6 bytes can be output in 2 clocks. Immediately after branching, it is possible to bypass the instruction queue and directly transfer the two bytes of the basic instruction portion to the instruction decoder.

The management of the prefetch destination instruction address is also performed in the IF stage (1). The address of the instruction to be fetched next is calculated by a dedicated counter as the address of the instruction to be input to the instruction queue. When a branch or jump occurs,
The address of the new instruction is transferred from the PC operation unit or data operation unit.

(1.1.2) Instruction Decode Stage The instruction decode stage (D stage (2)) decodes the instruction code (11) input from the IF stage (1). The instruction code is in units of 16 bits (halfword). Decode once every two clocks
The instruction code of 0 to 3 halfwords is consumed in the decoding process of one time. At the D stage (2), the instruction code is decomposed into a step code which is a pipeline processing unit. That is, one instruction is decomposed into one or a plurality of step codes and processed in the subsequent pipeline stage. In the D stage (2), as the step code, A is the address calculation information for the A stage (3).
The code (13) and the D code (12) which is the intermediate decoding result of the operation code are output.

In the D stage (2), control of the PC arithmetic unit, branch prediction processing, preceding branch processing for pre-branch instructions (pre-branch), instruction code output control from the instruction queue, etc. are also performed. Pre-branch processing is, prior to the branch processing at E stage (5), predicts branches such as unconditional branch instructions and conditional branch instructions, calculates the address of the jump destination in the PC arithmetic unit, and This is to cause (1) to fetch the jump destination instruction and to flow the jump destination instruction to the pipeline. The pre-branch instruction is an instruction for performing pre-branch processing.

(1.1.3) Operand address calculation stage The operand address calculation stage (A stage (3)) is roughly divided into two processes. One is a process for performing the subsequent decoding of the operand, and the other is a process for calculating the address of the operand.

The subsequent decoding process of the operation code receives the D code (12) as input, and outputs the R code (14) including the write reservation of the register and the memory and the entry address of the microprogram and parameters for the microprogram.
Note that the register or memory write reservation is for preventing the contents of the register or memory referred to in the address calculation from being rewritten by the preceding instruction on the pipeline and causing incorrect address calculation. In order to avoid deadlock, write reservation of registers and memory is performed not for each step code but for each instruction. The write reservation of registers and memories is described in detail in Japanese Patent Application No. 62-144394.

In the operand address calculation process, the A code (13) is input, the address calculation is performed by the operand address calculation unit according to the A code (13) by combining addition and memory indirect reference, and the calculation result is output as the F code (15). .
At this time, a conflict check is performed at the time of reading the register or memory associated with the address calculation, and if the conflict is instructed because the preceding instruction has not completed the writing process to the register or memory, the preceding instruction is written at the E stage (15). Wait until the process is completed.

In order to prevent a stack pointer (SP) conflict due to a pop operation from the stack, a push operation to the stack, etc. at the A stage (3), the A stage stack pointer (AS
P) is provided, and ASP update associated with pop and push operations is performed at this stage. Therefore, normal pop.
By referring to the ASP even immediately after the push operation, it is possible to proceed without delaying the processing of the step code due to the conflict of the SP. The method of managing the SP is described in detail in Japanese Patent Application No. 62-145852.

(1.1.4) Micro ROM access stage The operand fetch stage (F stage (4)) is also roughly divided into two processes. One is a micro ROM access process, which is particularly called an R stage (6). The other is an operand prefetch process, which is particularly called an OF stage (7). The R stage (6) and the OF stage (7) do not always operate at the same time, but operate independently depending on whether or not a memory access right can be acquired.

In the R stage (6), micro ROM access and micro instruction decoding processing for producing an E code (16) which is an execution control code used for execution in the next E stage (5) for the R code (14) Is done. 1 R
If the processing on the code is decomposed into two or more microprogram steps, the micro ROM is used in the E stage (5) and the next R code (14) is the micro ROM.
Waiting for access. Micro for R code (14)
ROM access is performed before the E stage (5)
It is the time of the last microinstruction execution in. In the data processor of the present invention, most basic instructions are executed in one microprogram step, so in practice, micro ROM access to the R code (14) is often performed one after another.

(1.1.5) Operand fetch stage The operand fetch stage (OF stage (7)) performs the operand prefetch process of the above two processes performed in the F stage (4).

In the operand prefetch, the F code (15) is input, and the fetched operand and its address are output as the S code (17). One F code (15) may cross word boundaries, but specifies an operand fetch of 4 bytes or less. The F code (15) also includes the designation of whether or not to access the operand, and the operand address itself or the immediate value calculated in the A stage (3) is E
When transferring to stage (5), operand prefetch is not performed and the contents of F code (15) are converted to S code (17)
To transfer as. When the operand to be prefetched and the operand to be written by the E stage (5) satisfy the inclusive relation, memory access is not performed for the operand prefetch and the value to be written by the E stage (5) is bypassed. To do.

(1.1.6) Execution stage The execution stage (E stage (5)) is the E code (1
6), using the S code (17) as an input, the data processing, the data reading, the data writing, and the like using various arithmetic units are performed. ALU, barrel shutter, priority encoder, counter, shift register, etc.
The E stage (5) is controlled by the microprogram and executes an instruction by executing a series of microprograms from the entry address of the microprogram indicated by the R code (16). 3 between the register and the main arithmetic unit
They are connected by a bus and process one microinstruction for instructing one inter-register operation in two clock cycles.

The E stage (5) is a stage for executing an instruction, and all the processes performed in the stages before the F stage (4) are preprocessing for the E stage (5). Occurs, all the processing from the IF stage (1) to the F stage (4) is invalidated, and the jump destination address is output to the instruction fetch unit and the PC calculation unit.

In the E stage (5), the store buffer in the data operation unit (56) can be used to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage (5), the write reservation for the register and the memory made in the A stage (3) is canceled after writing the operand.

When the conditional branch instruction causes a branch at the E stage (5), it indicates that the branch prediction for the conditional branch instruction is incorrect, and the branch history is rewritten.

(1.2) Management of Program Counter All step codes existing on the pipeline of the data processing device of the present invention may be for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that caused the step code. The program counter value attached to the step code and flowing through each stage of the pipeline is called a step program counter (SPC). SPCs are handed over to the pipeline stages one after another.

(2) Preceding Branch Processing of Subroutine Return Instruction In order to suppress the disturbance of the pipeline due to the execution of the subroutine return instruction in the execution stage, the data processing device of the present invention has an instruction decode stage (D stage (D stage ( The preceding branch processing is performed in 2)). The detailed operation will be described below.

FIG. 2 is a block diagram of the data processing apparatus of the present invention, in which only the portions necessary for explaining the processing of the subroutine call instruction and the subroutine return instruction are extracted and described. In the figure, (21) is the instruction queue,
(22) is an instruction decoding unit, (23) is a data input / output circuit for exchanging data with the outside, (24) is an address output circuit for outputting an external address, and (25) is an address for fetching an instruction. Counter for (QINPC), (2
6) is an instruction decoding unit (22) for each step code generation
Latch (IL) for storing the instruction length processed by, (27) is a latch (PD) for storing displacement for PC for pre-branch, (30) is addition in PC operation unit (54) PC adder to do, (28), (29), (31) are respectively PC
Input / output latches (PA, PB, P0) of the adder (30), (32) are registers (TPC) for storing the temporary PC for each step code processing, and (33) is the PC of the instruction currently being decoded.
D-stage PC (DPC) for storing the address, (34) A-stage PC (APC) for storing the PC corresponding to the step code code in the address calculation, (38) is a three-value for address calculation Address adder that performs addition, (35),
(36), (37), (39) are address adders (3
Input / output latches (AI, AD, AB, A0) and (40) of 8) are A stage stack pointers (ASP) and (41) that manage SP by incrementing or decrementing at A stage (3).
Is an F code for storing an address as an F code (15)
Code address registers (FA), (42) are S code (1
7) S code address register for storing address, (43) CA address register (CAA) for temporarily storing instruction fetch address, (4
4) is the address register (AA) managed by the E stage (5), (45) is the E stage branch address register (EB) for storing the branch destination address in the E stage (5), (46) Is a PC stack that stores only the return address at the time of subroutine call, (47) is a register file containing stack pointer, frame pointer, working register, etc. (56) is a value input from S2 bus (102) DM latch, which outputs the value to the D0 bus (103), (5
0) is ALU for data operation, (48), (49), (51)
Is an ALU (50) input / output latch, (DA, DB, D0), (52) is an S code data register (SD) for storing data as an S code (17), and (53) is an E stage (5 ) Is a data register (DD) for storing data related to memory access, and (101) to (110) are internal buses (S1 bus, S2 bus, D0 bus, etc.) for internally transferring data and addresses. A bus, A0 bus, DISP bus, P0 bus, CA bus, AA bus, D0 bus). Reference numeral (54) is a PC calculation unit, and (55) is an address calculation unit.

FIG. 3 is a block diagram of a portion particularly related to the preceding branch processing of the subroutine return instruction in the data processing device of the present invention. In the figure, (61) is a D stage control unit, (62) is an IF stage control unit, (63) is an E stage control unit, and (65) is 3 for counting the number of subroutine call instructions during pipeline processing. BSR counter, which is a bit counter, (66) is a 3-bit PC stack pointer (DP) managed by the D stage (2), (67)
Is a 3-bit PC stack pointer (EP) managed by the E stage (5), (68) and (69) are DP (6
6), a decoder that decodes EP (67), (201)
˜ (212) are control signals for each unit. In this figure, the clock signal for controlling the timing is omitted for simplicity.

In this embodiment, the PC stack (46) is composed of 8 entries. Although DP (66) and EP (67) are 3 bits, carry from the most significant bit at increment and borrow to the most significant bit at decrement are ignored. That is, the PC stack (46) is handled as a ring-shaped stack memory in which the entry pointed by the pointer '000' is adjacent.

(2.1) Outline of the operation of the PC stack An outline of how the subroutine call instruction and the subroutine return instruction are executed in the data processing device of the present invention will be described.

In the data processor of the present invention, there are a branch subroutine (BSR) instruction and a jump subroutine (JSR) instruction as the subroutine call instruction. Also, as a subroutine return instruction, a return subroutine (RTS)
As an instruction and a high-function instruction, there is a high-level language subroutine return and an EXITD instruction that releases parameters at once.

When the subroutine call instruction is executed, the return address from the subroutine is pushed onto the PC stack (46) at the E stage (5). When the subroutine return instruction is decoded, the preceding branch processing (pre-return) is performed at the address on the stack top of the PC stack (46) in the D stage (2). Since the branch process is performed in the decode stage (2) which is the initial stage of the pipeline, the disturbance of the pipeline due to the execution of the subroutine return instruction can be significantly reduced. In the execution stage (5), the pre-returned address and the true return address read from the memory are compared, and if they do not match, branch processing to the true return address is performed. Pointer PD (66), EP
(66) etc. will be explained in a little more detail, including updates.

In the reset state, the RESET signal (208)
The BSR counter (65) and EP (67) are cleared to zero and DP (6
The value of EP (67) which is zero is copied to 6).

First, the instruction code fetched from the instruction queue (21) is decoded by the instruction decoding unit (22). As a result of decoding, when the fetched instruction is a subroutine call instruction, the DPDEC signal (202) is used to decrement the DP and the BSR counter (65) is incremented. In the address calculation stage (3), the return address is calculated by the address adder (38) and the A0 bus (10
5) is transferred to the FA register (41). In the F stage (4), the value of the FA register (41) is changed to the SA register (4
2) transferred to. When the subroutine call instruction is executed at the E stage (5), EP (6
The value of 7) is pre-decremented. The PC stack (4) pointed to by the EP (67) updated by the PCWRITE signal (210)
The value of the return address stored in the SA register (42) is written in 6) via the SI bus (101). Also, BSRCDE
The B signal (205) decrements the BSR counter (65). In the BSR instruction, branch processing to the start address of the subroutine is performed in the D stage (2). The BSR instruction does not need to perform branch processing at the E stage (5).

Next, the processing of the subroutine return instruction will be described. If the instruction fetched from the instruction queue (21) is a subroutine return instruction, the BSR counter (6
BSRCZ signal (201) indicating whether the value of 5) is zero
Check. If the BSR counter (65) is not zero or the value of the BSR counter (65) becomes zero, the D stage (2) suspends the processing. The fact that the BSR counter (65) is not zero indicates that the corresponding subroutine call instruction has not been executed in the E stage (5) and is in pipeline, and the PC stack (46)
It indicates that the return address corresponding to is not registered. When the BSRCZ signal (201) indicates that the value of the BSR counter (65) is zero or has reached zero, the D stage control unit (61) sends a PRERET signal (209) to the IF stage control unit. Notify (62) and PC stack (46) that pre-return processing will be performed. PC stack (4
6) outputs the content of the entry pointed to by DP (66) to the CA bus (108). The IF stage control unit (62) invalidates all the instruction data fetched in the instruction queue (21), fetches the instruction at the return address with the value output to the CA bus, and fetches the fetched instruction data. It is sent to the instruction decoding unit (22). After the contents of the PC stack (46) are output to the CA bus (108), the D signal is output by the DPINC signal (203).
P (66) is post-incremented. In the RTS instruction,
At the F stage (4), the correct return address is fetched from the memory and taken into the SD register (52). In the EXITD instruction, the correct return address is fetched from the memory into the DD register (53) during the execution of the instruction at the E stage (5). EP (6 by the PCREAD signal (211)
The contents of the PC stack (46) pointed to by 7) are output to the S1 bus and taken into the DA latch (48) which is the input latch of the ALU (50). The value fetched in the DA latch (48) is the return address when the subroutine return instruction currently being processed in the E stage (5) has made a pre-return.
Further, the true return address stored in the SD register (52) or the DD register (53) is stored in the DB latch (49) via the S2 bus (102). The ALU (50) compares the contents of the DA latch (48) with the contents of the DB latch (49), and the zero flag (ZFLAG signal (21
2)) is sent to the E stage control unit (63). In the E stage control section (63), if the comparison results are in agreement, it indicates that the pre-return was correct, so the execution of the subroutine return instruction is ended. If the comparison results do not match, it indicates that the return address for which pre-return was performed was incorrect. At this time, the value of the true return address is transferred to the EB register (45) via the S1 bus (101), and then the value of the EB register (45) is output to the CA bus (108). The IF stage (1) is a CA bus (10
Instruction fetch is performed according to the value output in 8).

When the subroutine return instruction is executed, in the E stage (5), it is checked whether or not the return destination address which was pre-returned in the D stage (2) was correct. This is because the PC stack (46) consists of 8 entries, so if subroutine calls are nested at 9 levels or higher, the data at the return address for subroutine calls at levels above 8 will be overwritten. It will be destroyed. Further, even when the value of the return address on the external memory is rewritten by the program, the program returns to an address different from the return address registered in the PC stack (46). In preparation for such a case, the E stage (5) checks whether or not the pre-return has been correctly executed. However, it is unlikely that the value of the return address on the external memory will be rewritten by the program, and the correct value will always be stored in the PC stack (46) for the 8th level subroutine call from the point where the subroutine level became the deepest. Therefore, the probability that the pre-return will be correct is very high.

The BSR counter (65) described above is provided for more accurate pre-return and for reliable comparison in the E stage (5). Without this function, the subroutine call instruction is being processed and the processing at the D stage (2) has finished, but at the E stage (5) the value of the return address has not yet been written to the PC stack (46). If the subroutine return instruction is executed in the D stage (2) before that, the return destination address of the corresponding subroutine return instruction is not registered, so pre-return processing is performed at an incorrect return destination address. However,
When the subroutine return instruction is processed in the E stage (5), the preceding subroutine call instruction has already been processed and the correct return address is registered in the PC stack (46). (5)
The comparison result in (1) indicates a match, and the pre-return is processed as if it was correct. That is, in such a case, a malfunction occurs. By providing the function of the BSR counter, after the value of the return address to be referenced is registered by the preceding subroutine call instruction,
A pre-return is done. Also, when executing a subroutine call instruction, PC stack (46) at D stage (2)
Since the PC stack (46) is not rewritten from when is referenced to when the E stage (5) is processed, the value of the return destination address pre-returned in the D stage (2) is the E stage (5). Correctly referenced. However, with the JSR instruction that does not perform pre-branch, the branch processing of the branch destination address is performed in the E stage (5). Therefore, if the RTS instruction refers to the PC stack before being registered with the JSR instruction, it returns pre-return. However, since the pipeline is canceled before the RTS instruction itself is executed,
This will not happen.

As described above, by providing the PC stack (46) that stores only the return destination address at the time of subroutine call, pre-return to the return destination address is performed at the instruction decoding stage for the subroutine return instruction, and the subroutine return Eliminates turbulence in the pipeline when executing return instructions.

When a branch occurs in the E stage (5), the value of the BSR counter (65) is cleared to zero by the EBRA signal (204), and the content of EP (67) is copied to DP (66). When a branch occurs at the E stage (5), all the processing at the IF stage (1) to the F stage is invalidated, so that it was decoded at the D stage (2), but at the E stage (5). The value of the return address of the PC stack (46) up to that level is invalidated by invalidating the update of the BSR counter (65) and DP (66) performed for the unprocessed mid-process subroutine call instruction or subroutine return instruction. Can be correctly referred to on the D stage (2).

(2.2) Detailed Operation of Subroutine Call Instruction and Subroutine Return Instruction Above, the rough operation of the subroutine call instruction and the subroutine return instruction has been described. Here, the detailed operation of each instruction will be described.

In the data processor of the present invention, there are a branch subroutine (BSR) instruction and a jump subroutine (JSR) instruction as the subroutine call instruction. Also, as a subroutine return instruction, a return subroutine (RTS)
As an instruction and a high-function instruction, there is a high-level language subroutine return and an EXITD instruction that releases parameters at once. Hereinafter, each instruction will be described in detail. The bit allocation for each instruction is shown in FIG. "-" Indicates an operation code.

(2.2.1) BSR instruction The BSR instruction is a subroutine call instruction that supports only PC-relative addressing, and the return address is saved in the stack. As shown in FIGS. 4A and 4B, the BSR instruction has two instruction formats, a general type (G format) and a shortened type (D format). In the D stage (2), the same process is performed for both formats. This instruction is processed as one step code.

A flowchart for executing the BSR instruction is shown in FIG. When the BSR instruction is processed by the instruction decoding unit (22), a D code (12) indicating the step code of the BSR instruction and an A code (13) for calculating the return address are generated. In the case of the G format command, the value of the displacement (82D) is also captured at the same time according to the field (82B) indicating the size of the displacement.
Further, the DPDEC signal (202) decrements the DP (66) and increments the BSR counter (65). This instruction is an instruction for pre-branching, the jump address is calculated in the PC operation unit (54), and the operation result is output to the CA bus (108) for pre-branching processing. In the A stage (3), the return address is calculated in the address calculation section (55) according to the instruction of the A code (13) and transferred to the FA register (41) via the A0 bus (105). In the F stage (14), the value of the FA register (41) is transferred to the SA register (42). In the E stage (5), first, the EP (67) is sent by the EPDEC signal (206).
Pre-decrement of. Then the PCWRITE signal (210)
Depending on the value of the SA register (42) that stores the return address, S1 is transferred to the PC stack (4) via the bus (101).
It is written in the entry pointed to by EP (67) in 6). At the same time, the value of S1 bus (101) is ALU (50) and D0 bus (10
The value of the DD register (53), which is written in the DD register (53) via 3) and stores the return address, is pushed onto the stack on the memory managed by software by the stack pointer. When the return address is registered in the PC stack (46), BRS is sent by the BSRCDEC signal (205).
The counter (65) is decremented. In this command,
Since the branch processing has already been performed in the D stage (2), the branch processing is not performed in the E stage.

(2.2.2) JSR instruction The bit allocation of the JSR instruction is shown in Fig. 4 (C). The JSR instruction is a subroutine jump instruction to the effective address of NEWPC (83C), and the return address is saved in the stack. With respect to the jump destination address, it is possible to specify the addressing extension in a plurality of stages, but for simplicity, the case where the extension is not specified will be described. This instruction is decomposed into two step codes and processed in the D stage (2). The first step code performs processing regarding the jump destination address, and the second step code performs processing regarding the return destination address.

First, the process related to the first step code will be described. When the JSR instruction is decoded by the instruction decoding unit (22), the D code (12) indicating the first step code of the JSR instruction and the A for calculating the effective address of the jump destination address
Code (13) is generated. If an expansion unit (83C) such as an absolute address or displacement is required for address calculation of the jump destination address, that data is also fetched from the instruction queue (21) at the same time. In the A stage (3), the address calculation unit (55) calculates the jump destination address according to the instruction of the A code (13), and the FA register (4) is calculated via the A0 bus (105).
Transferred to 1). In the F stage (4), FA register (4
The value of 1) is transferred to the SA register (42). At the E stage (5), the value of the SA register (42) storing the jump destination address is transferred to the EB register (45) via the S1 bus (101).
Transferred to.

Next, the process related to the second step code will be described. In the D stage (2), a D code (12) indicating the second step code of the JSR instruction and an A code (13) for calculating the effective address of the return destination address are generated.
In the processing of this step code, the instruction data is not fetched from the instruction queue (21). Also, the DPDEC signal (202) decrements the DP (66) and the BSR counter (6
Perform the increment process of 5). In the A stage (3), the address calculation unit (5
The return address is calculated in 5) and the A0 bus (10
5) is transferred to the FA register (41). In F stage (4), the value of FA register (41) is SA register (42).
Transferred to. In the E stage (5), first, the EP (67) is pre-decremented by the EPDEC signal (206).
Next, by the PCWRITE signal (210), the value of the SA register (42) storing the return address is changed to the S1 bus (101).
Is written to the entry pointed to by EP (67) in the PC stack (46). At the same time, the value of S1 bus (101) is ALU.
(50), DD register (53) that has been written to the DD register (53) via the D0 bus (103) and stores the return address
Bush the value of 3) to the stack in the memory managed by software by the stack pointer. First
The value of the jump destination address already written in the EB register (45) by the step code is output to the CA bus (108) to perform branch processing. At this time, the BSR counter (65) is cleared by the EBRA signal (204), and the value of EP (67) is copied to DP (66).

As described above, the processing for the PC stack (46) is the same for the JSR instruction as for the BSR instruction.

(2.2.3) RTS instruction The RTS instruction is an instruction that returns from a subroutine and jumps to the return address returned from the stack. This instruction is processed as one step code.

A flow chart for executing the RTS instruction is shown in FIG. When the RTS instruction is processed by the instruction decoding unit (22), a D code (12) indicating the step code of the RTS instruction and an A code (13) for calculating the stack top address are generated. This instruction is a pre-return instruction. BSRCZ
When the signal (201) indicates that the subroutine call instruction exists in the pipeline, the processing is temporarily stopped until the content of the BSR counter (65) becomes zero. If the BSR counter (65) is zero, pre-return processing is performed. The PRERET signal (209) outputs the content of the entry pointed to by the DP (66) in the PC stack (46) to the CA bus (108), and performs the preceding branch processing (pre-return). Also, after referring to the PC stack (46), the DPINC signal (20
The post increment processing of DP (66) is performed by 3). In the A stage (3), the address calculation unit (55) calculates the stack top address according to the instruction of the A code (13) and writes the stack top address in the FA register (41) via the A0 bus (105). What is the stack top address
It is the value of ASP (40) itself. FA on F stage (4)
The operand is fetched with the value of the register (41) and taken into the SD register (52). The value stored in the SD register (52) is the true return address saved on the stack. At the E stage (5), the PCREAD signal (211) causes the EP (6) in the PC stack (46) in which the litter address referenced at the time of pre-return is stored.
The contents of the entry pointed to by 7) are output to the S1 bus (101),
It is taken into the DA latch (48). Then, the contents of the SD register (52) in which the true return address is stored are fetched into the DB latch (49) via the S2 bus (102). ALU
In (50), the pre-returned address is compared with the true return address, and the comparison result is the ZFLAG signal (2
12) is sent to the E stage control unit (63). Also,
At the same time, the contents of the SD register (52) are S2 bus (102), DM
It is saved in the working register in the register file (47) via the latch (56) and the D0 bus (103). EP (67) by EPINC signal (207) after referring to PC stack (46)
Post-increment. If the comparison results are in agreement, it indicates that the pre-return was made to the correct address, and the E stage (5) is 1 microcycle NO.
Execute P to end instruction execution. If the comparison result does not match, it indicates that the return address for which pre-return was performed is incorrect, and the value of the true return destination address saved in the working register is set to the S1 bus (10
1) to the EB register (45) and then to the EB register (4
The value of 5) is output to the CA bus (108) and branch processing is performed. At this time, the BSR counter (65) is cleared by the EBRA signal (204), and the value of EP (67) is copied to DP (66).

(2.2.4) EXITD instruction The EXITD instruction is a high-performance instruction that releases parameters for high-level languages, restores saved registers, returns from subroutines, and releases subroutine parameters on the stack. As shown in FIGS. 4 (E) and (F)
There are two instruction formats, G format and E format, for the EXITD instruction. In the G format, it is processed as three step codes, and in the E format, this instruction is processed as one step code. For the sake of simplicity, only the E format instruction shown in FIG. 4 (E) will be described.

When the EXITD instruction is processed by the instruction decoding unit (22), E
The XITD instruction generates a D code (12) indicating a step code and an A code (13) for transferring an immediate value. The value of the correction value (85B) of the stack pointer is sent as a literal in the D code (12). With this instruction, the value of the bitmap data (85C) of the 2-byte returning register is also fetched at the same time and transferred as the immediate value of the A code (13). This instruction is a pre-return instruction. BR
If the SCZ signal indicates that there is a subroutine call instruction in the pipeline, the processing is suspended until the content of the BSR counter (65) becomes zero. BS
If the R counter (65) is zero, pre-return processing is performed. PC stack (46) by PRERET signal (209)
The contents of the entry pointed to by DP (66) in the CA bus (10
Output to (8) and perform preceding branch processing (pre-return).
After referring to the PC stack (46), the post increment processing of the DP (66) is performed by the DPINC signal (203). In the A stage (3), the immediate value is transferred in the address calculation section (55) in accordance with the instruction of the A code (13) and is written in the FA register (41) via the A0 bus (105). F
At the stage, the value of FA register (41) is SA register (42)
Transferred to. In the E stage (5), after the saved registers are restored from the stack, the stack frame is released, and the frame pointer is restored from the stack, the return address value is popped from the stack and the DD register Take it into (53). In addition, the stack pointer is corrected to release the subroutine parameter. By the PCREAD signal (211), the contents of the entry pointed to by EP (67) in the PC stack (46) that stores the return address referenced at the time of pre-return is stored in the S1 bus (10
It is output to 1) and taken into the DA latch (48). Then, the contents of the DD register (53) in which the true return address is stored are transferred to the DB latch (49) via the S2 bus (102).
Is taken into. The ALU (50) compares the pre-returned address with the true return address, and the comparison result is the ZFLAG signal (212), which is the E stage control unit (6).
3) sent to. At the same time, the contents of the DD register (53) are changed to S2 bus (102), DM latch (56), DD bus (103).
Via the register file (47) to the working register. After referring to the PC stack (46), the EP (67) is post-incremented by the EPINC signal (207). If the comparison results are in agreement, it indicates that the pre-return was made to the correct address, and the E stage is 1
The micro cycle NOP is executed to terminate the execution of the instruction. If the comparison result does not match, it indicates that the return address for which pre-return was performed is incorrect, and the value of the true return destination address saved in the working register is sent via the S1 bus (101). EB register (45)
And the value of the EB register (45) is output to the CA bus (108) for branch processing. At this time, the EBRA signal (20
4) clears BSR counter (65) and DP (66)
The value of EP (67) is copied to.

As mentioned above, even with the EXITD instruction, the PC stack (46)
The processing regarding is the same as the RTS instruction.

(2.3) Description of Other Embodiments In this embodiment, the PC stack (46) is composed of 8 entries. Therefore, when a subroutine call is nested in 9 levels or more, another return address is overwritten in the entry in which a valid return address is stored, and the first value disappears. Therefore, except for a special case where a recursive call is made, an erroneous pre-return will be made when nesting 9 levels or more. Also, even if the return address on the external memory is rewritten by the program, pre-return will be performed to the wrong return address. Therefore, it is necessary to check whether the pre-return was correct at the E stage. The number of PC stack entries to be provided can be determined in consideration of the performance problem of how many levels of depth the subroutine call is made and the correct pre-return, and the amount of hardware increase.

In this embodiment, in order to guarantee the correct operation even if the return address from the subroutine is rewritten in the subroutine, the correct return address from the subroutine fetched from outside the CPU during execution of the RTS instruction and the PC stack (46) The addresses used for fetching and pre-returning are compared. If it is only necessary to execute the software that does not rewrite the return address from Saburchin (the return address from the subroutine is hardly rewritten in the actual application program), the subroutine There is no need to fetch the return address. It is only necessary to check whether or not the return address of the subroutine in the PC stack (46) is rewritten by providing a flag indicating whether the PC stack value is valid or invalid. In other words, if the consistency of the stack with the return address from the subroutine in the memory outside the CPU is guaranteed,
Only the management mechanism of the PC stack (46) judges whether the pre-return is correct, and only when the correct return address of the subroutine cannot be obtained from the PC stack, the return address of the subroutine is fetched from the memory outside the CPU. And return to that address.

In this embodiment, the BSR is
Although it has a counter (65), if the pre-branch processing of the subroutine call instruction is not performed, the branch processing to the jump destination address is always performed after the subroutine call instruction is executed, and the pipeline is canceled. No function required. Also, the pointer DP (66) is decremented when the BSR instruction is decoded in the D stage (2),
When the BSR instruction is executed at the E stage (5), the value of the decremented pointer EP (67) may be copied.

Further, in this embodiment, in order to check whether or not the pre-return is correctly performed at the E stage (5),
The return address after pre-returning from the PC stack (46) is referenced and compared with the correct return address fetched from the memory outside the CPU, but pre-returning was performed at the D stage (2). The return address may be saved, and the saved value may be referred to in the E stage (5).

Further, in the present embodiment, the counter is used as a means for detecting whether or not the stage subsequent to the D stage (2) is processing the subroutine call instruction. However, each step code or each pipeline stage uses the counter for the subroutine call instruction. The flag may be provided, and the pre-return processing may be performed only when all the flags are not set. Even if the function of the BSR counter or the above flag that replaces it is removed to reduce the hardware, it is checked whether the pre-return was correct when the subroutine return instruction is executed, so correct operation can be performed. it can. The performance degradation at this time depends on how often the subroutine call instruction and the corresponding subroutine return instruction are simultaneously fetched into the pipeline.

In the present embodiment, the pointer DP (6) managed by the D stage (2) is used as the pointer of the PC stack (46).
6) and the pointer EP (6
It has two pointers of 7). This is so that the correct return address can be referred to even when a plurality of subroutine return instructions are processed in the pipeline. EP (67) changes corresponding to the subroutine call instruction and the subroutine return instruction executed in the E stage (5). Since DP (66) changes at the instruction decoding stage, even if two or more subroutine return instructions are taken into the pipeline, the return address of the corresponding subroutine call instruction can be referred to. Since the pipeline is canceled when the branch processing is performed in the E stage (5), the value of EP (67) is copied to DP (66). When the subroutine return instruction is executed, it is checked whether the pre-return was correct, so even if all the pointer management of the PC stack (46) is performed only by EP (67) to reduce the hardware, the correct operation will be performed. be able to. The performance degradation in this case is
It depends on how often two or more subroutine return instructions are simultaneously captured in the pipeline. When the number of pointers is one, a flag for the subroutine return instruction is provided, the flag is set when the subroutine return instruction is being executed in the stages after the A stage (3), and the flag is set when the flag is set. By waiting for the return process, the PC stack (46) can be referenced after the pointer is properly switched, and thus the correct pre-return can be performed.

Further, the PC stack (46) of the present invention can be accessed at the time of pre-return as well as when it is determined whether the pre-return is correctly performed, and it is efficient to perform the access independently of the memory access outside the CPU. Therefore, in a data processing device such as a microprocessor in which the CPU is realized by one integrated circuit chip, if the PC stack (46) is provided in the same integrated circuit as the CPU, memory access outside the CPU is independent. PC
The stack (46) is accessible.

This invention can be implemented by the embodiments of the following (1) to (7).

(1) An instruction is processed by a pipeline process that has a first stage and a second stage, and for the execution of the instruction, the processing in the first stage precedes the processing in the second stage. A first memory device for storing instructions and data, a second memory device different from the first memory device for storing an address value of a return destination instruction from the subroutine, and a data processor First writing means for writing a value to be a return address to the first storage device; second writing means to write a value to be a return address from a subroutine to the second storage device; Controlled by the stage of the first value of the second
Reading means for reading from the storage device, second reading means for reading a second value serving as a return address from the subroutine from the first storage device during processing of a subroutine return instruction, and subroutine return The instruction fetch unit includes a determination unit that determines whether the first value is a return address from a subroutine during instruction processing, and an instruction fetch unit that fetches an instruction from the first storage device. , A function of fetching a first instruction from the address indicated by the first value of the first storage device, and a second instruction fetch from the address indicated by the second value of the first storage device A function is provided, and at the time of processing a subroutine return instruction, the determination means determines that the first value is a return address from the subroutine. The data processing device, wherein the first instruction is executed when the second instruction is executed, and the second instruction is executed when the determination means determines that the first value is not the return address from the subroutine. .

(2) The judging means is a comparing means for comparing the first value and the second value, and when the comparison results match by the comparing means, the first value is a return address from the subroutine. The data processing device according to claim 1, wherein it is determined that the first value is not the return address from the subroutine when the comparison result by the comparison means does not match.

(3) The second storage device is a stack storage device configured by a plurality of entries with cyclic numbers and a first pointer register for managing the cyclic numbers. The data processing device according to item 1.

(4) The second storage device is composed of 2 ⁿ entries and can be incremented or decremented by at least one of them, and the first n-bit counter for managing the number of the entry and both the incrementation and decrement Possible,
A second n-bit counter that manages the number of the entry; a third reading unit that reads from the entry indicated by the value of the second n-bit counter of the second storage device; and the second n-bit counter From the subroutine to the entry number indicated by the value of the second n-bit counter of the second storage device. The first read means is means for reading the first value from the entry indicated by the value of the first n-bit counter of the second storage device, The data processing device according to claim 2, wherein the means compares the first value obtained by reading by the third reading means with the second value.

(5) Subroutine call instruction for detecting whether or not the processing of writing the address of the return destination instruction from the subroutine to the second storage device has been completed for all the subroutine call instructions that have been processed in the first stage The data processing apparatus according to claim 1 or 4, further comprising processing detection means.

(6) A first storage device for storing instructions and data, and a first storage device.
Unlike the above memory device, it stores the address value of the return destination instruction from the subroutine, and it is possible to increment or decrement the second memory device consisting of 2 ⁿ entries and manage the number of the entry. The first n-bit counter that does, and can both increment and decrement,
A second n-bit counter for managing the number of the entry; a first reading means for reading a value from the entry indicated by the value of the first n-bit counter of the second storage device; Second read means for reading a value from an entry indicated by the value of the second n-bit counter of the storage device; and an entry indicated by the value of the second n-bit counter of the second storage device from the subroutine. A data processing device, comprising: a first writing unit that writes an address of a return destination instruction; and a second writing unit that writes the value of the second n-bit counter to the first n-bit counter. .

(7) A storage device that stores the address value of the return destination instruction from the subroutine, a storage device that is made up of 2 ⁿ entries, and a first n-bit counter that can increment or decrement and that manages the entry number , Both increment and decrement are possible,
A second n-bit counter for managing the number of the entry; first reading means for reading a value from the n-bit counter indicated by the value of the first n-bit counter of the second storage device; Second reading means for reading a value from the n-bit counter indicated by the value of the second n-bit counter of the second storage device; and an entry indicated by the value of the second n-bit counter of the second storage device. A first writing means for writing an address of a return destination instruction from the subroutine, and a second writing means for writing the value of the second n-bit counter to the first n-bit counter; And a data processing device provided in the integrated circuit.

〔The invention's effect〕

As described above, according to the present invention, by providing the PC stack that stores only the return address of the subroutine call instruction, the branch processing of the subroutine return instruction can be performed prior to the processing at the instruction execution stage,
Since the overhead of pipeline processing due to the execution of the subroutine return instruction is reduced, a high-performance data processing device can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a pipeline processing configuration of a data processing device of the present invention, FIG. 2 is a block diagram of the data processing device of the present invention, and FIG. 3 is a preceding branch of a subroutine return instruction in the data processing device of the present invention. FIG. 4 is a block diagram of a portion particularly related to processing, FIG. 4 is a diagram showing bit allocation of a subroutine call instruction and a subroutine return instruction in the data processing device of the present invention, FIG. 5 is a flowchart of BSR instruction execution, and FIG. 6 is RTS. FIG. 7 is a flow chart of instruction execution, and shows a typical pipeline stage of a conventional data processing device. (46) is a PC stack that stores only the return address of a subroutine call instruction, (65) is a BSR counter that counts the number of subroutine call instructions being processed in the instruction decode stage and subsequent stages, and (66) is instruction decode A pointer DP of the PC stack (46) managed by the stage is a pointer EP of a PC stack (46) managed by the instruction execution stage. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A first stage and a second stage,
What is claimed is: 1. A data processing device for processing an instruction by pipeline processing, wherein the processing in the first stage precedes the processing in the second stage, comprising: an instruction storage device for storing the instruction; 1 storage device, a second storage device different from the first storage device that stores the address value of the return destination instruction from the subroutine, and a value that becomes the return destination address from the subroutine when the subroutine call instruction is processed. First writing means for writing to a first storage device; second writing means for writing a value serving as a return address from a subroutine to the second storage device during processing of a subroutine call instruction; and the first stage And a second read means for reading a first value from the second storage device when processing a subroutine return instruction. And a second value which is a return address from the true subroutine and is read from the first storage device when the subroutine return instruction is processed.
Read means, a judgment means for judging whether the first value is a return address from a true subroutine at the time of processing a subroutine return instruction, and an instruction fetch means for fetching an instruction from the instruction storage device. The instruction fetch unit specifies the address indicated by the first value from the instruction storage device prior to the completion of the reading of the second value by the second reading unit during processing of a subroutine return instruction. And a function of fetching a second instruction designated by the address indicated by the second value from the instruction storage device. When the judging means judges that the first value is a return address from a true subroutine, the first instruction is executed. However, when the judging means judges that the first value is not the return address from the true subroutine, the preceding processing in the pipeline of the first instruction is invalidated and the second instruction is executed. A data processing device characterized by the above. 2. A first stage and a second stage,
A data processing device for processing instructions by pipeline processing performed in the first stage prior to the processing in the second stage, comprising: a first storage device for storing instructions and data; Unlike the first storage device, it stores the address value of the return destination instruction from the subroutine, and can be incremented or decremented by the second storage device consisting of 2 ⁿ entries, and the entry number A first n-bit counter that manages, a second n-bit counter that can both increment and decrement, and that manages the number of the entry, and a second n-bit counter that manages the number of the entry at the first stage when processing a subroutine return instruction. Reading means for reading a value from the entry indicated by the value of the first n-bit counter of the storage device, Second read means for reading a value from the entry indicated by the value of the second n-bit counter of the second storage device in the second stage during return instruction processing; The first address of the return destination instruction from the subroutine is written into the entry indicated by the value of the second n-bit counter of the second storage device.
Writing means and the second n stage when the pre-processing performed prior to the second stage in the first stage is invalidated.
A second writing means for writing the value of the bit counter to the first n-bit counter, and a data processing device. 3. A first stage and a second stage,
A data processing device for processing an instruction by pipeline processing performed in the first stage prior to the processing in the second stage, storing the address value of a return destination instruction from a subroutine,
A storage device consisting of 2 ⁿ entries, a first n-bit counter capable of incrementing or decrementing and managing the number of the entry, and a first n-bit counter capable of incrementing and decrementing and managing the number of the entry A second n-bit counter, and a first reading unit that reads a value from an entry indicated by the value of the first n-bit counter of the storage device in the first stage during processing of a subroutine return instruction, Second read means for reading a value from the entry indicated by the value of the second n-bit counter of the storage device in the second stage during processing of the subroutine return instruction; and the storage device during processing of the subroutine call instruction. Return from the subroutine to the entry indicated by the value of the second n-bit counter of When the first writing means for writing the address of the previous instruction, prior to said second stage was performed prior at the first stage processing is disabled, the second n
A data processing device comprising: a second writing means for writing a value of a bit counter into the first n-bit counter; and a second writing means in the same single integrated circuit as the CPU.