JPH0769807B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for performing multi-stage pipeline processing, and more particularly to a data processing device for performing multi-stage pipeline processing of branch instructions.

[Conventional technology]

FIG. 5 is a block diagram for explaining the pipeline processing configuration of the conventional data processing apparatus, and the configuration and operation will be described below.

The instruction fetch stage (IF stage) 51 fetches an instruction code from the memory and outputs it to the instruction decode stage (D stage) 52. D stage 52 is IF stage 51
The instruction code input from is decoded, and the decoded result is the operand address calculation stage (A stage) 53
Output to. The A stage 53 calculates the execution address of the operand specified in the instruction code, and outputs the calculated operand address to the operand fetch stage (F stage) 54. The F stage 54 fetches an operand from the memory according to the operand address input from the A stage 53. Output to the fetched operand instruction execution stage (E stage) 55. E stage 55
Executes the operation specified in the instruction code on the operand input from the F stage 54, and stores the operation result in the memory as necessary.

The pipeline processing mechanism decomposes the process specified by each instruction into five processes, and executes the five processes in order to complete the specified process. Each of the five processes can be operated in parallel for different instructions. Ideally, the five-stage pipeline processing mechanism processes five instructions at the same time, compared to the case where no pipeline processing is performed. As a result, data processing having a maximum processing capacity of 5 times can be executed.

The conventional pipeline processing can significantly improve the processing capacity by executing, for example, five stages of processing as described above, and can greatly contribute to high-speed processing of data, but disturb the instruction sequence. With respect to branch instructions, ideal pipeline processing may not always be executed.

Particularly, in a data processing device for performing pipeline processing as shown in FIG. 5, when a branch instruction is processed by the E stage 55 and then a branch destination instruction is processed by the IF stage 51, the pipeline processing is significantly disturbed.

FIG. 6 is a schematic diagram for explaining an instruction execution cycle of each stage related to branch instruction processing, where the vertical axis shows each stage and the horizontal axis shows time. The instructions 3 and 12 are branch instructions.

When the instruction 3 is executed, the instructions 4 to 7 which are already pipelined are canceled, and the instruction 11 is newly processed from the IF stage 51.

From the time the instruction 3 is executed in the E stage 55 to the time the instruction 11 is executed in the E stage 55, the time for processing four instructions is wasted, and the time for processing four instructions is the same for the instruction 12. To be wasted. This dead time is because the instruction fetch to be processed after the execution of the branch instruction is executed after all the pipeline processing for the branch instruction is completed, and the larger the number of stages of the pipeline processing, the longer the dead time. .

In order to reduce the disturbance of the pipeline due to the branch instruction, the branch of the conditional branch instruction is predicted at the stage of decoding the instruction at the D stage 52, and the IF of the IF instruction is executed before the branch instruction is executed at the E stage 55. Conventionally, a branch prediction process of changing the instruction fetch destination by the stage 51 to a branch destination has been executed.

That is, in the D stage 52, by predicting the branch of the conditional branch instruction at the stage of decoding the instruction, the instruction fetch is switched to the branch destination in advance, so that the pipeline processing efficiency is generally improved.

[Problems to be Solved by the Invention]

The conventional branch prediction process is executed using the address of the instruction decoded one before the conditional branch instruction. If a branch instruction is executed in the E stage 55 and a branch actually occurs, all the instructions being processed in the pipeline are canceled. Then, immediately before being canceled, the branch prediction mechanism makes a branch prediction at the address of the instruction following the branch instruction, so that the prediction has nothing to do with the instruction at the branch destination. there were.

That is, when the branch prediction is performed using the address of the instruction decoded immediately before, the branch prediction of the instruction decoded immediately after the branch in the E stage 55 becomes a misleading process.

The present invention has been made to solve the above problems, and holds information indicating immediately after a branch in an instruction execution stage to perform branch prediction processing for an instruction decoded immediately after a branch in an instruction execution stage. The purpose is to obtain a data processing device that can always predict that "no branching" will occur.

[Means for Solving the Problems]

The data processing apparatus according to the present invention holds the generation means indicating the occurrence of the second branch processing, and the branch prediction result in the first pipeline processing stage immediately after the occurrence of the second branch processing. Branch prediction control means for making non-branch based on the occurrence information held in the means.

[Action]

In the present invention, when the second branch processing is executed in the second pipeline processing stage based on the unit processing code transferred from the first pipeline stage, the occurrence information indicating the occurrence of the second branch processing is generated. Are held by the holding means. Then, immediately after the occurrence of the second branch processing, the first branch processing is performed.
The branch prediction control means sets the branch prediction in the instruction decoding mechanism to non-branch based on the occurrence information held in the holding means, and the branch prediction mechanism uses the instruction decoding mechanism. Predict not to branch.

〔Example〕

FIG. 1 is a block diagram for explaining the configuration of a data processing device showing an embodiment of the present invention. Reference numeral 1 is an instruction fetch unit, which is composed of a branch buffer, an instruction queue, a control unit, etc. and should be fetched next. Determines the address of the instruction and fetches the instruction from the branch buffer or memory outside the CPU. Also, for example, instruction registration in the branch buffer described in Japanese Patent Application No. 61-202041 is performed.

Since the branch buffer is small, it operates as a selective cache.

When fetching an instruction from a memory external to the CPU, the instruction decode unit 2 outputs the instruction code to the external bus interface unit, fetches the instruction code from the data input / output circuit 9, and then decodes the buffered instruction code by the instruction decoding unit 2. The instruction code to be output is output to the instruction decoding unit 2.

The instruction decoding unit 2 (included in the first pipeline stage) basically decodes the instruction code in 16-bit (halfword) units. This block includes an FHW decoder that decodes the operation code included in the first halfword, an NFHW decoder that decodes the operation code included in the second and third halfwords, and an addressing mode decoder that decodes the addressing mode. The instruction decoding unit 2 is provided with the holding unit and the branch prediction control unit of the present invention, and the second unit based on the unit processing code transferred from the first pipeline stage (D stage described later). When the second branch processing is executed in the pipeline processing stage (E stage to be described later) of, the holding information holds the occurrence information indicating the occurrence of the second branch processing. Immediately after the occurrence of the second branch processing, the branch prediction control means holds the result of the first branch prediction processing predicted in the first pipeline stage in the branch prediction table (holding means) shown in FIG. Based on the generated information, the branch prediction mechanism causes the instruction decoding mechanism to predict "no branch".

Furthermore, a decoder that further decodes the outputs of the FHW decoder and NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that performs branch prediction of conditional branch instructions, an address that checks pipeline conflicts when calculating operand addresses. A calculation conflict check mechanism is also provided.

The instruction decoding unit 2 decodes the instruction code input from the instruction fetch unit 1 into 0 to 6 bytes every 2 clocks.

Among the decoding results, the information related to the operation in the data operation unit 6 is output to the micro ROM unit 5, the information related to the operand address calculation is output to the operand address calculation unit 4, and the information related to the program counter calculation is output to the PC calculation unit 3, respectively. It

The PC calculation unit 3 is hard-wired controlled by the information related to the PC calculation output from the instruction decoding unit 2,
Calculate the PC value. The data processing device in this embodiment has a variable length instruction set described later, and the length of the instruction cannot be known unless the instruction is decoded. Therefore, the PC calculating unit 3 creates the PC value of the next instruction by adding the instruction length output from the instruction decoding unit 2 to the PC value of the instruction being decoded. When the instruction decoding unit 2 decodes a branch instruction and gives an instruction to branch at the decoding stage, the branch displacement is added to the PC value of the branch instruction instead of the instruction length, so that the PC
Calculate the value. Pre-branching is the branching of a branch instruction at the instruction decoding stage. Regarding the processing of this pre-branch, Japanese Patent Application Nos. 61-204500 and 6-6
Since it is described in detail in No. 1-200557 etc., its explanation is omitted.

The calculation result of the PC calculation unit 3 is output as the PC value of each instruction together with the instruction decode result, and is output to the instruction fetch unit 1 as the address of the next instruction to be decoded during pre-branching.

It is also used as an address for branch prediction of an instruction decoded by the next instruction decoding unit 2. The branch prediction process is described in detail in Japanese Patent Application No. 62-8394.

The operand address calculation unit 4 is hard-wired controlled by the information related to the operand address calculation output from the address decoder of the instruction decoding unit 2 or the like. In this block, most of the processing for calculating the address of the operand is performed. The address calculation result is sent to the external bus interface 7. The values of general-purpose registers and program counters required for address calculation are input from the data calculation unit 6. When performing the memory indirect addressing, the address output circuit 8 outputs the memory address to be referred to outside the CPU through the external bus interface unit 7 as it is, and the indirect address value input from the data input / output circuit 9 is output. Fetch through the instruction decoding unit 2.

The micro ROM unit 5 is provided with a micro ROM that mainly stores a micro program that controls the data operation unit 6, a micro sequencer, a micro instruction decoder, and the like. Micro instructions are sent from the micro ROM once every two clocks.
Read once. The micro sequencer accepts, in addition to the sequence processing indicated by the micro program, exception, interrupt, and trap processing (these three processings are collectively called EIT processing) by hardware.

The micro ROM unit 5 also manages the store buffer. The micro ROM unit 5 receives the interrupt information not depending on the instruction code and the flag information based on the operation execution result, and the output of the instruction decoding unit 2 such as the output of the decoder. The output of the microdecoder is mainly output to the data operation unit 6, but some information such as other preceding instruction stop information due to execution of the jump instruction is output to other blocks.

The data calculation unit 6 is controlled by a micro program,
According to the output information of the micro ROM unit 5, the operations required to realize the function of each instruction are executed by the register and the arithmetic unit.
If the operand to be operated is an address or immediate value,
The address or immediate value calculated by the operand address calculation unit 4 is obtained by passing through the external bus interface unit 7. When the operand to be operated is the data in the memory outside the CPU, the external bus interface unit 7 outputs the address calculated by the operand address calculation unit 4 from the address output circuit 8 The fetched operand is obtained from the data input / output circuit 9.

The arithmetic unit includes an ALU, barrel shifter, priority encoder, counter, shift register and the like. The registers and main arithmetic units are connected by three buses, and one microinstruction for instructing one inter-register operation is processed in two clock cycles.

When it is necessary to access the memory outside the CPU during data operation, the address is output from the address output circuit 8 to the outside of the CPU through the external bus interface section 7 according to the instruction of the microprogram, and the target is output through the data input / output circuit 9. Fetch the data.

When reading data from a memory external to the CPU, the address is set in the AA1 register to be described later, the address is output from the address output circuit 8 through the external bus interface unit 7, and the data is input from the data input / output circuit 9 to the DD described later. It is taken into the DDR1 register 6b through the bus 18. When writing data to the memory outside the CPU, set the address described below in the AA1 register, output that address from the address output circuit 8 through the external bus interface unit 7, and set the data set in the DD2 register 6c to the DD bus 18 Through the data input / output circuit 9 to the outside of the CPU.

When the data operation unit 6 obtains a new instruction address by performing a jump instruction process, an exception process, or the like, this is output to the instruction fetch unit 1 and the PC calculation unit 3.

The external bus interface unit 7 controls communication on the external bus, and particularly memory access is performed in clock synchronization and can be performed in a minimum of two clock cycles.

An access request to the memory is independently generated from the instruction fetch unit 1, the operand address calculation unit 4, and the data operation unit 6, and further, an access request for performing the operand prefetch is also generated. The external bus interface unit 7 arbitrates these memory access requests. Furthermore, access to data at a memory address that crosses a 32 bit (word) aligned boundary, which is the size of the data bus connecting the memory and the CPU, automatically detects that the word boundary is crossed within this block. It is performed by breaking it down into memory accesses.

When the prefetch operand and the store operand overlap, conflict prevention processing and bypass processing from the store operand to the fetch operand are also performed.

When there is an access request from the instruction fetch unit 1, an address is set in the CAA register described later.
When there is an access request from the operand address calculation unit 4, the address is set in the IA register described later. If there is an access request from the data calculation unit 6,
An address is set in the AA1 register described later.

When there is an access request for prefetching the operand, the address set in the FA register described later is output to the AA bus, and the operand data is fetched from the memory outside the CPU. The fetched operand data is input to the latch SDATA (see FIG. 2) through the DD bus. Further, the address on the AA bus used for access is input to the latch SCAM. The latch SCAM and the latch SDATA are connected by a match instruction line. Up to two aligned 4-byte data are stored in the latch SDATA. The address corresponding to the data in the latch SDATA is stored in the latch SCAM. Data is input to the latch SDATA in an aligned manner, but when the data operation unit 6 takes out and uses the data, it can be taken out from any address with any data length (however within 4 bytes).

Next, the data processing of the branch instruction according to the present invention will be described with reference to FIGS. 2 and 3.

The branch instruction type in this embodiment will be described.

In the data processing device according to the present invention, an instruction for performing dynamic branch prediction processing is called a pre-branch instruction, and this pre-branch instruction includes an instruction that always branches regardless of dynamic prediction, such as an unconditional branch instruction. The branch instructions can be classified into four types in total depending on whether the branch condition is static or dynamic and whether the branch destination is static or dynamic. In this embodiment, the instructions classified into the following two types are pre-branch instructions. .

The first type of branch instruction is a static instruction with both a branch condition and a branch destination. For this type of instruction, an unconditional branch instruction (BRA instruction) and a subroutine call instruction (BSR instruction)
There is.

The second type of branch instruction has a dynamic branch condition,
The branch destination is a static instruction. Examples of this type of instruction include conditional branch instructions (Bcc instructions) and loop control instructions (ACB
There is an instruction).

FIG. 2 is a detailed block diagram showing the configuration of the data processing device shown in FIG. 1. The configuration and operation will be described below.

Input side of instruction decoder 2a and PC adder 3b, address adder
The input side of 4d is connected by the DISP bus 10 which transfers the displacement value and the displacement value of the branch instruction.

The instruction decoder 2a and the input side of the address adder 4d are also connected to a correction value bus 12 that transfers the instruction code length used for step code generation, the pre-decrement value in the stack push mode, and the like. Instruction decoder 2a and PC adder
The input side of 3b is also connected to an instruction length bus 11 that transfers the instruction code length used for step code generation. The input side of the register file 6d and the address adder 4d transfers the address value stored in the register file 6d to the A bus 13
Tied with.

The instruction code is input to the instruction decoder 2a from the instruction queue 2b, and the branch prediction bit is input from the branch prediction table 2c. Whether the branch condition designation field of the conditional branch instruction is output to the instruction execution stage (second pipeline processing stage) as it is or the condition designation is inverted and output to the output unit of the instruction decoder 2a according to the branch prediction result. It has a branch condition generation circuit 2d for selecting.

The output of the added value selection circuit 3a which selects and inputs either the value of the instruction length bus 11 or the value of the DISP bus 10 and the instruction decoded by the decode stage (described later) which is the first pipeline processing stage. Either the DPC latch 3e that holds the PC value (program counter value) or the TPC latch 3d that holds the working PC value at each step code break is input to the PC adder 3b. The output of the PC adder 3b is output to the CA bus 14 and the PO bus 15 through the PC adder output latch 3c. PO
The bus 15 is also connected to the TPC latch 3d, the DPC latch 3e, the APC latch 3f that holds the PC value of the instruction being processed in the operand address calculation stage, and the branch prediction table 2c. T
The PC latch 3d has a CA bus 14 for inputting a new instruction address when a branch or jump occurs at the instruction execution stage.
There is also an input path from.

The output of the correction value bus 12 and the output of the DISP bus 10 are input to the displacement selection circuit 4b, and one of them is input to the address adder 4d. DISP bus 10 output and A bus 13
Is output to the base address selection circuit 4c, and one of them is input to the address adder 4d. The address adder 4d shifts the output of the displacement selection circuit 4b, the output of the base address selection circuit 4c, and the value input from the A bus 13 to obtain a value of 1 ×, 2 ×, 4 ×, 8 ×. The sum of the three input values of the output of the index value generation circuit 4a is added, and the addition result is the address adder output latch.
It is output to the AO bus 16 via 4e. The AO bus 16 outputs the address value from the address output circuit 8 to the outside of the CPU through the AA bus 17 when performing the memory indirect addressing, the IA latch 7a that holds the address value, and the operand fetch at the operand fetch stage, AA bus
When the operand output value is output from the address output circuit 8 to the outside of the CPU through 17, it is connected to the FA latch 7b that holds the operand address.

The FA latch 7b has an output path to the SA latch 7c that holds the operand address value for using the operand address calculated by the address adder 4d in the instruction execution stage. The SA latch 7c also has an output path to the S bus 19 which is a general-purpose data bus of the data calculator 6e. The CA bus 14 that transfers the address of the instruction is the PC adder output latch 3c and the TPC latch 3d.
, A counter QINPC that manages the address of the instruction code prefetched by the instruction fetch stage, and an address output circuit 8 for the address for instruction fetch through the AA bus 17.
CAA latch that holds the value when it is output from the CPU to the outside of the CPU
7e and the EB latch 6a which inputs a new instruction address from the SBus 19 when a branch jump occurs in the instruction execution stage. The APC latch 3f is an A bus 13 and an FP that holds the PC value of the instruction being processed in the operand fetch stage.
There is an output path in C latch 3g. 7d is the AA1 latch.

The FCP latch 3g has an output path to the CPC latch 3h which holds the PC value of the instruction being processed in the instruction execution stage. CPC latch
3h has an output path to the S bus 19 and an OPC latch 3i which holds the value of the least significant byte of the PC value for rewriting the branch history. The register file 6d includes general-purpose registers and working registers, has an output path to the S bus 19 and the A bus 13, and has an input path from the D bus 20.

The data calculator 6e, which is the calculation mechanism of the data calculator 6, has an input path from the S bus 19 and an output path to the D bus 20.

In the data processing device in this embodiment,
Unconditional branch instruction BRA, subroutine branch instruction BSR, loop control instruction ACB, and other three instructions are always predicted to branch regardless of the branch prediction bit output from the branch prediction table. This prediction is always correct for unconditional branch instructions BRA and subroutine branch instructions BSR.

The loop control instruction ACB is an instruction that adds a specified value to a loop control variable and determines whether or not the result satisfies a loop end condition, branches if the loop end condition is not satisfied, and does not branch if the loop end condition is satisfied. Therefore, the majority of software is correct in establishing this prediction for the loop control instruction ACB. Further, if the software is created in consideration of the processing for the loop control instruction ACB, it is possible to create an efficient program as compared with the case where the software is not considered.

For the conditional branch instruction BCC, whether to branch or not is determined according to the past history. That is, the history is
It is performed based on the lower 8 bits of the address of the instruction executed immediately before the conditional branch instruction BCC, and branch prediction is indicated by 1 bit according to only the branch history of the past one time.

FIG. 3 is a detailed block diagram for explaining the configuration of the branch prediction table 2c shown in FIG. 2, and the configuration and operation will be described below.

The 7-bit input from the PO bus 15 and the 7-bit input from the OPC latch 3i are input to the decoder 22 through the selector 21. The decoder 22 decodes 7 bits into 128 bits, and outputs one of the 128-bit branch history latches 23 as a branch prediction value to the branch prediction output latch 24 through the branch prediction signal line 29. When the clear signal 27 is input to the 128-bit branch history latch 23, the values are simultaneously set to zero, and the state indicates “no branch”.

The branch prediction output latch 24 has its contents inverted by a prediction inversion circuit 25 and is coupled to a branch prediction update latch 26. The branch prediction control flag 28 is composed of an SR type flip-flop, and the output is an AND gate as the branch prediction permission signal line 33.
Connected to 30. The branch prediction control flag 28 has an output of "0" in response to the branch occurrence signal 31 and an output of "1" in response to the 1-instruction decoding completion signal 32. A branch prediction signal line 34 outputs the branch history information read by the branch prediction output latch 24 to the AND gate 30.

In this embodiment, the lower 8 bits of the address of the instruction decoded in the D stage 52 immediately before the instruction to be decoded in the D stage 52 (the least significant bit (rightmost bit) of the instruction address is always Since it is "0", the branch prediction table 2c is composed of 128 bits) and the branch prediction is performed by subtracting the branch prediction table 2c. The branch prediction is registered by the direct mapping method according to only the past history.

Next, the operation will be described.

For the branch history of the branch prediction table 2c, the clear signal 27 sets all initial values to "no branch". The branch prediction is updated when the conditional branch instruction BCC branches at the instruction execution stage. When the conditional branch instruction BCC takes a branch at the instruction execution stage, it means that the branch prediction at the instruction decode stage was incorrect. Therefore, in the instruction execution stage, the contents of the OPC latch 3i are transferred to the decoder 22, and the branch history latch 23 corresponding to the decoding result is transferred.
The content of is read to the branch prediction output latch 24. Next, the contents of the branch prediction update latch 26 in which the contents of the branch prediction output latch 24 are inverted are written back to the branch history latch 23 also shown by the OPC latch 3i.

Since the branch prediction is performed based on the PC value of the instruction that was decoded just before the target conditional branch instruction BCC is decoded, the branch prediction table 2c is also updated at the instruction execution stage by 1 of the conditional branch instruction BCC. Performed based on the PC value of the last executed instruction. Therefore, in the instruction execution stage, there is an OPC latch 3i that stores the lower 1 byte (the least significant bit is not necessary) of the PC value of the instruction executed immediately before the currently executing instruction, and the branch prediction table 2c Update is performed using this value. Since the branch history is updated only when the conditional branch instruction BCC causes a branch at the instruction execution stage,
The reference operation of the branch prediction table 2c of the instruction decode stage is not hindered by the update of the instruction execution stage. Immediately after the branch occurs in the instruction execution stage, the instruction decode stage is in a state of waiting for the instruction code from the instruction fetch stage. Rewriting of the branch history is performed during this instruction code waiting state.

On the other hand, when a branch occurs in the instruction execution stage, the branch occurrence signal 31 becomes "1" and the branch prediction permission signal line 33 which is the output of the branch prediction control flag 28 becomes "0". At this time,
Branch prediction signal line 34 output from the branch prediction output latch 24
Is ANDed with the branch prediction permission signal line 33, and the AND output is input to the instruction decoder 2a. Therefore, while the branch prediction permission signal line 33 is "0", predict "no branch". Becomes The one-instruction decode completion signal 32 is output to the branch prediction control flag 28 when the decoding of one instruction is completed. After the branch occurrence signal 31 is output, the branch target instruction is decoded, and the 1-instruction decoding completion signal 32 is input to the branch prediction control flag 28, the branch prediction enable signal line
33 becomes "1", and the branch prediction value read to the branch prediction output latch 24 via the branch prediction signal line 34 is the instruction decoder.
It is output to 2a.

As described above, branch prediction can always be predicted as "no branch" for an instruction immediately after a branch in the instruction execution stage.

Next, the pipeline processing operation according to the present invention will be described with reference to FIG.

FIG. 4 is a block diagram for explaining the pipeline processing operation according to the present invention.

In this figure, 35 is an instruction fetch stage (IF stage), which prefetches instructions and outputs the instruction code to the subsequent stage. A decode stage (D stage) 36 decodes an instruction code, performs operand address calculation, and outputs a D code 42 which is an intermediate decoding result of the operation code and an A code 43 which is address calculation information to a subsequent stage. An operand address calculation stage (A stage) 37 outputs an R code 44 consisting of a register or memory write reservation, an entry address of the microprogram and parameters for the microprogram, and an F code 45 resulting from the address calculation. 38
Is an operand fetch stage (F stage), which is composed of an R stage 40 that performs micro ROM access and an OF stage 41 that performs prefetch of operands.
40 generates an E code 46 that is an execution control code, and the OF stage 41 outputs the fetched operand S code 47 to the execution stage (E stage) 39, for example. Run.
In addition, in the E stage 39, in addition to the one-stage store buffer, a part of the high-performance instructions pipelines the instruction execution itself, so that the processing equivalent to the pipeline processing of five or more stages can be actually performed.

Also, each stage operates independently of the other stages,
In theory, the five stages operate completely independently. Each stage can execute one processing in a minimum of 2 clocks. Further, in the data processing device in this embodiment, there are instructions that cannot be processed by only one basic pipeline processing such as memory-memory operation and memory indirect addressing. It is designed so that it can perform pipeline processing. For an instruction having a plurality of memory operands, the pipeline processing is performed by decomposing into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands. Particularly, the method of disassembling the pipeline processing unit is described in detail in Japanese Patent Application No. 61-236456, and the description thereof is omitted here.

Next, the processing operation of each stage will be described.

The information passed from the IF stage 35 to the D stage 36 is the instruction code itself. D stage 36 to A stage 37
There are two pieces of information that are passed to each of the two: the D code 42 related to the operation designated by the instruction and the A code 43 related to the operand address calculation. The information passed from the A stage 37 to the F stage 38 includes the entry address of the microprogram routine and the parameters to the microprogram.
There are two, code 45. F stage 38 to E stage 39
The information passed to E includes E control information and literals.
Code 46 and S containing operand and operand address
Two with code 47.

EIT processing detected in stages other than E stage 39
The EIT process is not started until the code reaches the E stage 39. That is, only the instruction processed in the E stage 39 is the instruction in the execution stage, and the IF stage 35-
The instruction processed in the F stage 38 has not yet reached the execution stage. Therefore, the EI detected in other than E stage 39
The T stores the detected result in the step code and transmits it to the next stage.

Next, the processing unit of the pipeline will be described.

In the data processing device according to this embodiment, since the pipeline processing that makes the best use of the characteristics of the instruction format is performed, D
In the stage 36, the 2-byte instruction basic part + 0 to 4-byte addressing modification part, the multi-stage indirect mode designating part + addressing modification part or the instruction-specific extension part is processed as one decoding unit. The decoding result of each time is called a step code, and this step code is used as a unit of pipeline processing after the A stage 37. Note that the number of step codes is unique to each instruction, and when the multistage indirect mode is not designated, one instruction is divided into a minimum of one step code and a maximum of three step codes. Also, if there is a multi-stage indirect mode designation, the step code increases accordingly.

Further, all step codes existing on the pipeline may be for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that caused the step code. The program counter value that is attached to the step code and flows through each stage of the pipeline is called a step program counter (SPC), and the step program counter (SPC) is passed through the pipeline stages one after another.

The input / output step codes of each pipeline stage are named for convenience as shown in FIG. Also, the step code performs processing related to the operation code,
There are two series of series, which are the entry address of the micro ROM section 5 and parameters for the E stage 39, and the series which is the operand for the micro instruction of the E stage 39.

The instruction fetch stage 35 fetches an instruction from a memory or a branch buffer, inputs it to the instruction queue 2b, and outputs an instruction code to the D stage 36. Input to the instruction queue 2b is performed in aligned 4-byte units. Fetching instructions from memory requires a minimum of 2 clocks for every 4 bytes aligned. When the branch buffer is hit, it is possible to fetch the aligned 4 bytes in 1 clock.

The output unit of the instruction queue 2b is variable every 2 bytes,
Up to 6 bytes can be output in 2 clocks. Also,
Immediately after branching, the instruction queue 2b is bypassed so that 2 bytes of the basic instruction part can be directly transferred to the instruction decoder.

Controls such as registering and clearing instructions in the branch buffer,
The IF stage 35 also manages the prefetch destination instruction address and controls the instruction queue.

The EIT processing detected by the IF stage 35 includes a bus access exception when fetching an instruction from the memory and an address translation exception due to a memory protection violation.

The instruction decode stage 36 decodes the instruction code input from the IF stage 35. Decoding is performed once every two clocks using the FHW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit 2, and one decoding process consumes an instruction code of 0 to 6 bytes (RET instruction The instruction code is not consumed in the output processing of the step code including the return address such as). About 35 bit control code which is A code 43 which is address calculation information and maximum 32 bit address modification information for A stage 37 and D code 42 which is intermediate decoding result of operation code. 50-bit control code and 8-bit literal information in A stage 37
Output to.

In the D stage 36, control of the PC calculator of each instruction, branch prediction processing, pre-branch processing for pre-branch instructions, and instruction code output processing from the instruction queue are also performed. Further, the EIT processing detected in the D stage 36 includes a reserved instruction exception and an odd address jump trap during pre-branch. In addition, various EITs transferred from the IF stage 35
The process is the process of encoding in the step code A
Transfer to stage 37.

In A stage 37, the processing is roughly divided into two,
One is a subsequent decoding process of the operation code by using the decoder of the instruction code unit 2, and the other is a process of calculating an operand address by the operand address calculation unit 4.

In the subsequent decoding process of the operation code, the D code 42 is input, and the R code 44 including the write reservation of the register and the memory and the entry address of the microprogram and parameters for the microprogram is output. The write reservation of the register and the memory is for preventing the contents of the register and the memory referred to in the address calculation from being rewritten by the preceding instruction on the pipeline and erroneous address calculation being performed. In order to avoid deadlock, write reservation of registers and memory is performed not for each step code but for each instruction. Details of the register and memory write reservations are described in Japanese Patent Application No. 62-144394 and the description thereof is omitted.

In the operand address calculation processing, the A code 43 is input, the operand address calculation unit 4 performs address calculation by combining addition and memory indirect reference according to the A code 43, and the calculation result is output as an F code 45. At this time, a conflict check is performed at the time of reading the register or the memory associated with the address calculation, and if the conflict is instructed because the preceding instruction does not finish the register or memory writing process, the preceding instruction finishes the writing process at the E stage 39. Wait until you do.

It also checks whether the operand address or memory indirect reference address falls within the I / O area mapped in memory.

The EIT processing detected at the A stage 37 includes a reserved instruction exception,
Privileged instruction exception, bus access exception, address translation exception,
There is a debug trap due to an operand breakpoint hit during memory indirect addressing. If the D code 42 and the A code 43 indicate that the EIT processing has occurred, the A stage 37 does not perform the address calculation processing on the code, and transmits the EIT processing to the R code 44 and the F code 45. .

The processing of the F stage 38 is also roughly divided into two, and one is composed of an R stage 40 for executing a micro ROM access processing and an OF stage 41 for performing an operand prefetch processing. The R stage 40 and the OF stage 41 are not always required. They do not operate simultaneously, but operate independently depending on whether memory access rights can be acquired.

In the R stage 40, a micro ROM access process, that is, a micro ROM access and a micro instruction decoding process for producing an E code 46, which is an execution control code used for execution in the next E stage 39, is performed on the R code 44. . When the processing for one R code 44 is decomposed into two or more microprogram steps, the micro ROM is used in the E stage 39, and the next R code 44 waits for the micro ROM access. The micro ROM access to the R code 44 is performed at the last micro instruction execution in the E stage 39 before that. Further, in the data processor of this embodiment, most of the basic instructions are executed in one microprogram step, so in practice, micro ROM access to the R code 44 is often performed one after another.

When there is no EIT processing newly detected in the R stage 40 and the R code 44 indicates an instruction processing re-execution type EIT, the microprogram for the EIT processing is executed.

When R-code 44 indicates an odd address jump trap, R-stage 40 conveys it to E-code 46. This is for a pre-branch. In the E stage 39, if no branch occurs in the E code 46, the pre-branch is validated and an odd address jump trap is generated.

In the OF stage 41, the operand fetch process of the two processes performed in the F stage 38 is performed.

For the operand fetch, the F code 45 is input, and the fetched operand and address are output as S code 47. One F code 45 may cross word boundaries, but specifies an operand fetch of 4 bytes or less. F
The code 45 also includes a designation as to whether or not to access the operand. When transferring the operand address itself or the immediate value calculated in the A stage 37 to the E stage 39, the operand prefetch is not performed and the F code 45 Is transmitted as S code 47.

When the operand to be prefetched and the operand to be written by the E stage 39 match, the operand prefetch is not performed from the memory but bypassed.

Also, the operand prefetch is delayed for the I / O area, and the operand fetch is performed after waiting for the completion of all the preceding instructions.

The EIT processing detected in the OF stage 41 includes a debug trap due to a breakpoint hit for a by-access exception, an address translation exception, and an operand prefetch. When the F code 45 indicates an EIT process other than a debug trap, it is transferred as an S code 47 and operand prefetch is not performed. When F code 45 indicates a debug trap, EI is issued for that F code 45.
The same processing as when T processing is not shown,
The debug trap is transmitted to the E stage 39 as S code 47.

In the execution stage 39, the E code 46 and the S code 47 operate as inputs to become the stage for executing instructions, and the F stage
All the processing performed in each stage before 38 functions as a pre-processing stage for E stage 39.

If a jump instruction is executed in E stage 39 or EIT processing is started, IF stage 35 to F stage
All processes up to 38 are invalidated. Controlled by the microprogram, the E stage 39 executes an instruction by executing a series of microprograms from the entry address of the microprogram indicated by the R code 44.

The reading of the micro ROM and the execution of the micro instructions are pipelined. Therefore, when a branch occurs in the microprogram, there is a space of 1 microstep. Further, the E stage 39 can use the store buffer in the data operation unit 6 to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage 39, the write reservation for the register and the memory made in the A stage 37 is canceled after writing the operand.

When the conditional branch instruction causes a branch at the E stage 39, the branch history for the conditional branch instruction is rewritten because the branch prediction for the conditional branch instruction was incorrect.

The EIT detected in the E stage 39 includes a bus access exception, an address translation exception, a debug trap, an odd address jump trap, a reserved function exception, an invalid operand exception, a reserved stack format exception, a divide by zero trap, an unconditional trap, and a conditional trap. , Delayed context trap, external interrupt, delayed interrupt, reset interrupt,
There is a system failure.

All EITs detected in E stage 39 are processed by EIT, but detected between IF stage 35 to F stage 38 before E stage 39 and reflected in R code 44 and S code 47.
EIT is not always processed by EIT. IF stage 35
All EITs that have been detected during the ~ F stage 38 but have not reached the E stage 39 due to the preceding instruction executing a jump instruction in the E stage 39, etc. are cancelled. The instruction that caused the EIT was not executed in the first place.

External interrupts and delayed interrupts are at the E stage due to instruction breaks.
It is directly accepted at 39, and the required processing is executed by the microprogram. Other various EITs are also processed by microprograms.

Each stage of the pipeline has an input latch and an output latch, and is basically operated independently of the other stages. When each stage completes the previous process, transfers the result of the process from the output latch to the input latch of the next stage, and when all the input signals necessary for the next process are available in the input latch of the own stage, In each stage, the input signal for the next process output from the previous stage becomes valid and each stage transfers the current process result to the input latch of the subsequent stage. And the output latch becomes empty, the next processing is started.

It is necessary that all input signals be completed at the clock timing one clock before the operation of each stage. If the input signals are not complete, the stage enters the waiting state (waiting for input). When performing a transfer from the output latch to the input latch of the next stage, the input latch of the next stage must be empty, and if the input latch of the next stage is not empty, the pipeline stage Waiting state (waiting for output). If the necessary memory access right cannot be acquired, a wait is inserted in the memory access being processed, or other pipeline conflict occurs, the processing itself of each stage is delayed.

Next, the operation of the PC calculator 3 for a branch instruction will be described.

When the instruction code is decoded in the D stage 36, the PC calculation unit 3 determines whether the instruction code is decoded from the length information of the instruction code that was decoded immediately before and the start address of the instruction code that was decoded immediately before that. Calculate the start address of the instruction code.
The PC calculator 3 holds the PC value of the instruction, which is the address of the instruction break, in the DPC latch 3e, and manages the address of the step code break in the TPC latch 3d. The DPC latch 3e is rewritten only when the break address of the instruction is calculated. The TPC latch 3d is rewritten at the address of the break of the step code, that is, every time the instruction decoding process is performed. Since the PC value of the step code processed in the pipeline needs the PC value of the instruction that caused the step code, the value of the DPC latch 3e shown in FIG. 2 is the APC latch 3f, FPC.
The data is sequentially transferred to the latch 3g and the CPC latch 3h.

As described above, the instruction decoding process is executed in units of step code, and 0 to 6 can be performed in one decoding process.
Bytes of opcode are consumed. The length of the instruction code used at that time, which is found for each instruction decoding process, is output to the instruction length bus 11 of the instruction decoder 2a.

If not pre-branched, the D stage 36 decodes the next succeeding instruction and, at the same time, calculates the PC value of the succeeding next instruction in the PC calculation unit 3, so that the value of the TPC latch 3d and the instruction length bus 11 are transferred. The added result is added to the length of the instruction code consumed by the decoding, and the addition result is written back to the TPC latch 3d. That is, the start address of a step code is calculated when the step code is generated by the decoding process.

Except for the pre-branch, the instruction codes to be decoded are output one after another from the instruction queue 2b, so it is not necessary to know the start address of the code at the decoding start stage. When the step code generated in the D stage 36 is the last step code of the instruction A, the output of the PC adder 3b calculated during the decoding process of the next instruction B is the start address of the instruction B and the instruction B The PC value of the instruction B, which is the output of the PC adder 3b, is from the PO bus 15 to the TPC latch 3d and the DPC latch.
Written on both 3e. Furthermore, at this time, A stage 37
Is waiting for the input code, and if the APC latch 3f is urgently needed, the PC value of the instruction B is also written from the PO bus 15 to the APC latch 3f.

When pre-branching, the D stage 36 outputs the last step code of the pre-branch instruction, and then the instruction decoder
Since the processing of 2a is stopped and the PC value of the branch destination instruction is calculated, DP
The value of the C latch 3e and the branch displacement transferred from the DISP bus 10 are added.

Further, the initialization instruction is issued to the IF stage 35, the PC value of the branch instruction as the addition result is written to the TPC latch 3d and the DPC latch 3e, and also output to the CA bus 14 to output the counter QINPC, CA.
Also write to A-latch 7e.

An odd address jump trap is also detected when the branch target instruction address is calculated by the pre-branch, and the result is shown as a parameter in the D code 42. In the E stage 39, when the pre-branch is found to be correct, the odd address jump trap is activated. If the pre-branch is wrong and a branch occurs again in the E stage 39, the odd address jump trap detected in the pre-branch is ignored. Therefore, the odd address jump trap detected in the D stage 36 is treated differently from other EITs. Further, in the E step 39, the value of the odd instruction address is required for the mobile processing of the odd address jump trap. Therefore, when the D stage 36 detects an odd address jump trap, it generates a special step code (OAJT step code) with the odd address value as the PC value. In response to the OAJT step code, the A stage 37 and F stage 38 transmit the code to the next stage. When the E stage 39 determines that the pre-branch is correct and the pre-branch detects an odd address jump trap, it uses the PC value of the OAJT step code transferred next through the CPC latch 3h to detect the odd address. Performs jump trap startup processing.

When a branch occurs at E stage 39, the branch destination address is EB
It is transferred from the latch 6 to the TPC latch 3d via the CA bus 14. The PC calculation unit 3 adds this value and zero and outputs the result to PO.
Write from the bus 15 to the TPC latch 3d and DPC latch 3e. This completes the initialization of the PC calculation unit 3. This initialization processing is performed by overlapping with the first unit decoding in which the branch occurs in the E stage 39. The same value is set in the counter QINPC and CAA latch 7e when the value is taken into the TPC latch 3d from the A bus 13.

When the D stage 36 does not perform the pre-branch processing for the pre-branch instruction, the operand address calculation unit 4 calculates the branch destination address of the pre-branch instruction. The branch destination address is calculated by the AP transferred from the A bus 13.
This is performed by adding the value of the C latch 3f and the branch displacement value transferred from the DISP bus 10 by the address adder 4d. The calculated branch destination address is transmitted to the E stage 39. When calculating the branch destination address using the operand address calculation unit 4 in the A stage 37, the odd address jump trap is not detected. Since the branch destination address transferred to the E stage 39 is odd, the information of the odd address jump trap is transmitted.

If D stage 36 performs pre-branch processing, BCC instruction,
For the ACB instruction, the A stage 37 calculates the PC value of the next instruction at the address following the pre-branch instruction. The calculation result is transmitted to the E stage 39 and used as a branch destination address again when the pre-branch is wrong. For an instruction such as a BCC instruction that is decoded into a one-step code in the D stage 36, the value of the APC latch 3f transferred from the A bus 13 is set to the instruction length of the BCC instruction transferred from the correction value bus 12. Add and add the result to AO bus 1
Write to FA latch 7b from 6.

〔The invention's effect〕

As described above, according to the present invention, the holding means for holding the occurrence information indicating the occurrence of the second branch processing, and the branch prediction result in the first pipeline processing stage immediately after the occurrence of the second branch processing are held. Since the branch prediction control means for making non-branch based on the occurrence information held in the means is provided, the branch prediction processing by the instruction decoded immediately after the branch in the instruction execution stage can be predicted as "no branch", which is ambiguous. This has an excellent effect of preventing a decrease in data processing efficiency due to the prediction processing.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the configuration of a data processing apparatus showing an embodiment of the present invention, FIG. 2 is a detailed block diagram for explaining the configuration of the data processing apparatus shown in FIG. 1, and FIG. 2 is a detailed block diagram for explaining the structure of the branch prediction table shown in FIG. 2, FIG. 4 is a block diagram for explaining the pipeline processing operation according to the present invention, and FIG. 5 is a pipeline processing structure for a conventional data processor. FIG. 6 is a schematic diagram for explaining the instruction execution cycle of each stage related to branch instruction processing. In the figure, 1 is an instruction fetch unit, 2 is an instruction decode unit, 3 is a PC calculation unit, 4 is an operand address calculation unit, 5
Is a micro ROM unit, 6 is a data operation unit, 7 is an external bus interface unit, 8 is an address output circuit, and 9 is a data input / output circuit. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first prediction function comprising: a decoding mechanism for decoding an instruction; and a branch prediction mechanism for executing a branch prediction process for predicting branching or non-branching of a conditional branch instruction. A first pipeline processing stage that performs branch processing, transfers the instruction decoding and the result of the first branch processing as a unit processing code to a subsequent pipeline processing stage, and the first pipeline processing stage. In a data processing device having a second branch processing based on a unit processing code and a second pipeline processing stage for executing a decoded instruction, holding means for holding occurrence information indicating occurrence of the second branch processing. And the branch prediction result in the first pipeline processing stage immediately after the occurrence of the second branch processing. The data processing apparatus being characterized in that includes a branch prediction unit for a non-branch based on the occurrence information held in the holding means.