JPH0769814B2 - Data processing device with pipeline processing mechanism - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device that realizes high processing capability by an advanced pipeline processing mechanism,
In particular, the present invention also relates to a data processing device capable of performing a preceding branch process to a return destination address in the early stage of pipeline processing even for a subroutine return instruction.

[Conventional technology]

FIG. 8 is a diagram showing a typical pipeline stage of a conventional data processing apparatus. In the figure, (1) is an instruction fetch stage, (2) is an instruction decode stage,
(3) is an address calculation stage, (4) is an operand fetch stage, (5) is an execution stage, and (8) is an operand write stage.

Next, the operation will be described. The data processing device shown in FIG. 8 uses an idle time of the bus to fetch the instruction data, an instruction fetch stage (1), an instruction decode stage (2) for analyzing the instruction data, an operand, etc. Of the address calculation stage (3) for performing address calculation of the operand, the operand fetch stage (4) for fetching operand data, the execution stage (5) for processing data, and the operand write stage (8) for writing operand data. It is composed of 6 pipeline stages, and each stage can simultaneously process different instructions. However, if a conflict occurs with respect to operands or memory access, the process with a low priority is suspended until the conflict is resolved.

As described above, in the pipelined data processing device, the process is divided into a plurality of stages according to the flow of data processing, and each stage is operated at the same time,
The average processing time required for one instruction is shortened to improve the overall performance.

However, in such a pipelined data processing device, when an instruction that disturbs the flow of instructions such as a branch instruction is executed in the execution stage (5), the processing performed in the previous stage is executed. Are all canceled,
The next instruction to be executed must come from the instruction's fetch. In this way, when an instruction that disturbs the processing flow is executed, the pipeline processing overhead increases,
The execution speed of the data processor does not increase. In order to improve the performance of the data processing device, various measures have been made to reduce the overhead related to instruction execution such as unconditional branch instructions and conditional branch instructions. For example, a branch target buffer that stores the address of the branch instruction and the address of the branch destination as a pair is used to predict the flow of the instruction at the instruction fetch stage and perform the processing. (JKFLe
e and AJSmith, “Branch Prediction Strategies and
Branch Target Buffer Design, "IEEE COMPUTER Vol.1
7, No. 1, January 1984, pp. 6-22.) As described above, the flow of processing is predicted at the early stage of pipeline processing, and the pipeline is predicted to be executed next. (Hereinafter referred to as the preceding branch processing) to reduce the overhead at the time of executing the branch instruction. However, regarding the return instruction from the subroutine, it is difficult to predict the flow of processing because the return address from the subroutine depends on the address of the corresponding subroutine call instruction.

[Problems to be Solved by the Invention]

As described above, in the conventional data processing device, since the return address from the subroutine depends on the address of the corresponding subroutine call instruction with respect to the return instruction from the subroutine, an effective means for predicting the processing flow is provided. Nakatsuta.

The present invention has been made in order to solve the above problems, and it is possible to obtain a data processing device capable of performing a pre-branch processing to a return destination address even in the case of a subroutine return instruction at an early stage of pipeline processing. With the goal.

[Means for Solving the Problems]

The data processor according to the present invention comprises a stack memory (hereinafter referred to as a PC stack) dedicated to a program counter (PC) that stores only the return address of a subroutine call instruction.

[Action]

In the data processor according to the present invention, the return address from the subroutine is pushed to the PC stack when the subroutine call instruction is executed at the execution stage, and the PC when the subroutine return instruction is decoded at the instruction decode stage.
Preceding branch processing is performed on the address popped from the stack.

〔Example〕

(1) Pipeline Mechanism The pipeline processing of the data processing apparatus of the present invention has the configuration shown in FIG. An instruction fetch stage (IF stage (1)) for prefetching instructions, a decode stage (D stage (2)) for decoding the first instruction,
An operand address calculation stage (A stage (3)) for decoding the second-stage instruction and operand address calculation, a micro ROM access (especially referred to as R stage (6)), and an operand pre-fetch (especially OF stage (7)) )) Is performed and an execution stage (E stage (5)) for executing an instruction is performed as a basic five-stage pipeline process. In the E stage (5), there is a one-stage store buffer, and in addition, some high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and theoretically five stages operate completely independently. Each stage is 1
A minimum of 2 clocks can be processed. Therefore, ideally, pipeline processing proceeds one after another every two clocks.

The data processing device of the present invention has instructions that cannot be processed by only one basic pipeline process, such as memory-memory operation and memory indirect addressing. It is designed for balanced pipeline processing as much as possible. For an instruction having a plurality of memory operands, the pipeline processing is performed by decomposing into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands. The method of disassembling the pipeline processing unit is described in detail in Japanese Patent Application No. 61-236456.

The information passed from the IF stage (1) to the D stage (2) is the instruction code (11) itself. D stage (2)
The information passed from A to A stage (3) is related to the operation specified by the instruction (called D code (12)) and the information related to operand address calculation (A code (13)).
There are two). The information passed from the A stage (3) to the F stage (4) is an R code (14) including an entry address of a microprogram routine and a parameter to the microprogram, and an F code including an operand address and access method instruction information. It is two with the code (15). Information passed from the F stage (4) to the E stage (5) is an E code (16) including operation control information and a literal and an S code (17) including operands and operand addresses.

(1.1) Processing of each pipeline stage (1.1.1) Instruction fetch stage The instruction fetch stage (IF stage (1)) fetches an instruction from the external memory and inputs it to the instruction queue, and then the D stage (2). The instruction code (11) is output to.

Input the instruction queue in aligned 4-byte units. Fetching instructions from memory requires a minimum of 2 clocks for every 4 bytes aligned.

The output unit of the instruction queue is variable every 2 bytes.
Up to 6 bytes can be output during the clock. Immediately after branching, it is possible to bypass the instruction queue and transfer the two bytes of the basic instruction portion directly to the instruction decoder.

IF stage (1) for managing prefetch destination instruction address
Done in. The address of the instruction to be fetched next is calculated by a dedicated counter as the address of the instruction to be input to the instruction queue. When a branch or jump occurs, the address of the new instruction is transferred from the PC arithmetic unit or data arithmetic unit.

(1.1.2) Instruction Decode Stage The instruction decode stage (D stage (2)) decodes the instruction code (11) input from the IF stage (1). The instruction code is in units of 16 bits (halfword). Decoding is performed once for every two clocks, and 0 to 3 half-word instruction codes are consumed by one decoding process. At the D stage (2), the instruction code is decomposed into a step code which is a pipeline processing unit. That is, one instruction is decomposed into one or a plurality of step codes and processed in the subsequent pipeline stage. In the D stage (2), an A code (13) which is address calculation information for the A stage (3) as a step code and a D which is an intermediate decoding result of the operation code.
The code (12) and is output.

In the D stage (2), control of the PC arithmetic unit, branch prediction processing,
Pre-branch processing (pre-branch) for a pre-branch instruction and instruction code output control from the instruction queue are also performed.
Pre-branch processing means predicting branches such as unconditional branch instructions and conditional branch instructions prior to branch processing at the E stage (5), calculating the address of the jump destination in the PC arithmetic unit, and the IF stage (1) To jump to the destination instruction, and to flow the destination instruction to the pipeline. The pre-branch instruction is an instruction for performing pre-branch processing.

(1.1.3) Operand address calculation stage Operand address calculation stage (A stage (3))
Is roughly divided into two processes. One is the process of performing the subsequent decoding of the opcode, and the other is the process of calculating the address of the operand.

The subsequent decoding process of the operation code receives the D code (12) as input, and outputs the R code (14) including the write reservation of the register and the memory and the entry address of the microprogram and parameters for the microprogram. Note that the register or memory write reservation is for preventing the contents of the register or memory referred to in the address calculation from being rewritten by a preceding instruction on the pipeline and causing incorrect address calculation. In order to avoid deadlock, write reservation of registers and memory is performed not for each step code but for each instruction. The write reservation of registers and memory is described in detail in Japanese Patent Application No. 62-144394.

In the operand address calculation process, an A code (13) is input, an address calculation is performed according to the A code (13) by combining addition and memory indirect reference, and the calculation result is output as an F code (15). At this time, a conflict check is performed at the time of reading the register or memory associated with the address calculation, and if the conflict is instructed because the preceding instruction has not completed the writing process to the register or memory, the preceding instruction is written at the E stage (5). Wait until the process is completed.

In the A stage (3), in order to prevent a stack pointer (SP) conflict due to a push operation from the stack, a push operation to the stack, etc., the A stage stack pointer (SP) precedes the SP of the execution stage (5). AS
P) is provided, and the ASP update associated with the pop and push operation is performed at this stage. Therefore, a normal pop,
By referring to the ASP even immediately after the push operation, the processing can be advanced without delaying the step code processing due to the SP conflict. The method of managing the SP is described in detail in Japanese Patent Application No. 62-145852.

(1.1.4) Micro ROM access stage The operand fetch stage (F stage (4)) is also roughly divided into two processes. One is a micro ROM access process, which is particularly called an R stage (6). The other is an operand prefetch process, which is particularly called an OF stage (7). The R stage (6) and the OF stage (7) do not always operate at the same time, but operate independently depending on whether or not a memory access right can be acquired.

In the R stage (6), the next E for the R code (14)
Micro ROM access and microinstruction decoding processing for producing an E code (16) which is an execution control code used for execution in the stage (5) are performed. When the processing for one R code is decomposed into two or more microprogram steps, the micro ROM is used in the E stage (5) and the next R code (14) is the micro ROM.
Waiting for access. Micro for R code (14)
ROM access is performed before the E stage (5)
It is the time of the last microinstruction execution in. In the data processor of the present invention, most of the basic instructions are executed by one microprogram step, so in practice, micro ROM access to the R code (14) is often performed one after another.

(1.1.5) Operand fetch stage Operand fetch stage (OF stage (7)) is F
Operand prefetch processing is performed out of the above two processing performed in stage (4).

Operand prefetch input F code (15),
Fetch the operand and its address in S code (1
Output as 7). One F code (15) may cross word boundaries, but specifies an operand feature of 4 bytes or less. The F code (15) also includes a designation as to whether or not to access the operand. When transferring the operand address itself or the immediate value calculated in the A stage (3) to the E stage (5), the operand prefetch is performed. The contents of the F code (15) are transferred as the S code (17) without performing the stitching. When the operand to be prefetched and the operand to be written by the E stage (5) satisfy the inclusive relation, the memory access is not performed for the operand prefetch, and the value to be written by the E stage (5). Bypass.

(1.1.6) Execution stage The execution stage (E stage (5)) is the E code (16),
The S code (17) is used as an input to perform data processing, data reading, writing, and the like using various arithmetic units. There are ALUs, barrel shifters, priority encoders, counters, shift registers, etc. as computing units. The E stage (5) is controlled by the microprogram and executes an instruction by executing a series of microprograms from the entry address of the microprogram indicated by the R code (16). The registers and the main arithmetic units are connected by 3 buses, and the instruction between the registers is 1
Process micro-instructions in 2 clock cycles.

This E stage (5) is a stage for executing instructions,
All the processes performed in the stages before the F stage (4) are pre-processes for the E stage (5). When a branch occurs at the E stage (5), all the processing from the IF stage (1) to the F stage (4) is invalidated, and the jump destination address is output to the instruction fetch section and the PC calculation section.

In the E stage (5), the store buffer in the data operation unit (56) can be used to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage (5), the write reservation for the register and the memory performed in the A stage (3) is canceled after writing the operand.

When the conditional branch instruction causes a branch at the E stage (5), it indicates that the branch prediction for the conditional branch instruction is incorrect, and the branch history is rewritten.

(1.2) Management of Program Counter All step codes existing on the pipeline of the data processing device of the present invention may be for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that caused the step code. The program counter value attached to the step code and flowing through each stage of the pipeline is called the step program counter (SPC). SPCs are handed over to the pipeline stages one after another.

(2) Preceding Branch Processing of Subroutine Return Instruction In order to suppress the disturbance of the pipeline due to the execution of the subroutine return instruction in the execution stage, the data processing device of the present invention has an instruction decode stage (D stage (D stage ( The preceding branch processing is performed in 2)). The detailed operation will be described below.

FIG. 2 is a block diagram of the data processing apparatus of the present invention, in which only the parts necessary for explaining the processing of the subroutine call instruction and the subroutine return instruction are extracted and described. In the figure, (21) is the instruction queue,
(22) is an instruction decoding unit, (23) is a data input / output circuit for exchanging data with the outside, (24) is an address output circuit for outputting an address to the outside, and (25) is an address for performing an instruction fetch. Counter (QINPC) for
(26) is an instruction decoding unit (2
Latch (IL) that stores the instruction length processed in 2), (2
7) is a latch (PD) for storing displacements to the PC for pre-branching, (30) is a PC adder for performing addition in the PC arithmetic unit (54), (28), (29), (31) are input / output latches (PA, PB, PO) of the PC adder (30), (3
2) is a register (TPC) for storing the temporary PC for each step code processing, (33) is a D stage PC (DPC) for storing the PC of the instruction currently being decoded, (3
4) is an A-stage PC (APC) for storing the PC corresponding to the step code under address calculation, (38) is an address adder for performing ternary addition for address calculation, and (3
5), (36), (37) and (39) are the input / output latches (AI, AD, AB, AO) of the address adder (38), and (40) is A.
Increment and decrement on stage (3)
A stage stack pointer (ASP) that manages SP,
(41) is an F code address register (FA) for storing an address as an F code (15), (42) is an S code address register for storing an address as an S code (17), (43) Is a CA address register (CA
A) and (44) are address registers (AA) managed by the E stage (5), and (45) is an E stage branch address register (EB) for storing the branch destination address in the E stage (5). , (46) is a PC stack that stores only the return address at the time of subroutine call, (47) is a register file including stack pointer, frame pointer, working register, etc. (50) is an ALU for data operation , (48), (49) and (51) are input / output latches (DA, DB, DO) of the ALU (50), and (52) is an S code data register for storing data as an S code (17). (S
D) and (53) are data registers (DD) that store data related to memory access performed in the E stage (5), and (101) to (110) are internal for internally transferring data and addresses. It is a bus (S1 bus, S2 bus, DO bus, A bus, AO bus, DISP bus, PO bus, CA bus, AA bus, DD bus). Reference numeral (54) is a PC calculation unit, and (55) is an address calculation unit.

FIG. 3 is a block diagram of a portion particularly related to the preceding branch processing of the subroutine return instruction in the data processing device of the present invention. In the figure, (61) is a D stage control unit, (62) is an IF stage control unit, (63) is an E stage control unit, and (65) is 3 for counting the number of subroutine call instructions during pipeline processing. The BSR counter, which is a bit counter, (66) is a 3-bit PC stack pointer (DP) (6) managed by the D stage (2).
7) is a 3-bit PC stack pointer (EP) managed by the E stage (5), (68), (69) is DP respectively.
Decoder for decoding (66), EP (67), AN for (70)
D gate, (71) is the effective bit control signal latch,
(201) to (214) are control signals for each unit. In this figure, the clock signal for controlling the timing is omitted for simplicity.

FIG. 4 is a diagram showing the configuration of the PC stack (46). In the figure, (46A) is the return address field that stores the return address, and (46B) is the return destination stored in each entry. This is a valid bit indicating whether the address is valid or invalid.

In this embodiment, the PC stack (46) is composed of 8 entries. Also, since the instruction code is in units of 16 bits, there is no odd address for the PC, and the return address field is 31 bits. If the return address is read from the PC stack (46),
The lowest bit is output as '0'. DP (66), EP (6
Although 7) is 3 bits, the carry from the highest bit when incrementing, and the borrow to the highest bit when decrementing are ignored. That is, the PC stack (46) is handled as a ring-shaped stack memory in which the entries indicated by the pointer "000" and the pointer "111" are adjacent to each other.

(2.1) Outline of operation of PC stack In the data processing device of the present invention, there are a branch subroutine (BSR) instruction and a jump subroutine (JSR) instruction as the subroutine call instruction. Also, as a subroutine return instruction, a return subroutine (RTS)
As an instruction and a high-function instruction, there is a high-level language subroutine return and an EXITD instruction that releases parameters at once.

When the subroutine call instruction is executed, the return address from the subroutine is pushed to the PC stack (46) at the E stage (5). When the subroutine return instruction is decoded, the preceding branch processing (pre-return) is performed on the address in the stack of the PC stack (46) in the D stage (2). In the E stage (5), it is checked whether or not the pre-return processing in the D stage (2) is correct, and if the address for which the pre-return is made is wrong, the branch to the true return destination address is made. Perform processing.

It will be described in detail below including the updating of the pointers DP (66) and EP (66). However, the effective bit control signal latch (7
The value of 1) shall be '1'.

In the reset state, the PC stack (46) initialization signal (INIT signal (208)) causes the BSR counter (65), EP
(67) is cleared to zero, and the value of EP (67) which is zero is copied to DP (66). Also, the PC stack (4
All valid bits (6B) in 6) are cleared to '0'.

First, the instruction code (11) fetched from the instruction queue (21) is decoded by the instruction decoding section (22). When the fetched instruction is a subroutine call instruction, the DPDEC signal (202) decrements the DP and the BSR counter (65) counts up. In the address calculation stage (3), the return address is calculated by the address adder (38) and transferred to the FA register (41) via the AO bus (105). At the F stage (4), the value of the FA register (41) is transferred to the SA register (42). When the subroutine call instruction is executed in the E stage (5), EP is issued by the EPDEC signal (206).
The value of (67) is pre-decremented. Then, the EP updated by the PCWRITE signal (210) in the PC stack (46)
The return address field of the entry pointed to by (67) (46
The value of the return address stored in the SA register (42) is written in A) via the S1 bus (101), and the valid bit (46B) of that entry is set to '1'. Also, BSRCD
The EC signal (205) decrements the BSR counter (65). With the BSR instruction, branch processing to the start address of the subroutine is performed in the D stage (2), so the E stage (5)
There is no need to perform branch processing with.

Next, the processing of the subroutine return instruction will be described. When the instruction fetched from the instruction queue (21) is a subroutine return instruction, the BSR counter (65)
The BSRCZ signal (201) is checked to see if the value of is zero. If the BSR counter (65) is not zero, the D stage (2) suspends processing until the value of the BSR counter (65) becomes zero. BSR counter (65)
Is not zero, it means that the corresponding subroutine call instruction is not executed yet in the E stage (5) and is in the pipeline, and the return address corresponding to the PC stack (46) is not registered. It is shown that.
When the BSRCZ signal (201) indicates that the value of the BSR counter (65) is zero or has reached zero,
The D stage controller (61) receives the I signal by the PRERET signal (209).
Notify the F stage control unit (62) and the PC stack (46) that pre-return processing will be performed. PC stack (46)
Outputs the content of the return address field (46A) of the entry pointed to by DP (66) to the CA bus (108). The IF stage controller (62) invalidates all the instruction data fetched by the instruction queue (21), fetches the instruction at the return address with the value output to the CA bus, and fetches the fetched instruction data. It is sent to the instruction decoding unit (22). After the contents of the PC stack (46) are output to the CA bus (108), the DP (66) is post-incremented by the DPINC signal (203). The contents of the valid bit (46B) of the entry pointed to by the EP (67) in the PC stack (46) by the VREAD signal (211) are sent to the E stage control section (63) as a VALID signal (214). The valid bit (46B) of the read entry is cleared to "0". In the E stage control unit (63), if the VALID signal (214) is "1", it indicates that the pre-return is correct, and the execution of the subroutine return instruction is ended. if
When the VALID signal (214) is "0", it indicates that the return address for which pre-return was performed is incorrect. At this time, the value of the true return address is
Captured in register (53) and EB via S1 bus (101)
After transferring to register (45), the value of EB register (45)
Output to CA bus (108). The IF stage (1) performs instruction fetch according to the value output to the CA bus (108).

The valid bit (46B) in the PC stack (46) is set to '1' when the return address at the time of subroutine call is registered, and the valid bit (46B) at the subroutine return.
It is cleared to '0' after B) is read. That is, the correct return address is registered in the entry with the valid bit (46B) of '1' in the PC stack.

E stage (5) when the subroutine return instruction is executed
Then, a check is made as to whether or not the return address that was pre-returned in the D stage (2) was correct. This is because the PC stack (46) consists of 8 entries, so if subroutine calls are nested at 9 levels or higher, the return address data for subroutine calls at levels higher than 8 will be overwritten. It will be destroyed. In case of such a case,
In the E stage (5), a check is made as to whether or not the pre-return has been executed correctly. When the PC stack (46) is read (subroutine return) from the deepest point for 8 levels or more, the PC stack (46)
All of the valid bits (46B) are "0", indicating that a valid return address is not stored. But,
From the deepest level of the subroutine level, the correct value is always PC for 8th level subroutine calls.
Stored in the stack (46), the probability of pre-return being correct is very high.

The BSR counter (65) described above is a B that performs pre-branch.
It is provided for accurate pre-return even immediately after the SR instruction and for reliable comparison at the E stage (5).
Without this function, the BSR instruction is being processed and the processing at the D stage (2) has ended, but at the E stage (5) the value of the return address has not yet been written to the PC stack (46). If the subroutine return instruction is executed in the D stage (2), the return address of the corresponding subroutine return instruction is not registered, and the pre-return processing is performed at the incorrect return destination address. However, when the subroutine return instruction is processed in the E stage (5), the preceding BSR instruction has already been processed and the correct return address is registered in the PC stack (46). Stage (5)
When the valid bit (46B) is referred to, the VALID signal (214) shows '1' (valid), and the pre-return is processed as if it was correct. That is, in such a case, a malfunction will occur. By providing the function of the BSR counter, the value of the return destination address to be referenced precedes
After registering with the BSR instruction, a pre-return is performed. In addition, when executing the BSR instruction, P at the D stage (2)
Since the PC stack (46) is not rewritten after the C stack (46) is referenced until it is processed in the E stage (5), the PC stack (where the return address is read in the D stage (2) is The valid bit (46B) corresponding to the entry in 46) is correctly referenced in the E stage (5).

In the JSR instruction that does not perform pre-branching, branch processing to the branch destination address is performed in the E stage (5), so if the RTS instruction is registered in the JSR instruction, refer to the PC stack (46). Even if you pre-return, that RTS
This does not happen because the pipeline is canceled before the instruction itself is executed. The same applies when the pre-branch processing is not performed for the BSR instruction.

As described above, by providing the PC stack (46) that stores only the return address at the time of the subroutine call, the subroutine return instruction is pre-returned to the return address at the instruction decoding stage, and the subroutine Eliminates turbulence in the pipeline when executing return instructions.

When a branch occurs in the E stage (5), the value of the BSR counter (65) is cleared to zero by the EBRA signal (204), and the content of EP (67) is copied to DP (66). When a branch occurs at the E stage (5), all the processing at the IF stage (1) to the F stage is invalidated, so that it is decoded at the D stage (2), but at the E stage (5). The update of the BSR counter (65) and DP (66) performed for the subroutine call instruction and the subroutine return instruction that were not executed during processing is invalidated, and the return address of the PC stack (46) to that level is reset. The value can be referred to correctly in the D stage (2).

When the return address value from the subroutine in the external memory is rewritten by the program, the return address stored in the PC stack (46) is different from the return address in the external memory. Therefore, the operation is not guaranteed. Therefore. When performing pre-return processing, rewriting the value of the return address on the external memory by the program is prohibited.

The data processing apparatus of the present invention has means for forcibly invalidating the pre-return processing by a program.
This processing is performed by rewriting the contents of the valid bit control signal latch (VCNT latch (71)) in the control register by the program. If the VCNT latch (71) is set to '1', the VALID signal (2
14) is sent to the E stage control section (63), reflecting the value of the effective bit (46B) in the PC stack (46). VCNT
If the latch (71) is set to '0', the VCNT signal (21
3) becomes '0' and the valid bit (4) in the PC stack (46)
Whatever the value of 6B), the VALID signal (214) sent from the AND gate (70) to the E stage control unit (63) becomes "0". Therefore, the pre-return processing performed in the D stage (2) is always invalid, the return destination address is read from the external memory in the E stage (5), and the return destination address is returned. Since all the pre-return processing is disabled, the correct operation is guaranteed even if the value of the return address from the subroutine on the external memory is rewritten.

Also, the effective bit control signal latch (VCNT latch (71))
After setting "0" to, to enable pre-return processing again, program the PC in the control register.
Stack (46) initialization signal (INIT signal (208)) to '1'
The PC stack (46) is initialized by resetting. The BSR counter (65) and EP (67) are cleared to zero, and the value of EP (67) that has reached zero is copied to DP (66). In addition, the effective bit (46) in the PC stack (46)
B) are all cleared to '0'. After that, the VCNT latch (71) is set to '1' to enable the pre-return processing again.

(2.2) Detailed Operation of Subroutine Call Instruction and Subroutine Return Instruction Above, the rough operation of the subroutine call instruction and the subroutine return instruction has been described. Here, the detailed operation of each instruction will be described.

In the data processor of the present invention, there are a branch subroutine (BSR) instruction and a jump subroutine (JSR) instruction as the subroutine call instruction. Also, as a subroutine return instruction, a return subroutine (RTS)
As an instruction and a high-function instruction, there is a high-level language subroutine return and an EXITD instruction that releases parameters at once. The bit allocation of each instruction is shown in FIG. "-" Indicates an operation code.

The BSR instruction and the JSR instruction and the RTS instruction and the EXITD instruction have the same processing regarding the PC stack (46).
The TS instruction will be described in detail.

(2.2.1) BSR instruction The BSR instruction is a subroutine call instruction that supports only PC-relative addressing, and the return address is saved in the stack. As shown in FIGS. 5 (A) and (B)
Regarding the BSR instruction, there are two instruction formats, a general type (G format) and a short form (D format).
In the D stage (2), the same process is performed for both formats. This instruction is processed as one step code.

The flow chart for executing the BSR instruction is shown in FIG. When the BSR instruction is processed by the instruction decoding unit (22), a D code (12) indicating the step code of the BSR instruction and an A code (13) for calculating the return address are generated. In the case of the G format command, the value of the displacement (82D) is also captured at the same time according to the field (82B) indicating the size of the displacement. Also, the DPDEC signal (202) decrements the DP (66),
Also, the BSR counter (65) is incremented. This instruction is an instruction to perform pre-branch, the jump destination address is calculated in the PC operation unit (54), the operation result is output to the CA bus, and pre-branch processing is performed. In the A stage (3), the return address is calculated in the address calculation section (55) according to the instruction of the A code (13) and transferred to the FA register (41) via the AO bus (105). In the F stage (14), the value of the FA register (41) is transferred to the SA register (42). In the E stage (5), first, the EP (67) is pre-decremented by the EPDEC signal (206). Next, by the PCWRITE signal (210),
The value of the SA register (42) that stores the return address is set to EP (6) in the PC stack (46) via the S1 bus (101).
The return address field of the entry pointed to by 7) (46A)
The valid bit (46B) of the entry is set to "1". At the same time, the value of the S1 bus (101) is ALU (50) and the value of the DD register (53) via the DO bus (103).
The value of the DD register (53), which has been written to the memory and is stored in the return address, is pushed to the stack on the memory managed by the software by the stack pointer. PC
Return to the stack (46) and register the destination address. BSRCDE
The BRS counter (65) is decremented by the C signal (205). With this instruction, branch processing has already been performed in the D stage (2), so branch processing is not performed in the E stage.

(2.2.2) RTS instruction The RTS instruction is an instruction that returns from a subroutine, and jumps to the return address returned from the stack. This instruction is processed as one step code.

A flow chart for executing the RTS instruction is shown in FIG. When the RTS instruction is processed by the instruction decoding unit (22), a D code (12) indicating the step code of the RTS instruction and an A code (13) for calculating the address of the stap are generated. This instruction is a pre-return instruction. BSRCZ
When the signal (201) indicates that the subroutine call instruction exists in the pipeline, the processing is temporarily stopped until the content of the BSR counter (65) becomes zero. If the BSR counter (65) is zero, pre-return processing is performed. The PRERET signal (209) outputs the contents of the return address field (46A) of the entry pointed to by DP (66) in the PC stack (46) to the CA bus (108), and performs the pre-branch processing (pre-return). . Also, after referring to the PC stack (46), DP (66) by the DPINC signal (203)
Post-increment processing of. Stage A (3)
Then, in accordance with the instruction of the A code (13), the address calculator (55) calculates the address of the staptop,
It is written to the FA register (41) via the AO bus (105). The address of the stamp is the ASP (40) value itself. In the F stage (4), FA register (41)
Is transferred to the SA register (42). At the E stage (5), the valid bit (46B) of the entry pointed to by the EP (67) in the PC stack (46) in which the return address referred to at the time of pre-return is stored by the VREAD signal (211). The contents are sent to the E stage control section (63) as a VALID signal (214), and the valid bit (46
The value of B) is cleared to '0'. At the same time, the value of the SA register (42) indicating the address of the stap is transferred to the AA register (44) via the S1 bus (101). After referring to the PC stack (46), use the EPINC signal (207)
Post increment of EP (67). VALID signal (2
If 14) is '1', it indicates that the pre-return was made to the correct address, and the E stage (5) executes one micro cycle NOP to end the execution of the instruction. V
If the ALID signal (214) is '0', it means that the return address for the pre-return was incorrect, and the value of the return address is used as the fetch address with the value of the AA register (45) as the address. And load it into the DD register (53).
The value of the DD register (53) is transferred to the EB register (45) via the S1 bus (101), and the value of the EB register (45) is output to the CA bus (108) for branch processing. At this time, E
The BRA signal (204) clears the BSR counter (65) and copies the value of EP (67) to DP (66).

(2.3) Description of Other Embodiments In this embodiment, the PC stack (46) is composed of 8 entries. Therefore, when the subroutine calls are nested in nine levels or more, another return address is overwritten on the entry in which a valid return address is stored, and the first value disappears. Therefore,
9 except in the special cases of making recursive calls
If you nest more than the level, you will get a wrong pre-return. Therefore, it is necessary to check whether the pre-return is correct at the E stage. PC
The number of stack entries to be provided may be determined in consideration of the performance problem of how many levels of depth the subroutine call is made and the correct pre-return, and the increased amount of hardware.

In the present embodiment, the BSR counter (65) is provided in order to perform a reliable pre-return. However, if the pre-branch processing of the subroutine call instruction is not performed, the jump destination address is always executed after the subroutine call instruction is executed. This function is not necessary because branch processing is performed and the pipeline is canceled. Also, the pointer DP (66) is decremented when the BSR instruction is decoded in the D stage (2), but BS
When the R instruction is executed at the E stage (5), the value of the decremented pointer EP (67) may be copied.

In addition, in this embodiment, in order to check whether the pre-return was correctly performed at the E stage (5), the PC
The valid bit (46B) of the entry referred to when performing the pre-return from the stack (46) is read, but the valid bit (46B) is performed during the pre-return in the D stage (2).
B) may also be read at the same time and the value of the valid bit may be transferred to the E stage (5). In this case, a check may be performed at the E stage (5) using the transferred valid bit value as in the present embodiment, and the entry address of the microinstruction is changed using this valid bit value. For example, the processing of the micro instruction may be changed in the R stage (4). However, also in this case, the pointer switching process and the valid bit (46B) clearing process are necessary.

Further, in this embodiment, the pre-return processing is always carried out when the subroutine return instruction is processed in the D stage (2), but the effective bit (46B) is also simultaneously executed when the pre-return is carried out in the D stage (2). The pre-return processing may be performed only when the value of the valid bit is read and is "1" (valid).

Further, in this embodiment, after checking whether or not the pre-return was correct in the E stage (5), the correct return address is fetched from the external memory only when it is wrong. The value of the return destination address may be read regardless of the above. For example, if it is an RTS instruction, the value of the return address may be prefetched in the F stage (4).

Further, in this embodiment, the counter is used as a means for detecting whether or not the stage subsequent to the D stage (2) is processing the subroutine call instruction. However, for each step code or each pipeline stage, the subroutine call instruction is used. The flag may be provided and the pre-return processing may be performed only when all the flags are not set.

In this embodiment, the pointer DP (66) managed by the D stage (2) is used as the pointer of the PC stack (46).
And a pointer EP (67) managed by the E stage (5). This is so that the correct return address can be referred to even when a plurality of subroutine return instructions are processed in the pipeline. EP (67) changes corresponding to the subroutine call instruction and the subroutine return instruction executed in the E stage (5). Since DP (66) changes at the instruction decoding stage, even if two or more subroutine return instructions are taken into the pipeline, the return address of the corresponding subroutine call instruction can be referred to. When the branch processing is performed in the E stage (5), the pipeline is canceled, so the value of EP (67) is copied to DP (66). All pointer management of PC stack (46) EP (6
7) only, a flag for the subroutine return instruction is provided, the flag is set when the subroutine return instruction is being executed in the stage A (3) and subsequent stages, and the flag is set when the flag is set. You may make it wait for the return process. In this case, since the PC stack (46) can be referenced after the pointer has been properly switched, correct pre-return can be performed.

Further, the PC stack (46) of the present invention is also accessed at the time of pre-return to determine whether or not the pre-return is correctly performed, and it is efficient to perform it independently of the memory access outside the CPU. Therefore, in a data processing device such as a microprocessor in which the CPU is realized by one integrated circuit chip, if the PC stack (46) is provided in the same integrated circuit as the CPU, the memory access outside the CPU is Independently accessible by PC stack (46).

This invention can be implemented by the embodiments of the following (1) to (4).

(1) An instruction is processed by a pipeline process that has a first stage and a second stage, and for the execution of the instruction, the processing in the first stage precedes the processing in the second stage. A data processing device comprising: a first storage device for storing instructions and data; an address storage unit for storing one or a plurality of address values of a return destination instruction from a subroutine; and an address storage unit for storing data in the address storage unit. A second storage device different from the first storage device, which includes a valid bit storage unit that stores a valid bit indicating whether the value of each return destination address is valid or invalid in combination with the return destination address from the subroutine; , The value that is the return address from the subroutine is the first
First writing means for writing in the storage device, and a value which is a return address from the subroutine is stored in the second writing means.
Writing into the return address storage unit of the storage device of
Writing means, first reading means for reading the first value from the second storage device under the control of the first stage, and a return address from the subroutine when processing the subroutine return instruction. Second reading means for reading the value of 2 from the first storage device, and valid bit writing means for writing a value indicating validity in the valid bit storage part of the second storage device during processing of a subroutine call instruction. Valid bit clearing means for writing a value indicating invalidity to the valid bit storage section of the second storage device during processing of the subroutine return instruction; and valid bit storage section of the second storage device during processing of the subroutine return instruction. Valid bit reading means for reading the stored valid bit; and a command from the first storage device. An instruction fetching means for executing the instruction fetching means for fetching the first instruction from the address indicated by the first value of the first storage device, and the second fetching means of the first storage device. Is provided with a function of fetching the second instruction from the address indicated by the value of, when the valid bit value read by the valid bit reading means is valid during the processing of the subroutine return instruction, the first instruction is executed. A data processing apparatus, which executes the second instruction, when the value of the valid bit read by the valid bit reading means is valid.

(2) The second storage device is the address storage unit 1
1 entry and 1 entry in the valid bit storage section
Each entry consists of 2 ⁿ cyclically numbered entries, at least one of which can be incremented or decremented, and the first n-bit counter for managing the number of the entry and both the increment and decrement. A second n-bit counter for managing the number of the entry, and a third writing means for writing the value of the second n-bit counter to the first n-bit counter. The writing means is means for writing the return address from the subroutine to the entry number indicated by the value of the second n-bit counter in the second storage device, and the first reading means is for the second storage device. The first value is read from the address storage unit of the entry number indicated by the value of the first n-bit counter. The valid bit writing means is a means for writing a valid value in the valid bit storage section of the entry number indicated by the value of the second n-bit counter of the second storage device, 2. The data according to claim 1, wherein the bit clearing means is means for writing a value indicating invalidity into the valid bit storage part of the entry number indicated by the value of the second n-bit counter of the second storage device. Processing equipment.

(3) By the second writing means, the write processing of the address of the return destination instruction from the subroutine to the second storage device is completed for all the subroutine call instructions that have been processed in the first stage. The data processing device according to claim 1 or 2, further comprising a subroutine call instruction processing detecting means for detecting whether or not the data processing apparatus is present.

(4) The first storage device for storing instructions and data differs from the first storage device in that the address storage unit for storing a part or all of the address value of the return destination instruction from the subroutine and the address value are A valid bit storage unit for storing valid bits indicating valid or invalid is stored as one entry grouped as one entry, and a second storage device having 2 ⁿ entries and at least one of increment and decrement are stored. A first n-bit counter that manages the number of the entry, and a second n-bit counter that manages both the increment and decrement and manages the number of the entry; First reading means for reading the address value of the return destination instruction from the entry indicated by the value of the first n-bit counter; First writing means for writing a part or all of the address of the return destination instruction from the subroutine to the address storage section of the entry indicated by the value of the second n-bit counter of the storage apparatus; Valid bit writing means for writing a value indicating valid or invalid in the valid bit storage part of the entry indicated by the value of the second n-bit counter, and stored in the valid bit storage part of the second storage device. Valid bit reading means for reading the value of the valid bit present, second writing means for writing the value of the second n-bit counter to the first n-bit counter, and all entries of the second storage device. A data processing device comprising: a valid bit clearing means for writing a value indicating invalidity into the valid bit storage section.

〔The invention's effect〕

As described above, according to the present invention, by providing the PC stack that stores only the return address of the subroutine call instruction, the branch processing of the subroutine return instruction can be performed prior to the processing at the instruction execution stage. Since the overhead of pipeline processing due to execution of the return instruction is reduced, a high-performance data processing device can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a pipeline processing configuration of a data processing device of the present invention, FIG. 2 is a block diagram of the data processing device of the present invention, and FIG. 3 is a preceding branch of a subroutine return instruction in the data processing device of the present invention. A block diagram of a portion particularly related to processing, FIG. 4 is a diagram showing a configuration of a PC stack (46) of the present invention, and FIG. 5 is a bit allocation of a subroutine call instruction and a subroutine return instruction in the data processing device of the present invention. Figure and Figure 6 show BSR
FIG. 7 is a flow chart of instruction execution, FIG. 7 is a flow chart of RTS instruction execution, and FIG. 8 is a diagram showing a typical pipeline stage of a conventional data processor. (46) is a PC stack that stores only the return address of the subroutine call instruction, (46A) is a PC stack (46) that is the return address field that registers the return address at the time of subroutine call, and (46B) is the PC stack (46B). Four
A valid bit indicating whether the return address stored in each entry in 6) is valid or invalid, (65) is a BSR counter that counts the number of subroutine call instructions processed in the stages following the instruction decoding stage, (66) is a PC stack managed by the instruction decode stage (46)
The pointer DP, (67) is the pointer EP of the PC stack (46) managed by the instruction execution stage. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A first stage and a second stage,
A data processing device that processes an instruction by pipeline processing, in which the processing in the first stage precedes the processing in the second stage in response to the execution of the instruction, and stores a first instruction and data. Storage device, an address storage unit that stores one or more address values of a return destination instruction from a subroutine, and a validity indicating whether the value of each return destination address stored in the address storage unit is valid or invalid. A second storage device different from the first storage device that includes a valid bit storage unit that stores a bit in combination with a return address from the subroutine, and a value that is a return address from the subroutine is the first storage device.
First writing means for writing in the storage device, and a value which is a return address from the subroutine is stored in the second writing means.
Writing into the return address storage unit of the storage device of
Writing means for reading the first value from the second storage device, which is controlled by the first stage, and a second address which is a return address from the subroutine when the subroutine return instruction is processed. Second read means for reading the value of from the first storage device, valid bit writing means for writing a value indicating validity in the valid bit storage part of the second storage device during processing of a subroutine call instruction, and a subroutine Valid bit clearing means for writing a value indicating invalidity into the valid bit storage part of the second storage device at the time of return command processing; and storing in the valid bit storage part of the second storage device at processing of a subroutine return command Valid bit reading means for reading the valid bit stored therein, and a command from the first storage device. And a function for fetching the first instruction from the address indicated by the first value of the first storage device, and the second fetch function of the first storage device. Has a function of fetching a second instruction from the address indicated by the value of, and when the value of the valid bit read by the valid bit reading means is valid at the time of processing the subroutine return instruction, the first instruction is executed. The data processing device is characterized by executing the second instruction when the value of the valid bit read by the valid bit reading means indicates invalid. 2. A first storage device for storing instructions and data; and, unlike the first storage device, an address storage section for storing a part or all of an address value of a return destination instruction from a subroutine, and the above-mentioned. The valid bit storage unit that stores the valid bit indicating whether the value of the return address stored in the address storage unit is valid or invalid is grouped into one entry and stored as one entry, and consists of 2 ⁿ entries. Second
A first n-bit counter capable of incrementing or decrementing and managing the number of the entry, and a second n-bit counter capable of both incrementing and decrementing and managing the number of the entry. A bit counter; first reading means for reading the address value of the return destination instruction from the entry indicated by the value of the first n-bit counter of the second storage device; and the second reading device of the second storage device. first write means for writing a part or all of the address of the return destination instruction from the subroutine to the address storage section of the entry indicated by the value of the n-bit counter; and the second n-bit counter of the second storage device. Valid bit writing means for writing a value indicating valid or invalid in the valid bit storage section of the entry indicated by A valid bit reading means for reading a value of a valid bit stored in the valid bit storage section of the second storage device; and a value for writing the value of the second n-bit counter in the first n-bit counter. A data processing device comprising: a second writing unit; and a valid bit clearing unit that writes a value indicating invalidity into the valid bit storage units of all entries of the second storage device.