JPH08204669A - Data signal multiplexer demultiplexer - Google Patents

Abstract

PURPOSE: To suppress production of a data error by keeping synchronization relation of multiplexed data at the changeover device of a reference clock. CONSTITUTION: The multiplexer demultiplexer is provided with data processing circuits RN1, RN2 in which a clock synchronously with a reference clock is generated and optional data are demultiplexed into branch data from an input interface T1 based on the clock signal. Then the RN1 acts like a master and gives a synchronization clock to the RN2 as a reference clock and when an input reference clock of the RN1 being the master is interrupted, the other RN2 is acted like a master and output data from the RN1, RN2 are synchronized and given to a multiplex output interface T2. A hold-over function is provided to the RN1, RN2 and when the reference clock input of the RN1 acting like the master is interrupted, the RN1 is set to the hold-over state and after the RN2 not in the hold-over state is confirmed, the RN2 is selected to be the master.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal demultiplexing device used in, for example, a relay station or a terminal device of an optical transmission network system.

[0002]

2. Description of the Related Art Recently, a plurality of ADMs (Add Drop Multipl
The development of an optical transmission network system using an exer) device as a relay station or a terminal device (hereinafter referred to as a node) is in progress. The ADM device is a data signal demultiplexing device that can add and drop a data signal to an optical transmission line, and can add and drop a data signal corresponding to the interface to a network.

FIG. 6 shows the configuration of a conventional ADM device. T1 and T2 are input interfaces and output interfaces connected to other nodes and internal data demultiplexing processing circuits RN1 and RN2, respectively.
T1 is 1 Fb / s for 2 Fb / s data from another node
Each of them is separated into two pieces of data and sent to the data processing circuits RN1 and RN2 together with the synchronous clocks P1 and P2 of the data, and the T2 outputs the two data of 1 Fb / s from the data processing circuits RN1 and RN2. Synchronous clock CK1,
Input together with CK2, multiplex both data and send to other node.

The data processing circuits RN1 and RN2 have the same structure, and 1 Fb / s from the input interface T1.
Data is input to perform branching / insertion processing of arbitrary data, and the data is sent to the interface T2 at a rate of 1 Fb / s.

Here, in order to multiplex the data from the data processing circuits RN1 and RN2 at the output interface T2, the data must be synchronized. For this reason, the RN1 and RN2 output the respective synchronization clocks to each other so as to establish a subordinate relationship.

For example, RN1 is an input interface T
When the synchronous clock P1 from 1 is used as the reference clock, the RN2 operates using the synchronous clock S1 output from the RN1 as the reference clock. When the synchronous clock P1 from the input interface T1 is disconnected, the RN2 operates with the synchronous clock P2 from the interface T2 as a reference clock, and the RN1 operates with the synchronous clock S2 output from the RN2 as a reference clock. By such processing, the clocks used in RN1 and RN2 are kept in a dependency relationship, and thus the output data is in a synchronization relationship.

However, the conventional AD having the above structure
In the M device, when the reference clock is switched, a timing loop (a condition in which the devices request the reference clock) and a non-synchronized condition occur, which may cause a data error. This is shown in FIG.

That is, in FIG. 7, RN1 sets P1 to RN
2 uses S1 as the reference clock, and when P1 is disconnected, RN1 switches the reference clock to S2 and RN2 switches to the reference clock. In FIG. 7A, RN1 is S2.
When RN2 selects S1 and falls into the timing loop state in which the reference clocks are requested from each other, FIG.
(B) shows a case where RN1 selects P1 and RN2 selects P2, which operate with different reference clocks from each other and fall into an asynchronous state.

[0009]

As described above, in the conventional data signal demultiplexing device, there is a problem that it becomes impossible to maintain the synchronous relationship of the data multiplexed when the reference clock is switched, and a data error occurs. It was

The present invention has been made to solve the above problems, and an object of the present invention is to provide a data signal demultiplexing device which does not cause a data error, in which data to be multiplexed maintains a synchronous relationship even when a reference clock is switched. And

[0011]

In order to solve the above problems, the present invention provides a plurality of data processing circuits that generate an internal clock synchronized with a reference clock and demultiplex input data based on the internal clock. When any one of the data processing circuits is the main, its synchronous clock is supplied to other data processing circuits as a reference clock, and when the reference clock input to the main data processing circuit is disconnected, another In a data signal demultiplexing device which is mainly composed of one of the data processing circuits and has a redundant configuration to synchronize the output data of each data processing circuit, each of the plurality of data processing circuits has a reference synchronized with the input data. In addition to the function of inputting a clock and a clock from another data processing circuit and selecting and outputting one of the clocks as a reference clock, In addition to a clock selecting means having a function of detecting an input disconnection of a reference clock and transmitting input disconnection detection information and a function of generating the internal clock based on the reference clock selected by this means, a holdover command input In the state, a clock generation means having a function of internally generating and outputting a clock having the same frequency as the clock that has been selected up to now, and when receiving the input disconnection detection information, sends a holdover command to the clock generation means. At the same time, holdover information for identifying that the clock generating means is in the holdover state is sent to another data processing circuit, and holdover information from the other data processing circuit is monitored to hold all of them. Reference clock of said clock selection means when it is identified that it is not in a state Characterized in that the-option as well as switching control was set to a control means for releasing the hold-over command to the clock generating means.

[0012]

In the data signal demultiplexer having the above structure,
If each data processing circuit has a holdover function and the reference clock of the main data processing circuit is cut off, put it in the holdover state so that all the other data processing circuits are not in the holdover state. After confirmation, other data processing circuits are mainly switched, so that the multiplexed data maintains a synchronous relationship even when the reference clock is switched, and a data error does not occur.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. However, in FIG. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals, and different parts will be mainly described here.

FIG. 1 shows the configuration of an ADM apparatus according to the present invention. RN1 and RN2 are provided in addition to S1 and S2.
A function of outputting the data signals D1 and D2 which inform each other that the device itself is in the holdover state is added. Holdover (hereinafter referred to as HO) is to internally create and output a clock having the same frequency as the clock that has been selected until then, when the reference clock runs out. By adding this function, RN
1 and RN2 can maintain a synchronous relationship even when there is no reference clock, and device reliability can be improved.

As a clock switching method, it is determined that the HO state from the data signals D1 and D2 is RN.
1, RN2 confirm each other, and then perform reference clock switching. The situation is shown in FIG.

That is, RN1 and RN2 enter the HO state from the reference clock initially selected, and then switch to another reference clock. If such a process is performed, the reference clocks are switched after the mutual HO state is entered, so that the RN1 is set to S2, R as shown in FIG.
Timing loop state where N2 becomes P2, RN1 becomes P
1, the RN2 does not enter the asynchronous state of S1.

Therefore, in the ADM apparatus having the above-mentioned configuration, the output data is not caused to cause a data error in the output interface T2 because the synchronization state of each output data is maintained even when the reference clocks of RN1 and RN2 are switched.

Here, a concrete configuration of the RN1 is shown in FIG.
Shown in The RN2 has the same configuration as the RN1, and therefore the description thereof is omitted here. First, the data from the input interface T1 is received by the receiving unit 11, is input to the demultiplexing unit 12 to perform necessary data multiplexing and demultiplexing, and then is transmitted from the transmitting unit 13 to T2. Operation clock S1 of these receiver 11, demultiplexer 12, and transmitter 13
Is generated by the clock generator 14.

The clock generator 14 selects either the synchronous clock P1 from the input interface T1 or the synchronous clock S2 from the RN2 (S).
EL) 141, and a PLL circuit 142 that generates the operation clock S1 based on the synchronous clock selected by the selector 141 and has a HO function.

The PLL circuit 142 is constructed, for example, as shown in FIG. In FIG. 4, the clock from the selector 141 and the VCXO divided by the counter 1421 are used.
The phase comparator 1423 compares the phase with the clock signal from the (voltage controlled oscillator) 1422, and the analog LPF (low-pass filter) 1424 converts the phase error signal into a voltage.

Further, the A / D (analog / digital) converter 1425 converts the signal into a digital signal, the digital filter 1426 corrects the characteristic, and the D / A (digital / analog) converter 1427 restores the analog signal. The control voltage is applied to the VCXO 1422, whereby the clock S1 synchronized with the synchronization clock selected by the selector 141 is obtained. Here, the digital filter 142
By holding the process of No. 6, the above-mentioned holdover function can be realized.

Selection switching of the selector 141 and PLL
The HO switching of the circuit 142 is performed by a switching control signal from the switching control unit (CONT) 15. The switching control unit 15
The selection state of the selector 141 and the presence / absence of the input of the HO identification data signal D2 from the RN2 are monitored, and normally the selector 1
41 to select P1 (S1 in the case of RN2), and when the input disconnection is detected, the HO recognition data signal D2 from RN2.
Is not input, the synchronous clock S from RN2
Select 2 (P2 for RN2).

Further, the switching control section 15 sends an HO instruction signal to the digital filter 1426 of the PLL circuit 142 when the input loss of the selected clock is detected, and sets the PLL circuit 142 in the holdover state (at this time, the digital filter 1426 is turned off). The output HO confirmation signal is being monitored) and the data signal D1 indicating that RN1 is in the HO state is sent to RN2.

With the above configuration, the RN1 and RN2 can be set to enter the HO state when the reference clock initially selected by each becomes the disconnected state, and then switch to another reference clock.

The above example is for the case where the data signal is an electric signal, and when the data is transmitted and received by an optical signal, the receiving unit 1
1 and the transmitter 13 may be replaced with an optical receiver and an optical transmitter, respectively.

FIG. 5 shows another embodiment according to the present invention.
In this ADM device, the data signals D1 and D2 notifying the holdover state are controlled by the control device CONT.
The control device CONT determines whether the data processing circuits RN1 and RN2 are in the holdover state. After confirming that RN1 and RN2 have entered the holdover state, the control device CONT displays the data signal C prompting the switching of the reference clock.
1 and C2 are output to RN1 and RN2 to perform clock switching.

According to this circuit configuration, similarly to the embodiment shown in FIG. 1, when switching the reference clocks, RN1 and RN2.
Does not become a timing loop or an asynchronous state, the output data can be kept in a synchronous state to prevent a device data error, and the switching control section in RN1 and RN2 is unnecessary, and the circuit configuration is simple as a whole. Can be converted.

In the above embodiment, the data is from T1 to T
The case of transmission to T2 has been described, but T2 to T1
The same applies to the case of performing bidirectional processing that is also transmitted to.
In addition, various modifications can be made without departing from the spirit of the invention.

[0029]

As described above, according to the present invention, it is possible to provide a data signal demultiplexing apparatus that does not cause a data error because the multiplexed data maintains a synchronous relationship even when the reference clock is switched.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of an ADM device according to the present invention.

FIG. 2 is a timing chart for explaining the clock switching method according to the embodiment.

FIG. 3 is a block circuit diagram showing a specific configuration of a data processing circuit of the same embodiment.

FIG. 4 is a block circuit diagram showing a PLL circuit configuration in the data processing circuit of the embodiment.

FIG. 5 is a block circuit diagram showing the configuration of another embodiment according to the present invention.

FIG. 6 is a block circuit diagram showing a configuration of a conventional ADM device.

FIG. 7 is a timing diagram for explaining problems in the clock switching method of the conventional device.

[Description of Codes] T1, T2 ... Interface, RN1, RN2 ... Data processing circuit, 11 ... Receiving unit, 12 ... Demultiplexing unit, 13 ...
Transmitter, 14 ... Clock generator, 141 ... Selector, 1
42 ... PLL circuit, 1421 ... Counter, 1422 ... V
CXO, 1423 ... Phase comparator, 1424 ... Analog L
PF, 1425 ... A / D converter, 1426 ... Digital filter, 1427 ... D / A converter, 15 ... Switching control unit,
CONT ... Control device.

Claims (3)

[Claims] 1. A plurality of data processing circuits for generating an internal clock synchronized with a reference clock and performing demultiplexing of input data on the basis of the internal clock. When a clock is supplied to another data processing circuit as a reference clock and the reference clock input to the main data processing circuit is cut off, one of the other data processing circuits becomes the main and has a redundant configuration. In the data signal demultiplexing device for synchronizing the output data of each data processing circuit, each of the plurality of data processing circuits inputs a reference clock synchronized with the input data and a clock from another data processing circuit. In addition to the function of selectively outputting that clock as the reference clock, it also detects the input disconnection of the selected reference clock and sends the input disconnection detection information. In addition to the clock selecting means having the function to generate the internal clock based on the reference clock selected by this means, a clock having the same frequency as that of the clock previously selected in the holdover command input state is added. A clock generation unit having a function of internally generating and outputting, and when receiving the input disconnection detection information, sends a holdover command to the clock generation unit and identifies that the clock generation unit is in a holdover state. To the other data processing circuit, monitor the holdover information from the other data processing circuit, and when it is identified that they are not all in the holdover state, the reference of the clock selecting means. The clock selection is controlled by switching and the clock to the clock generating means is controlled. A data signal demultiplexing device comprising: a control means for releasing a field over command. 2. A plurality of data processing circuits for generating an internal clock synchronized with a reference clock and performing demultiplexing of input data on the basis of the internal clock. When a clock is supplied to another data processing circuit as a reference clock and the reference clock input to the main data processing circuit is cut off, one of the other data processing circuits becomes the main and has a redundant configuration. In the data signal demultiplexing device for synchronizing the output data of each data processing circuit, each of the plurality of data processing circuits inputs a reference clock synchronized with the input data and a clock from another data processing circuit. In addition to the function of selectively outputting that clock as the reference clock, it also detects the input disconnection of the selected reference clock and sends the input disconnection detection information. In addition to the clock selecting means having the function to generate the internal clock based on the reference clock selected by this means, a clock having the same frequency as that of the clock previously selected in the holdover command input state is added. A clock generating means having a function of internally generating and outputting, and further, based on the input disconnection detection information transmitted from the plurality of data processing circuits, a holdover command is issued to the clock generating means of the data processing circuits. At the same time as sending, holdover information for identifying that the clock generation means is in the holdover state is sent to another data processing circuit, and the holdover state from the other data processing circuit is monitored to hold all of them. When it is determined that the clock is not in the over state, the reference clock of the clock selecting means is Data signal demultiplexing device, further comprising control means for switching control of clock selection and for releasing a holdover command to the clock generation means. 3. The clock generation means includes a phase locked loop circuit that uses a digital filter as a loop filter and synchronizes a phase of a generated clock with an input clock.
4. The data signal demultiplexing device according to claim 1, wherein the digital filter output is fixed when the holdover command is input.