JPH08204557A - Digital-analog converter - Google Patents

Abstract

PURPOSE: To improve the precision by reducing the variance of the current flowing to a transistor TR which determines a constant current in a current summing type D/A converter. CONSTITUTION: If a potential Va at the connection point between a TR 31 for constant current which determines the constant current and a resistance varying TR 34 is varied to the side of a supply voltage VDD in a constant current source 11, the output voltage of a differential amplifier 35, namely, the gate voltage of the resistance varying TR 34 is reduced, and the on-state resistance value of the resistance varying TR 34 is reduced, and feedback is applied so as to reduce the potential Va to the ground side. Thus, such control is performed that the potential Va is kept constant, that is, the voltage between the source and the drain of the TR 31 for constant current is kept constant, and the variance of the current flowing to the TR 31 for constant current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current addition type digital-analog converter (hereinafter referred to as a D / A converter).

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a schematic configuration of a conventional current addition type D / A converter. This D / A converter includes a plurality of constant current source cells 101 _{1 to} 101 _m , each of which can switch the current path. Each of the constant current source cells 101 _{1 to} 101 _m includes a constant current source 102 and a switch unit 103 that switches a current system path of the output current from the constant current source 102 to a two system path. One output end of the switch unit 103 is connected to the common output current path 104, and the other output end is grounded. Output current path 1
04 is connected to the output terminal 105. This output terminal 10
When 5 is grounded via the output resistor 106, an analog signal is obtained as the voltage across the output resistor 106.

FIG. 6 is a circuit diagram showing the structure of the constant current source cell shown in FIG. This constant current source cell 101 (101 ₁
It represents ˜101 _m . ) Includes a constant current transistor 111 as a constant current source 102 and two transistors 112 and 113 as a switch unit 103.
Each of the transistors 111, 112, and 113 is composed of a P-channel MOS (metal oxide film semiconductor) type FET (field effect transistor). Transistor 111
The power supply voltage V _DD is applied to the source of and the drains are connected to the sources of the transistors 112 and 113. The drain of the transistor 112 is connected to the output current path 104, and the drain of the transistor 113 is grounded. The gate of the transistor 111 has the transistor 11
A gate voltage V _G for saturating 1 is applied. A switching signal S is applied to the gate of the transistor 112, and a switching signal bar S is applied to the gate of the transistor 113. Transistor 1
When 12 is on and the transistor 113 is off, the constant current flowing through the constant current transistor 111 is the output current path 10.
4, transistor 112 is off, transistor 1
When 13 is on, the constant current flowing through the constant current transistor 111 flows to the ground.

In this D / A converter, the switching signals S and S given to each constant current source cell 101 are controlled according to the digital signal, and the transistors 112 are provided for the constant current source cells 101 of the number corresponding to the digital signal. When turned on, the constant current flowing through the constant current transistor 111 is passed through the output current path 104. The current flowing through the output current path 104 is the sum of the output currents of the constant current source cells 101 in which the transistor 112 is on. This added output current value corresponds to an analog value. Output end 105
When is grounded via the output resistor 106, the voltage across the output resistor 106 is obtained as the product of the output current value and the resistance value of the output resistor 106, and the voltage across the output resistor 106 becomes the output voltage corresponding to the analog value.

[0005]

By the way, in such a conventional D / A converter, as shown in FIG. 5, an output current is passed through the output resistor 106 to obtain an analog value as an output voltage. In this case, the potential V _b of the output current path 104 shown in FIG. 6 changes according to the output voltage, and the potential V _{a at} the connection point of the transistors 111, 112, 113 also changes accordingly. Since the constant current transistor 111 is in a saturated operation, the influence of the fluctuation of the potential V _a is small, but the output conductance of the constant current transistor 111 is not zero, so that the fluctuation of the potential V _a , that is, the D / A converter. The fluctuation of the output voltage causes the fluctuation of the current value flowing through the constant current transistor 111.

Therefore, at present, in order to realize a highly accurate D / A converter, the channel length between the drain and the source of the constant current transistor 111 is increased to reduce the output conductance. However, there is a problem that the D / A converter of about 10 bits is the limit and it is difficult to realize higher precision.

Further, if the channel length between the drain and the source of the constant current transistor 111 is increased in order to realize a highly accurate D / A converter, there is a problem that the D / A converter becomes large in size. .

The present invention has been made in view of the above problems. A first object of the present invention is to reduce fluctuations in the current flowing through a transistor that determines a constant current, thereby improving accuracy. To provide a D / A converter of.

A second object of the present invention is, in addition to the above objects,
It is to provide a D / A converter that can be downsized.

[0010]

According to a first aspect of the present invention, there is provided a D / A converter including an output current path for outputting a current according to an analog value, a constant current transistor for determining a constant current, and a digital current. A constant voltage between a plurality of constant current source cells having a switch section for selectively outputting a constant current flowing through a constant current transistor to an output current path according to a signal and a terminal through which the constant current of the constant current transistor flows is constant. And a control means for performing control for keeping the above.

A D / A converter according to a second aspect is the first aspect.
In the D / A converter described above, the control means is provided between the constant current transistor and the switch unit for each constant current source cell, and the resistance variable transistor whose resistance value changes in accordance with the control voltage, Control that is provided for each constant current source cell and that generates a control voltage that keeps this potential constant according to the potential between the variable resistance transistor and the constant current transistor, and gives it to the variable resistance transistor And a voltage generating means.

A D / A converter according to a third aspect is the first aspect.
In the D / A converter described, each of the constant current transistors of the plurality of constant current source cells outputs a constant current having the same value, and each of the switch units of the plurality of constant current source cells is In order from the constant current source cells for the lower bits, only the constant current source cells of the number corresponding to the value of the digital signal operate to output the constant current to the output current path, and the control means controls the constant current sources. A variable resistance transistor, which is provided between the constant current transistor and the switch section for each source cell, and whose resistance value changes according to the control voltage, and a constant variable source transistor for the constant current source cell for the least significant bit. In accordance with the potential between the current transistor and the current transistor, a control voltage generating means for generating a control voltage for keeping this potential constant and providing it to the resistance variable transistors of all cells is provided. .

A D / A converter according to a fourth aspect is the first aspect.
In the D / A converter described in any one of 1 to 3,
The constant current transistor is a field effect transistor that allows a constant current to flow between the source and the drain, and the control means is configured to perform control to keep the voltage between the source and drain of the field effect transistor constant.

[0014]

In the D / A converter according to the first aspect, the constant current flowing through the constant current transistor is selectively output to the output current path by the switch unit according to the digital signal for each constant current source cell. The current flowing through the output current path becomes a current according to the analog value. Further, the control means performs control to keep the voltage between the terminals of the constant current transistors through which the constant current flows constant, and as a result, fluctuations in the current flowing through the constant current transistors are reduced.

According to another aspect of the D / A converter of the present invention, the control voltage generating means sets the potential of each constant current source cell according to the potential between the resistance varying transistor and the constant current transistor. A control voltage that keeps constant is generated, this control voltage is given to the resistance variable transistor, the resistance value of the resistance variable transistor changes, and the potential between the resistance variable transistor and the constant current transistor changes. Is kept constant.

According to another aspect of the D / A converter of the present invention, each of the constant current transistors of the plurality of constant current source cells outputs a constant current of the same value, and each of the switch units of the plurality of constant current source cells. Operates so as to output the constant current to the output current path only from the constant current source cell for the least significant bit, in the order of the constant current source cells corresponding to the value of the digital signal. The control means, by the control voltage generation means, generates a control voltage for keeping the potential constant according to the potential between the resistance variable transistor and the constant current transistor of the constant current source cell for the least significant bit. Then, it is applied to the resistance variable transistors of all cells. As a result, the resistance values of the variable resistance transistors of all cells change, and for all constant current source cells that output a constant current to the output current path, the resistance between the variable resistance transistor and the constant current transistor is The potential is kept constant.

According to another aspect of the D / A converter of the present invention, the control means performs control for keeping the voltage between the source and drain of the field effect transistor as a constant current transistor constant.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a D / A according to the first embodiment of the present invention.
It is a block diagram which shows the structure of a converter. D / of this embodiment
The A converter 10 is an example of a 10-bit current addition type D / A converter. The D / A converter 10 includes 63 unit current source cells 11a that output a unit current I ₀ as constant current source cells, and 1/2, 1/4, and 1/4 of the unit current I ₀ , respectively.
It is provided with four weighted current source cells 11b to 11e which output currents of 1/8 and 1/16. D / A converter 10
Is the upper 3 bits of the 10-bit digital signal.
A decoder 12 that decodes bits to generate a switching signal to be supplied to the unit current source cell 11a, a latch 13 that latches the switching signal generated by the decoder 12 and that is to be supplied to the unit current source cell 11a, and 10
A decoder 14 that decodes the next 3 bits of the bit digital signal to generate a switching signal to be supplied to the unit current source cell 11a, and a switching signal that is generated by this decoder 14 are latched, and the unit current source cell 11a is latched. To the weighting current source cells 11b to 11e.

The D / A converter 10 further includes each latch 1
Clock generator 1 for supplying clocks to 3, 15 and 16
7, a unit current source cell 11a and a bias power source 18 for supplying a bias voltage to each of the weighted current source cells 11b to 11e. The D / A converter 10 further includes each unit current source cell 11a and each weighted current source cell 11b-1.
An output current path 20 for outputting a current according to an analog value is provided, which is connected to 1e. This output current path 20
Is connected to the output terminal 21.

FIG. 2 is a circuit diagram showing the configuration of the constant current source cell in FIG. The constant current source cell 11 (representing the unit current source cell 11a and the weighted current source cells 11b to 11e) is a constant current transistor 31 that determines a constant current.
And two switching transistors 32 and 33 as a switch section, and a resistance variable transistor 34 that is provided between the constant current transistor 31 and the transistors 32 and 33 and whose resistance value changes according to the control voltage. this and variable resistance transistor 34 in accordance with the potential V _a between the constant current transistor 31, and generates a control voltage so as to keep the electric potential V _a constant, variable resistance transistor 34
, And a differential amplifier 35 as a control voltage generating means.

The transistors 31, 32, 33 and 34 are
Both are composed of P-channel MOS type FETs.
The power supply voltage V _DD is applied to the source of the transistor 31, and the drain is connected to the source of the transistor 34. The drain of the transistor 34 is the transistor 3
It is connected to 2,33 sources. Transistor 32
Of the transistor 33 is connected to the current path 20a, and the drain of the transistor 33 is connected to the current path 20b. One of the current system path 20a and the current system path 20b is the output current path 20.
Used as. In the current system path 20a, the current value increases as the value of the digital signal increases.
At 0b, the current value decreases as the value of the digital signal increases, and the current system path 20a and the current system path 20b have a complementary relationship. Transistor 3 is at the gate of transistor 31
A gate voltage V ₁ for saturating ₁ is applied. The switching signal S is applied to the gate of the transistor 32, and the switching signal bar S is applied to the gate of the transistor 33. The potential Va between the transistor 34 and the transistor 31 is applied to the inverting input terminal of the differential amplifier 35, and the power supply voltage V _a is applied to the non-inverting input terminal.
A reference voltage obtained by stepping down _DD by the power supply 36 is applied. The output terminal of the differential amplifier 35 is connected to the gate of the transistor 34.

Next, the main operation of the D / A converter 10 of this embodiment will be described. The decoder 12 sets the eight unit current source cells 11a as one column, and outputs the unit current I ₀ from the unit current source cells 11a in the number of columns represented by the upper 3 bits of the 10-bit digital signal. The switching signal S, S is generated to be output to the path 20. The switching signals S and S are supplied to the unit current source cell 11a via the latch 13. Therefore, for example, when the 3-bit data is “010”, the unit current I ₀ is output to the output current path 20 from the two columns, that is, 16 unit current source cells 11 a.

The decoder 14 outputs the unit current I ₀ from the unit current source cells 11a of the number represented by the next 3 bits of the 10-bit digital signal among the seven unit current source cells 11a. The switching signals S and S are generated so as to be output to the current path 20. The switching signals S and S are supplied to the unit current source cell 11a via the latch 15. Therefore, for example, when the 3-bit data is “011”, the unit current I ₀ is output to the output current path 20 from the three unit current source cells 11 a.

Further, the latch 16 latches the lower 4 bits of the 10-bit digital signal and supplies them to the weighted current source cells 11b to 11e. Accordingly, the current I _0/2 and the current I _0/16 from the cell 11b and the cell 11e is output to the output current path 20 in the case of, for example, 4-bit data is "1001".

The current flowing through the output current path 20 is the sum of the output currents of the unit current source cell 11a and the weighted current source cells 11b to 11e. This added output current value corresponds to an analog value. Output terminal 21 to output resistance 22
When grounded via, the voltage across the output resistor 22 is obtained as the product of the output current value and the resistance value of the output resistor 22, and the voltage across the output resistor 22 becomes the output voltage corresponding to the analog value.

Next, the control for keeping the voltage between the source and drain of the constant current transistor 31 in the D / A converter 10 of the present embodiment constant will be described. As shown in FIG. 1, the output current flowing through the output current path 20 is changed to the output resistance 22.
When the analog value is supplied to the output voltage, the potential of the output current path 20 changes according to the output voltage. Here, if the on-resistance of the variable resistance transistor 34 is constant, also varies the potential V _a of the connection point of the transistors 31, 34. Here, the constant current transistor 3
It is known that the current _IDS flowing between the source and the drain of the constant current transistor 31 when 1 is operating in the saturation region is represented by the following equation.

[0028]

[Number 1] _{I DS = -K' (W / 2L} ) (V GS -V TP)
² (1-λV _DS )

Here, K'is a predetermined coefficient, W is a channel width, L is a channel length, V _GS is a source-gate voltage, V
_TP is the threshold voltage, λ is the reciprocal of the Early voltage V _A , and V _DS is the source-drain voltage.

In FIG. 2, when V _DD and V ₁ are constant, the factor that varies I _DS without considering variations due to process variations is the variation in source-drain voltage V _DS . In the conventional constant current source cell 101 as shown in FIG. 6, the constant current transistor 11 changes as the output voltage changes.
Since the voltage V _DS between the source and drain of No. 1 changes, a transistor having a long channel length L is used as the constant current transistor 111 in order to reduce λ and suppress the fluctuation of I _DS .

On the other hand, in the present embodiment, if the potential V _{a at} the connection point between the transistors 31 and 34 changes to the power supply voltage V _DD side by the resistance varying transistor 34 and the differential amplifier 35, the differential amplifier 35. the output voltage or gate voltage of the variable resistance transistor 34 decreases, the resistance on the resistance value of the variable transistor 34 is decreased, feedback, such as lowering the potential V _a on the ground side is applied. In this way, in this embodiment, the control for keeping the potential V _a constant, that is, the control for keeping the voltage between the source and drain of the constant current transistor 31 constant is performed, and as a result, the output voltage fluctuates. Even constant current transistor 31
Fluctuations in the current flowing through the D / A converter can be reduced and the accuracy of the D / A converter can be improved.

Further, in the present embodiment, since it is not necessary to increase the channel length L of the constant current transistor 31 as in the conventional case, for example, in the process of the minimum line width of 0.5 μm, the constant current transistor 31 of The size (area) can be reduced to about 1/4 of the conventional size, and the D / A converter can be downsized even if the resistance variable transistor 34 and the differential amplifier 35 are increased.

FIG. 3 shows a D / A according to the second embodiment of the present invention.
It is a circuit diagram which shows the structure of the constant current source cell in a converter. Constant current source cell 11 in this embodiment, in response to the potential V _a between the variable resistance transistor 34 and constant current transistor 31, and generates a control voltage so as to keep the electric potential V _a constant, As the control voltage generating means applied to the resistance varying transistor 34, a transistor 38 and a transistor 39 are provided instead of the differential amplifier 35 in the first embodiment. The transistor 38 is a P-channel MOS type FET, and the transistor 39 is an N-channel MOS type FET. Transistor 3
The source of 8 is applied with the power supply voltage V _DD , the gate is applied with the potential V _a , and the drain is connected to the drain of the transistor 39. The source of the transistor 39 is grounded, and the gate voltage V ₂ for operating the transistor 39 in the saturation region is applied to the gate.

[0034] In the constant current source cells 11, if variable potential V _a of the connection point of the transistors 31 and 34 to the power supply voltage V _DD side, the on-resistance of the transistor 38 is increased,
The potential at the connection point between the transistors 38 and 39, that is, the gate voltage of the resistance varying transistor 34 decreases, and the on-resistance value of the resistance varying transistor 34 decreases.
Feedback is applied to lower the potential V _a to the ground side. In this way, the control to maintain the potential V _a constant, i.e., the control to keep the source of the constant current transistor 31, the voltage between the drain constant is performed. Other configurations, operations and effects of this embodiment are similar to those of the first embodiment.

FIG. 4 shows a D / A according to the third embodiment of the present invention.
It is a circuit diagram which shows the structure of a converter. The D / A converter of this embodiment is an n-bit D / A converter, and 2 ⁿ -1 constant current source cells 41 that output constant currents of the same value.
_{1 to} 41 ₂ ⁿ _-1 . Each constant current source cell 41 (4
It represents 1 _{1 to} 41 ₂ ⁿ _-1 . ) Is a constant current transistor 31 similar to the first embodiment, two switch transistors 32 and 33, and a resistance variable transistor 34.
It has and. The power supply voltage V _DD is applied to the source of the transistor 31, and the drain is connected to the source of the transistor 34. The drain of the transistor 34 is connected to the sources of the transistors 32 and 33. The drain of the transistor 32 is connected to the output current path 20. The drain of the transistor 33 is grounded.
The output current path 20 is connected to the output end 21. A gate voltage V ₁ for saturating the transistor 31 is applied to the gate of the transistor 31. Each cell 4
Switching signals S _{1 to} S ₂ ⁿ _-1 are applied to the gates of the transistors 32 of 1 _{1 to} 41 ₂ ⁿ _-1 , respectively, and switching signals are applied to the gates of the transistors 33 of the cells 41 _{1 to} 41 ₂ ⁿ _-1. The bars S ₁ to S ₂ ⁿ _-1 are applied. The D / A converter according to the present embodiment further includes a decoder (not shown). This decoder starts from the constant current source cell 41 ₁ for the least significant bit, and outputs a constant current of a number corresponding to the value of the n-bit digital signal. Switching signals S ₁ to output a constant current to the output current path 20 only in the source cell
S ₂ ⁿ _-1 , bar S ₁ to bar S ₂ ⁿ _-1 are generated.

The D / A converter of the present embodiment is further provided with a potential V _a between the transistor 34 and the transistor 31 of the constant current source cell 41 ₁ for the least significant bit according to the potential V a.
A control voltage is generated to keep _a constant, and all cells 41
The differential amplifier 35 is provided as a control voltage generating means to be applied to the resistance varying transistors 34 of _{1 to} 41 ₂ ⁿ _-1 . The inverting input terminal of the differential amplifier 35 the potential V _a between the transistor 34 and the transistor 31 of the constant current source cells 41 ₁ for the least significant bit is applied, the power supply voltage V _DD to the non-inverting input terminal The reference voltage reduced by 36 is applied. The output terminals of the differential amplifier 35 are all cells 41 ₁ ...
It is connected to the gate of the resistance variable transistor 34 of 41 ₂ ⁿ _-1 .

In the D / A converter of the present embodiment, each transistor 32 of the constant current source cells 41 _{1 to} 41 ₂ ⁿ _-1 has a digital signal value in order from the constant current source cell 41 ₁ for the least significant bit. The number of constant current source cells corresponding to the number of the constant current source cells operates to output the constant current to the output current path 20. Therefore, except when the digital signal is "0 (zero)", the transistor 32 of the constant current source cell 41 ₁ for the least significant bit is always on. In this embodiment, the differential amplifier 35 in response to the potential V _a in the constant current source cells 41 ₁ for the least significant bit, and generates a control voltage so as to keep the electric potential V _a constant, all the cells 41 _{It is applied to} the resistance varying transistor 34 of _{1 to} 41 ₂ ⁿ _-1 .

When the output current system path of the constant current source cell 11 is a two-system path as in the first or second embodiment, which current system path is selected for each constant current source cell 11. It is necessary to change the control voltage applied to the resistance varying transistor 34 depending on whether the control voltage is variable. On the other hand, as in this embodiment,
If the output current pathway of the constant current source cell 41 is a single, since the potential V _a only when outputting a constant current to the output current path 20 may be controlled to be constant, the digital signal is " A constant current is always output except when it is 0 (zero) ".
Constant current source cell 41 ₁ for the least significant bit outputting to 0
The control voltage generated on the basis of the potential V _a at the reference point is used as the resistance variable transistor 34 of all the cells 41 _{1 to} 41 ₂ ⁿ _-1.
The constant current transistors 31 in all the constant current source cells 41 that are outputting the constant current to the output current path 20.
It is possible to control the voltage between the source and drain of the device to be constant. When the digital signal is "0 (zero)", the output voltage is also zero, and therefore control for keeping the voltage between the source and drain of the constant current transistor 31 constant is unnecessary.

According to the present embodiment, since only one differential amplifier 35 as the control voltage generating means is required, the differential amplifier 35 is provided.
Compared to the case where the cells are provided for each of the cells 41 _{1 to} 41 ₂ ⁿ _-1
It is possible to downsize the / A converter. Other operations and effects are similar to those of the first embodiment. In this embodiment, instead of the differential amplifier 35, the transistors 38 and 39 shown in FIG. 3 may be provided.

The present invention is not limited to the above-mentioned embodiments. For example, in the embodiment, an F transistor is used as a constant current transistor.
Although ET is used, it is also possible to use a bipolar transistor.

[0041]

As described above, according to the D / A converter of the first or second aspect, the control means controls the constant voltage of the constant current transistors to keep the voltage between the terminals constant. Since this is done, there is an effect that the fluctuation of the current flowing through each constant current transistor is reduced and the accuracy of the D / A converter can be improved.

Further, according to the D / A converter of the third aspect, each constant current transistor of the plurality of constant current source cells comprises:
The constant current of the same value is output respectively, and each switch unit of the plurality of constant current source cells sequentially from the constant current source cell for the least significant bit, only the number of constant current source cells corresponding to the value of the digital signal, It is configured to operate so as to output a constant current to the output current path, and by the control voltage generation means, the potential between the variable resistance transistor and the constant current transistor of the constant current source cell for the least significant bit is set. Accordingly, a control voltage that keeps this potential constant is generated and applied to the resistance variable transistors of all cells.
In addition to the above effect, there is an effect that the control voltage generating means is shared by all the cells and the D / A converter can be downsized.

According to the D / A converter of the fourth aspect, in the D / A converter using the field effect transistor as the constant current transistor, the fluctuation of the current flowing through the constant current transistor is reduced. In addition, there is no need to increase the channel length between the source and drain of the constant current transistor, and in addition to the above first effect, there is an effect that the D / A converter can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a D / A converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a constant current source cell in FIG.

FIG. 3 is a circuit diagram showing a configuration of a constant current source cell in a D / A converter according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a D / A converter according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a schematic configuration of a conventional current addition type D / A converter.

6 is a circuit diagram showing a configuration of a constant current source cell in FIG.

[Explanation of symbols]

 10 D / A Converter 11 Constant Current Source Cell 11a Unit Current Source Cell 11b to 11e Weighted Current Source Cell 20 Output Current Path 21 Output Terminal 22 Output Resistance 31 Constant Current Transistor 32, 33 Switch Transistor 34 Resistance Variable Transistor 35 Differential amplifier

Claims (4)

[Claims] 1. An output current path for outputting a current according to an analog value, and a constant current transistor for determining a constant current, respectively.
Between a plurality of constant current source cells having a switch section that selectively outputs a constant current flowing through the constant current transistor to the output current path according to a digital signal, and between terminals where the constant current of the constant current transistor flows. And a control means for controlling the voltage of the device to be kept constant. 2. The control means is provided between the constant current transistor and the switch section for each constant current source cell, and the resistance variable transistor whose resistance value changes according to the control voltage, and each constant current. It is provided for each source cell, and according to the potential between the variable resistance transistor and the constant current transistor,
2. The digital-analog converter according to claim 1, further comprising a control voltage generating means for generating a control voltage for keeping the potential constant and supplying it to the resistance varying transistor. 3. The constant current transistors of the plurality of constant current source cells each output a constant current of the same value, and each switch unit of the plurality of constant current source cells is for a least significant bit. In order from the constant current source cells, only the constant current source cells of the number corresponding to the value of the digital signal operate so as to output the constant current to the output current path, and the control means controls each constant current source cell. The variable resistance transistor, which is provided between the constant current transistor and the switch unit and whose resistance value changes according to the control voltage, and the variable resistance transistor and the constant current transistor of the constant current source cell for the least significant bit. 2. The control voltage generating means for generating a control voltage for keeping the potential constant according to the potential between the control voltage and the control voltage generation means for applying the control voltage to the resistance variable transistors of all cells. Digital Rule-analog converter. 4. The constant current transistor is a field effect transistor for flowing a constant current between a source and a drain,
4. The digital control according to claim 1, wherein the control means controls the voltage between the source and the drain of the field effect transistor to be constant.
Analog converter.