JPH0424892B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a DA conversion circuit built into a one-chip microcomputer or the like.

(b) Conventional technology In general, there are various types of DA conversion circuits, such as those using an R-2R ladder resistance network, those using PWM (pulse width modulation) modulation, and those that select divided voltage. Things are being thought of.

The DA conversion circuit built into a microcomputer or the like is easily constructed, and therefore, a type in which a voltage divided by series resistors is selected depending on the value of digital data is used.

Figure 2 shows a conventional divided voltage selection type DA conversion circuit, in which 2 ⁿ + 1 (n is the number of bits of digital data) resistors R are connected in series between voltage Va and voltage Vb, and the connection point is One end of a transmission gate 1 is connected to each, and the other end of the transmission gate 1 is commonly connected to an analog output terminal 2. These plurality of transmission gates 1 are controlled by the output of the decoder 3 to which digital data D ₁ -D _o are applied, and one transmission gate specified by the value of the digital data D ₁ -D _o 1 is turned on, and the divided voltage at the connected node is output to the analog output terminal 2.

Such a DA conversion circuit is disclosed in Japanese Patent Application Laid-Open No. 62-24713.
It is stated in the No.

(c) Problems to be Solved by the Invention However, in the transmission gate 1 shown in FIG. 2, the substrate electrode of the N-channel MOSFET is connected to the ground voltage _Vss , and the
Since the substrate electrode of the channel MOSFET is connected to the power supply voltage V _DD , the input characteristics of its transmission gate 1 change to the midpoint of the input voltage V _IN due to the backgate bias effect, as shown in Figure 3a. The on-resistance was high near the level. Therefore, when extracting a voltage near the intermediate voltage divided by the resistor R, there is a drawback that an error occurs in the extracted voltage due to the influence of the on-resistance.

Therefore, in order to eliminate the backgate bias effect, it is conceivable to apply a voltage to the substrate electrode to the source electrode. For example, N channel
The input characteristics when the MOSFET substrate is applied to the source are as shown in FIG. 3b. This reduces the on-resistance of the transmission gate, but has the disadvantage that the pattern area increases because the N-channel MOSFET of transmission gate 1 in FIG. 2 must be formed in an independent well region. There is. Furthermore, if the lower voltage of the divided voltages is selected at the transmission gate, the selected voltage is the N-channel of the transmission gate where the higher voltage is applied to the source and substrate.
Since the voltage is applied to the drain of the MOSFET, there is an inconvenience that a forward bias is created between the drain of the N-channel MOSFET and the substrate.

(d) Means for solving the problems The present invention was created in view of the above points, and each N channel of a transmission gate selects a voltage divided by a resistor.
MOSFETs or P-channel MOSFETs are formed in the same well region of a semiconductor substrate, and a predetermined voltage divided by the resistor or a predetermined voltage is selected by a predetermined bit of digital data and applied to the well region. It is equipped with a voltage switching circuit.

(e) Effect According to the above-mentioned means, when one of the voltages divided by the resistors is selected according to the value of digital data, the selected voltage is selected from predetermined voltages prepared in advance. Since the nearest and lowest predetermined voltage is selected by the voltage switching circuit and applied to the well region, the back gate bias effect is reduced and the reverse bias with respect to the drain is maintained.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
2 ⁿ +1 (n is the number of bits of digital data) resistors 4 are connected in series between the voltage Va and the voltage Vb (ground voltage), and one end of the signal path of the transmission gate 5 is connected to each connection point. has been done. Also,
The other ends of the signal paths of the transmission gates 5 are commonly connected to an analog output terminal 6. The decoder 7 receives input n-bit digital data D ₁
It outputs signals S ₁ to S ²ⁿ for selecting one of the transmission gates 5 from ~D _o , and the signals S ₁ to ^{S 2n} select N of the transmission gates 5.
Each inverted signal S 1 to S 2n of the signals S ₁ to ^{S 2n} is applied to the gate of the channel MOSFET 8, and each inverted signal S ₁ to ^{S 2n} is applied to the gate of the channel MOSFET 8.
Applied to the gate of MOSFET9.

N channel of transmission gate 5
A broken line 10 surrounding the MOSFET 8 indicates the same well region on the semiconductor substrate, and the P well region, that is, the substrate electrode of each N-channel MOSFET 8 is connected to the voltage switching circuit 11.
This voltage switching circuit 11 is connected to each N channel.
N-channel MOSFET whose drains are both connected to the connection line from the substrate of MOSFET8
12, 13, one N channel
The source of MOSFE12 is connected to the ground potential _Vss ,
The source of the other N-channel MOSFET 13 is
It is connected to the voltage Vm at approximately the midpoint of the resistor 4.
Further, a bit signal D _o of digital data output from the decoder 3 is applied to the gate of the N-channel MOSFET 13, and the N-channel MOSFET 13 is
A bit signal Do is applied to the gate of the MOSFET 12, and an inverted _{signal o} of the bit signal _Do is applied to the gate of the N-channel MOSFET 12.

Here, assuming that the ground voltage _Vss = Vb = O, the voltage switching circuit 11 converts the digital data D ₁ to
The divided voltage Vx selected by D _o is the divided voltage
If the voltage is larger than Vm, the voltage switching circuit 11 applies the voltage Vm to the P-well region 10, whereas if the divided voltage Vx selected by _the digital data D ₁ to Do is O<Vx<Vm Voltage switching circuit 11
applies the ground voltage V _ss =O to the P-well region 10. That is, in the former case, digital data D _o
is “1” and the N-channel MOSFET 13 is turned on, and in the latter case, the digital data D _o is “0”
Therefore, the N-channel MOSFET 12 is turned on.

In this way, when one of the voltages divided by the resistor 4 is selected by the transmission gate 5, the voltage lower and closest to the selected voltage Vx is selected and P By applying the voltage to the well region 10, the back gate bias of the N-channel MOSFET 8 in the P-well region 10 is reduced, and furthermore, the region between the drain and the P-well region 10 is no longer biased in the forward direction.

In the embodiment shown in FIG. 1, two types of voltages are applied to the P-well region 10, and the digital data is
Selected with 1 bit of D _o , but digital data
Four types of voltages may be applied to the P well region 10 using D _o-1 and D _o . In this case, the boundary of the division range of the divided voltage selected by the digital data D _o-1 and D _o , for example, the divided voltage selected when D _o-1 and D _o are "1, 1". The divided voltage at the boundary of the range and the divided voltage range selected in the state of "0, 1" is used as the voltage applied to the P-well region 10, and the four decoded digital data Do _-1 , _Do is selected by an N-channel MOSFET controlled by a signal.

(G) Effects of the Invention As described above, according to the present invention, by reducing the backgate bias effect without increasing the pattern area, the on-resistance of the transmission gate is reduced, and the on-resistance of the transmission gate is reduced. This provides a DA conversion circuit in which the error when extracting the applied voltage is reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, and FIGS. 3a and 3b are diagrams showing input characteristics of a transmission gate. 4...Resistor, 5...Transmission gate, 6...Analog output terminal, 7...Decoder,
10...P well region, 11... Voltage switching circuit.

Claims (1)

[Claims] 1 A plurality of resistors are connected in series between a predetermined potential difference, one end of each is connected to the connection point of the resistors, the other end is commonly connected to the analog output terminal, and the N-channel MOSFET and P-channel MOSFET are connected in parallel. a plurality of transmission gates configured with a plurality of transmission gates, and a signal to which digital data is applied and which selectively controls the plurality of transmission gates based on the digital data is output to a control electrode of the transmission gate. In the DA conversion circuit equipped with a decoder circuit that
are formed in the same well region on the semiconductor substrate,
A DA conversion circuit comprising a voltage switching circuit that selects a predetermined voltage divided by the plurality of resistors or a predetermined predetermined voltage based on a predetermined bit of the digital data and applies the selected voltage to the well region.