JPH08204316A - Printed wiring board and its manufacture - Google Patents
Printed wiring board and its manufactureInfo
- Publication number
- JPH08204316A JPH08204316A JP1175895A JP1175895A JPH08204316A JP H08204316 A JPH08204316 A JP H08204316A JP 1175895 A JP1175895 A JP 1175895A JP 1175895 A JP1175895 A JP 1175895A JP H08204316 A JPH08204316 A JP H08204316A
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- solder
- layer
- resist
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁基板の表面に、導体
回路、及び、非半田接合面にソルダーレジスト層を形成
したプリント配線板、及び、その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board in which a conductor circuit is formed on the surface of an insulating substrate and a solder resist layer is formed on a non-solder joint surface, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】電子機器等に用いられるプリント配線板
は、絶縁基板の表面に導体回路、及び、非半田接合面に
ソルダーレジスト層を形成する。上記ソルダーレジスト
層を形成するソルダーレジストとして、ＵＶ硬化型ソル
ダーレジスト、及び、熱硬化型ソルダーレジストが知ら
れている。近年の回路形成のファイン化の要求に伴っ
て、上記ＵＶ硬化型ソルダーレジストが汎用されてい
る。しかし、このＵＶ硬化型ソルダーレジストを用いた
場合は、熱硬化型ソルダーレジストを用いた場合に比
べ、レジストのにじみがなく、回路形成のファイン化に
は適するものの、半田処理後、及び、高温高湿状態で保
管した場合に、絶縁基板や導体回路との密着性が低下す
る。2. Description of the Related Art In a printed wiring board used for electronic equipment or the like, a conductor circuit is formed on the surface of an insulating substrate, and a solder resist layer is formed on the non-solder joint surface. UV-curable solder resists and heat-curable solder resists are known as solder resists for forming the solder resist layer. With the recent demand for finer circuit formation, the UV-curable solder resist is widely used. However, when this UV-curable solder resist is used, there is no bleeding of the resist as compared with the case of using a thermosetting solder resist, which is suitable for finer circuit formation, but after soldering and at high temperature and high temperature. When stored in a damp state, the adhesion with the insulating substrate and the conductor circuit deteriorates.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記の問題点
を解消するためになされたもので、その目的とするとこ
ろは、半田処理後や高温高湿保管後の密着性が良好で、
且つ、回路形成のファイン化に適したプリント配線板、
及び、その製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its purpose is to provide good adhesion after soldering or after storage at high temperature and high humidity.
And a printed wiring board suitable for finer circuit formation,
And to provide a method for manufacturing the same.
【０００４】[0004]
【課題を解決するための手段】本発明の請求項１に係る
プリント配線板は、表面に導体回路２が形成された絶縁
基板１の非半田接合面をソルダーレジスト層５で被覆し
たプリント配線板であって、上記ソルダーレジスト層５
の層構成は、上記導体回路２の非半田接合面となる端部
と接する内層が、ＵＶ硬化型ソルダーレジストが硬化し
たＵＶ硬化レジスト層３と、その外層が熱硬化型ソルダ
ーレジストが硬化した熱硬化レジスト層４とからなり、
且つ、上記ＵＶ硬化レジスト層３の境界縁３ａが露出し
ていることを特徴とする。A printed wiring board according to claim 1 of the present invention is a printed wiring board in which a non-solder joint surface of an insulating substrate 1 having a conductor circuit 2 formed on its surface is covered with a solder resist layer 5. And the solder resist layer 5
In the layer structure, the inner layer in contact with the end portion which is the non-solder joint surface of the conductor circuit 2 is the UV curable resist layer 3 in which the UV curable solder resist is cured, and the outer layer is the heat in which the thermosetting solder resist is cured. Consisting of a cured resist layer 4,
In addition, the boundary edge 3a of the UV curable resist layer 3 is exposed.
【０００５】本発明の請求項２に係るプリント配線板の
製造方法は、絶縁基板１の表面に導体回路２を形成し、
絶縁基板１の非半田接合面に、上記導体回路２の端部に
接してＵＶ硬化型ソルダーレジストを用い、ＵＶ硬化レ
ジスト層３を形成した後に、このＵＶ硬化レジスト層３
の外面に熱硬化型ソルダーレジストを塗布し、熱硬化レ
ジスト層４を、ＵＶ硬化レジスト層３の境界縁３ａが露
出するように形成することを特徴とする。A method of manufacturing a printed wiring board according to a second aspect of the present invention comprises forming a conductor circuit 2 on the surface of an insulating substrate 1,
After the UV curable solder resist is formed on the non-solder joint surface of the insulating substrate 1 in contact with the end portion of the conductor circuit 2 and the UV curable resist layer 3 is formed, the UV curable resist layer 3 is formed.
A heat-curable solder resist is applied to the outer surface of, and the heat-curable resist layer 4 is formed so that the boundary edge 3a of the UV-curable resist layer 3 is exposed.
【０００６】以下、本発明を図面に基づいて詳細に説明
する。図１は本発明の一実施例に係るプリント配線板の
要部を拡大した断面図であり、図２（ａ）、（ｂ）は本
発明の一実施例に係るプリント配線板の製造方法のステ
ップを示す要部拡大断面図である。The present invention will be described below in detail with reference to the drawings. FIG. 1 is an enlarged cross-sectional view of a main part of a printed wiring board according to an embodiment of the present invention, and FIGS. 2A and 2B show a method for manufacturing a printed wiring board according to an embodiment of the present invention. It is a principal part expanded sectional view which shows a step.
【０００７】本発明のプリント配線板は、図１に示す如
く、表面に導体回路２が形成された絶縁基板１の非半田
接合面をソルダーレジスト層５で被覆したものである。
上記絶縁基板１は、基材に樹脂を含浸して得られるプリ
プレグの樹脂を硬化させた有機系の絶縁基板、又はアル
ミナ等のセラミック系の絶縁基板が挙げられる。この有
機系の絶縁基板の樹脂としてはエポキシ樹脂、ポリイミ
ド樹脂、フッ素樹脂、フェノール樹脂、ＰＰＯ樹脂等の
単独、変性物、混合物等が挙げられる。有機系の絶縁基
板の基材としては、例えばガラス、アスベスト等の無機
繊維、ポリエステル、ポリアミド、ポリビニルアルコー
ル、アクリル等の有機合成繊維、木綿等の天然繊維から
なる織布、不織布、マット、紙及びこれらの組合せた基
材が用いられ、なかでも、無機繊維が耐熱性、耐湿性に
優れて好ましい。上記導体回路２は、例えば、上記絶縁
基板１の表面に配設された銅等の金属箔にエッチング等
を施し形成される。As shown in FIG. 1, the printed wiring board of the present invention has a solder resist layer 5 covering the non-solder joint surface of an insulating substrate 1 having a conductor circuit 2 formed on the surface thereof.
Examples of the insulating substrate 1 include an organic insulating substrate obtained by curing a resin of a prepreg obtained by impregnating a base material with a resin, or a ceramic insulating substrate such as alumina. Examples of the resin for the organic insulating substrate include epoxy resin, polyimide resin, fluororesin, phenol resin, PPO resin, and the like alone, modified products, and mixtures. As the base material of the organic insulating substrate, for example, inorganic fibers such as glass and asbestos, organic synthetic fibers such as polyester, polyamide, polyvinyl alcohol, and acrylic, woven fabrics, non-woven fabrics, mats, papers made of natural fibers such as cotton, and A base material in which these are combined is used, and among them, inorganic fibers are preferable because they are excellent in heat resistance and moisture resistance. The conductor circuit 2 is formed, for example, by etching a metal foil such as copper provided on the surface of the insulating substrate 1 and the like.
【０００８】上記プリント配線板は、半田を付着させる
導体回路２の半田接合面６を露出し、絶縁基板１の非半
田接合面をソルダーレジスト層５で被覆している。上記
ソルダーレジスト層５の層構成は、内層がＵＶ硬化型ソ
ルダーレジストが硬化したＵＶ硬化レジスト層３、及
び、外層が熱硬化型ソルダーレジストが硬化した熱硬化
レジスト層４からなる。上記ＵＶ硬化レジスト層３は、
例えば、導体回路２を形成した絶縁基板１の上にＵＶ硬
化型ソルダーレジストを塗布し、ドライフィルムを用い
非半田接合面となる箇所を露光すると、ソルダーレジス
トが硬化し、その後、ソルダーレジストが未硬化の箇所
を除去することにより作製される。このＵＶ硬化レジス
ト層３は、上記導体回路２の非半田接合面となる端部と
接して形成されている。上記ＵＶ硬化レジスト層３の外
面に形成される熱硬化レジスト層４は、例えば、熱硬化
型ソルダーレジストをスクリーン印刷し、加熱するとソ
ルダーレジストが硬化し、作製される。上記ソルダーレ
ジスト層５は、半田接合面６との境界であるＵＶ硬化レ
ジスト層３の境界縁３ａは露出するように、上記熱硬化
レジスト層４が形成されている。上記ＵＶ硬化レジスト
層３の境界縁３ａを露出するように、上記熱硬化レジス
ト層４が形成されているので、上記熱硬化型ソルダーレ
ジストは印刷の際に発生するにじみが、半田接合面６に
まで到達することがない。上記プリント配線板は雰囲気
に曝されるソルダーレジスト層５の外層が主に熱硬化レ
ジスト層３で形成されているので、半田処理後や高温高
湿保管後の密着性が良好である。In the printed wiring board, the solder joint surface 6 of the conductor circuit 2 to which the solder is attached is exposed and the non-solder joint surface of the insulating substrate 1 is covered with the solder resist layer 5. The layer structure of the solder resist layer 5 includes a UV-curable resist layer 3 in which an inner layer is a UV-curable solder resist cured, and an outer layer is a thermosetting resist layer 4 in which a thermosetting solder resist is cured. The UV curable resist layer 3 is
For example, when a UV-curable solder resist is applied on the insulating substrate 1 on which the conductor circuit 2 is formed and a dry film is used to expose a portion which becomes a non-solder joint surface, the solder resist is cured, and then the solder resist is not applied. It is produced by removing the cured part. The UV-curable resist layer 3 is formed in contact with the end of the conductor circuit 2 which is the non-solder joint surface. The thermosetting resist layer 4 formed on the outer surface of the UV-curing resist layer 3 is produced by screen-printing a thermosetting solder resist and curing the solder resist when heated. In the solder resist layer 5, the thermosetting resist layer 4 is formed so that the boundary edge 3a of the UV curing resist layer 3 which is the boundary with the solder joint surface 6 is exposed. Since the thermosetting resist layer 4 is formed so as to expose the boundary edge 3a of the UV curing resist layer 3, the thermosetting solder resist has bleeding that occurs during printing on the solder joint surface 6. Never reach. Since the outer layer of the solder resist layer 5 exposed to the atmosphere is mainly formed of the thermosetting resist layer 3 in the above-mentioned printed wiring board, the adhesion is good after the soldering process and the high temperature and high humidity storage.
【０００９】次に、本発明のプリント配線板の製造方法
について説明する。図２（ａ）に示す如く、上記絶縁基
板１の表面に導体回路２を形成した後に、図２（ｂ）に
示す如く、ＵＶ硬化型ソルダーレジストを用い、上記絶
縁基板１の非半田接合面にＵＶ硬化レジスト層３を形成
する。このＵＶ硬化レジスト層３は、上記導体回路２の
非半田接合面となる端部と接して形成される。上記ＵＶ
硬化レジスト層３の作製は、絶縁基板１の上にＵＶ硬化
型ソルダーレジストを厚み５〜１５μｍ程度で塗布し、
非半田接合面となる箇所を露光し、ソルダーレジストを
硬化させた後に、ソルダーレジストの未硬化の箇所を除
去する。露光条件等は公知のＵＶ硬化型ソルダーレジス
トを用いる条件で行えばよい。次に、図１に示す如く、
上記ＵＶ硬化レジスト層３の外面に熱硬化型ソルダーレ
ジストを塗布する。この際、熱硬化型ソルダーレジスト
はＵＶ硬化レジスト層３の境界縁３ａが露出するように
塗布する。上記熱硬化型ソルダーレジストの塗布は、例
えば、スクリーン印刷による。本発明の製造方法による
と、上記熱硬化型ソルダーレジストを塗布する際に、に
じみが生じても半田接合面６にまで到達することがな
い。その後、加熱しソルダーレジストを硬化すると、熱
硬化レジスト層４が形成される。Next, a method of manufacturing the printed wiring board of the present invention will be described. After forming the conductor circuit 2 on the surface of the insulating substrate 1 as shown in FIG. 2A, a non-solder joint surface of the insulating substrate 1 is formed by using a UV curable solder resist as shown in FIG. 2B. Then, a UV curable resist layer 3 is formed. The UV curable resist layer 3 is formed in contact with the end portion of the conductor circuit 2 which is a non-solder joint surface. UV above
The cured resist layer 3 is produced by applying a UV curable solder resist on the insulating substrate 1 to a thickness of about 5 to 15 μm,
After exposing the portion which becomes the non-solder joint surface and curing the solder resist, the uncured portion of the solder resist is removed. The exposure conditions and the like may be performed under the conditions using a known UV-curable solder resist. Next, as shown in FIG.
A thermosetting solder resist is applied to the outer surface of the UV curable resist layer 3. At this time, the thermosetting solder resist is applied so that the boundary edge 3a of the UV curing resist layer 3 is exposed. The thermosetting solder resist is applied by screen printing, for example. According to the manufacturing method of the present invention, when the thermosetting solder resist is applied, even if bleeding occurs, it does not reach the solder joint surface 6. After that, when the solder resist is heated and cured, the thermosetting resist layer 4 is formed.
【００１０】上述の如く、上記プリント配線板の製造方
法によって、半田接合面６と非半田接合面との境界はＵ
Ｖ硬化型ソルダーレジストを用いてＵＶ硬化レジスト層
３を形成するため、回路形成のファイン化を実現したプ
リント配線板が得られる。さらに、このＵＶ硬化レジス
ト層３の外面に熱硬化型ソルダーレジストを用いて熱硬
化レジスト層４を形成するので、熱硬化レジスト層４は
耐熱性、及び、耐湿性が優れるため、半田処理後や高温
高湿保管後の密着性が良好なプリント配線板が得られ
る。As described above, the boundary between the solder joint surface 6 and the non-solder joint surface is U according to the method for manufacturing the printed wiring board.
Since the UV-curable resist layer 3 is formed by using the V-curable solder resist, a printed wiring board that realizes fine circuit formation can be obtained. Further, since the thermosetting resist layer 4 is formed on the outer surface of the UV-curing resist layer 3 by using the thermosetting solder resist, the thermosetting resist layer 4 has excellent heat resistance and moisture resistance. A printed wiring board having good adhesion after storage at high temperature and high humidity can be obtained.
【００１１】[0011]
【作用】本発明の請求項１に係るプリント配線板におい
ては、上記ソルダーレジスト層５の層構成は、上記導体
回路２の非半田接合面となる端部と接する内層が、ＵＶ
硬化型ソルダーレジストが硬化したＵＶ硬化レジスト層
３と、その外層が熱硬化型ソルダーレジストが硬化した
熱硬化レジスト層４とからなるので、半田接合面６と非
半田接合面との境界となるソルダーレジスト層５はＵＶ
硬化型ソルダーレジストが硬化したＵＶ硬化レジスト層
３で形成されると共に、雰囲気に曝される熱硬化レジス
ト層３は耐熱性、及び、耐湿性が優れる。In the printed wiring board according to the first aspect of the present invention, in the layer structure of the solder resist layer 5, the inner layer contacting with the end portion of the conductor circuit 2 which is the non-solder joint surface is UV.
Since the UV curable resist layer 3 in which the curable solder resist is cured and the outer layer thereof is the thermosetting resist layer 4 in which the thermosetting solder resist is cured, the solder serving as the boundary between the solder joint surface 6 and the non-solder joint surface. The resist layer 5 is UV
While the curable solder resist is formed of the cured UV curable resist layer 3, the heat curable resist layer 3 exposed to the atmosphere has excellent heat resistance and moisture resistance.
【００１２】本発明の請求項２に係るプリント配線板の
製造方法においては、絶縁基板１の表面に導体回路２を
形成し、絶縁基板１の非半田接合面に、上記導体回路２
の端部に接してＵＶ硬化型ソルダーレジストを用い、Ｕ
Ｖ硬化レジスト層３を形成した後に、このＵＶ硬化レジ
スト層３の外面に熱硬化型ソルダーレジストを塗布し、
熱硬化レジスト層４を、ＵＶ硬化レジスト層３の境界縁
３ａが露出するように形成するので、半田接合面６と非
半田接合面との境界はＵＶ硬化型ソルダーレジストを用
いて被覆すると共に、ソルダーレジスト層３の外面に耐
熱性、及び、耐湿性が優れる熱硬化レジスト層４を形成
する。In the method of manufacturing a printed wiring board according to the second aspect of the present invention, the conductor circuit 2 is formed on the surface of the insulating substrate 1, and the conductor circuit 2 is formed on the non-solder joint surface of the insulating substrate 1.
U-type solder resist is used in contact with the end of
After forming the V-curable resist layer 3, a thermosetting solder resist is applied to the outer surface of the UV-curable resist layer 3,
Since the thermosetting resist layer 4 is formed so that the boundary edge 3a of the UV curing resist layer 3 is exposed, the boundary between the solder joint surface 6 and the non-solder joint surface is covered with a UV curable solder resist, and A thermosetting resist layer 4 having excellent heat resistance and moisture resistance is formed on the outer surface of the solder resist layer 3.
【００１３】[0013]
実施例１ 絶縁基板として、厚さ１．０ｍｍのガラス布基材変性ポ
リイミド樹脂積層板を用いた。この絶縁基板の表面に配
設した厚さ１８μｍの銅箔をエッチングし、回路幅０．
１２ｍｍの導体回路を作製した。ＵＶ硬化レジスト層は
次のように作製した。ＵＶ硬化型ソルダーレジスト（太
陽インク株式会社製：ＰＳＲ−４０００Ｚ２６）を導体
回路を形成した絶縁基板の全面に１０μｍの厚みで塗布
し、７０℃１５分乾燥した後に、ドライフィルムを用い
非半田接合面となる箇所を４００ｍｊ／ｃｍ2 の照度で
露光した。その後、１ｗｔ％のＮａＣＯ3 の水溶液に６
０秒浸漬し、未硬化のソルダーレジストを除去した後
に、１５０℃で３０分乾燥した。次に熱硬化レジスト層
は次のように作製した。熱硬化型ソルダーレジスト（株
式会社アサヒ化学研究所製：ＣＣＲ−２３２ＣＦＶ）を
用い、半田接合面６との境界であるＵＶ硬化レジスト層
３の境界縁３ａが露出するように、上記ＵＶ硬化レジス
ト層の上に１０μｍの厚みでスクリーン印刷した後に、
１３０℃１０分加熱した。上記方法によりプリント配線
板を得た。Example 1 A 1.0 mm thick glass cloth substrate-modified polyimide resin laminate was used as an insulating substrate. A copper foil having a thickness of 18 μm arranged on the surface of this insulating substrate is etched to obtain a circuit width of 0.
A 12 mm conductor circuit was produced. The UV curable resist layer was prepared as follows. A UV-curable solder resist (manufactured by Taiyo Ink Co., Ltd .: PSR-4000Z26) is applied to the entire surface of an insulating substrate on which a conductor circuit is formed in a thickness of 10 μm, dried at 70 ° C. for 15 minutes, and then a non-soldered surface using a dry film. The exposed area was exposed with an illuminance of 400 mj / cm 2 . Then, add 6% to a 1 wt% aqueous solution of NaCO 3.
After immersing for 0 seconds to remove the uncured solder resist, it was dried at 150 ° C. for 30 minutes. Next, a thermosetting resist layer was prepared as follows. Using a thermosetting solder resist (CCR-232CFV manufactured by Asahi Chemical Laboratory Co., Ltd.), the UV curable resist layer is exposed so that the boundary edge 3a of the UV curable resist layer 3 which is the boundary with the solder joint surface 6 is exposed. After screen printing with a thickness of 10 μm on the
Heated at 130 ° C. for 10 minutes. A printed wiring board was obtained by the above method.
【００１４】比較例１ ソルダーレジスト層としてＵＶ硬化レジスト層のみを形
成した。実施例１と同様に、絶縁基板に所望の導体回路
を作製し、ＵＶ硬化レジスト層を形成した。Comparative Example 1 Only a UV curable resist layer was formed as a solder resist layer. Similar to Example 1, a desired conductor circuit was prepared on an insulating substrate and a UV curable resist layer was formed.
【００１５】比較例２ ソルダーレジスト層として熱硬化レジスト層のみを形成
した。実施例１と同様に、絶縁基板に所望の導体回路を
作製し、熱硬化型ソルダーレジスト（株式会社アサヒ化
学研究所製：ＣＣＲ−２３２ＣＦＶ）を用い、非半田接
合面に１０μｍの厚みでスクリーン印刷した後に、１３
０℃１０分加熱し、熱硬化レジスト層を形成した。Comparative Example 2 Only a thermosetting resist layer was formed as a solder resist layer. Similar to Example 1, a desired conductor circuit was prepared on an insulating substrate, and a thermosetting solder resist (CCR-232CFV manufactured by Asahi Chemical Laboratory Co., Ltd.) was used to screen print on the non-solder joint surface with a thickness of 10 μm. After doing 13
It was heated at 0 ° C. for 10 minutes to form a thermosetting resist layer.
【００１６】実施例１、及び、比較例１〜２のプリント
配線板の半田処理後、及び、高温高湿保管後の密着性、
並びに、レジストのにじみを評価した。Adhesion of the printed wiring boards of Example 1 and Comparative Examples 1 and 2 after soldering and storage at high temperature and high humidity,
In addition, the bleeding of the resist was evaluated.
【００１７】上記半田処理後の密着性は、２６０℃の半
田に６０秒浸漬した後に、ＪＩＳ−Ｄ−０２０２の基盤
目付着性試験方法に基づいて、基盤目を作製し、テープ
を瞬時に剥がし、剥がれた基盤目数を検査した。基盤目
の５％以上剥がれたものは不合格（表示×）、５％未満
のものは合格（表示○）とした。The adhesion after the above soldering treatment was carried out by immersing the solder in a solder at 260 ° C. for 60 seconds, and then preparing a base mesh based on the base mesh adhesion test method of JIS-D-0202, and immediately peeling off the tape. The number of peeled substrates was inspected. Those with 5% or more peeled off of the substrate were judged to be unacceptable (indication x) and those less than 5% were judged to be acceptable (indication o).
【００１８】上記高温高湿保管後の密着性は、２気圧、
１２１℃、２００時間ＰＣＴ試験を行った後に、上述と
同様にＪＩＳ−Ｄ−０２０２の基盤目付着性試験方法に
基づいて、剥がれた基盤目数を検査した。基盤目の５％
以上剥がれたものは不合格（表示×）、５％未満のもの
は合格（表示○）とした。The adhesion after storage at high temperature and high humidity is 2 atm,
After the PCT test was performed at 121 ° C. for 200 hours, the number of peeled base stitches was inspected based on the base stitch adhesion test method of JIS-D-0202 as described above. 5% of base
Those peeled off as above were rejected (indication x), and less than 5% were acceptable (indication o).
【００１９】上記レジストのにじみは、拡大鏡を使用し
目視検査し、にじみの有無を調べた。にじみが有るもの
は不合格（表示×）、無きものは合格（表示○）とし
た。The bleeding of the resist was visually inspected with a magnifying glass to check for the bleeding. Those with bleeding were rejected (indication x), and those without bleeding were accepted (indication o).
【００２０】結果は表１に示すとおり、実施例１は半田
処理後、及び、高温高湿保管後の密着性、並びに、レジ
ストのにじみはいずれも合格であった。比較例１は密着
性がいずれも不合格であり、比較例２はレジストのにじ
みが不合格であった。The results are shown in Table 1. In Example 1, the adhesiveness after soldering and the storage after high temperature and high humidity, and the bleeding of the resist were all acceptable. In Comparative Example 1, the adhesiveness was unacceptable, and in Comparative Example 2, resist bleeding was unacceptable.
【００２１】[0021]
【表１】 [Table 1]
【００２２】[0022]
【発明の効果】本発明の請求項１に係るプリント配線板
は、半田処理後や高温高湿保管後の密着性が良好であ
る。上記プリント配線板は回路形成のファイン化に適す
る。EFFECTS OF THE INVENTION The printed wiring board according to the first aspect of the present invention has good adhesion after soldering and after storage at high temperature and high humidity. The printed wiring board is suitable for finer circuit formation.
【００２３】本発明の請求項２に係るプリント配線板の
製造方法によって、半田接合面６と非半田接合面との境
界はＵＶ硬化型ソルダーレジストを用いてＵＶ硬化レジ
スト層３を形成するため、回路形成のファイン化を実現
すると共に、このＵＶ硬化レジスト層３の外面に熱硬化
型ソルダーレジストを用いて熱硬化レジスト層４を形成
するので、熱硬化レジスト層４は耐熱性、及び、耐湿性
が優れるため、半田処理後や高温高湿保管後の密着性が
良好なプリント配線板を得ることができる。According to the method for manufacturing a printed wiring board according to the second aspect of the present invention, since the UV curable resist layer 3 is formed at the boundary between the solder joint surface 6 and the non-solder joint surface using the UV curable solder resist, Since the thermosetting resist layer 4 is formed on the outer surface of the UV-curing resist layer 3 by using a thermosetting solder resist, the thermosetting resist layer 4 has heat resistance and moisture resistance. Is excellent, it is possible to obtain a printed wiring board having good adhesion after soldering or storage at high temperature and high humidity.
【図１】本発明の一実施例に係るプリント配線板の要部
を拡大した断面図である。FIG. 1 is an enlarged cross-sectional view of a main part of a printed wiring board according to an embodiment of the present invention.
【図２】（ａ）、（ｂ）は本発明の一実施例に係るプリ
ント配線板の製造方法のステップを示す要部拡大断面図
である。2A and 2B are enlarged cross-sectional views of a main part showing steps of a method for manufacturing a printed wiring board according to an embodiment of the present invention.
１ 絶縁基板 ２ 導体回路 ３ ＵＶ硬化レジスト層 ３ａ 境界縁 ４ 熱硬化レジスト層 ５ ソルダーレジスト層 ６ 半田接合面 1 Insulating Substrate 2 Conductor Circuit 3 UV Curing Resist Layer 3a Border Edge 4 Thermosetting Resist Layer 5 Solder Resist Layer 6 Solder Joint Surface
Claims (2)
基板（１）の非半田接合面をソルダーレジスト層（５）
で被覆したプリント配線板であって、上記ソルダーレジ
スト層（５）の層構成は、上記導体回路（２）の非半田
接合面となる端部と接する内層が、ＵＶ硬化型ソルダー
レジストが硬化したＵＶ硬化レジスト層（３）と、その
外層が熱硬化型ソルダーレジストが硬化した熱硬化レジ
スト層（４）とからなり、且つ、上記ＵＶ硬化レジスト
層（３）の境界縁（３ａ）が露出していることを特徴と
するプリント配線板。1. A non-solder joint surface of an insulating substrate (1) having a conductor circuit (2) formed on a surface thereof is provided with a solder resist layer (5).
In the printed wiring board covered with, the solder resist layer (5) has a layer structure in which the inner layer in contact with the end portion which is the non-solder joint surface of the conductor circuit (2) is cured by the UV curable solder resist. The UV curable resist layer (3) and the outer layer thereof are a thermosetting resist layer (4) obtained by curing a thermosetting solder resist, and the boundary edge (3a) of the UV curing resist layer (3) is exposed. A printed wiring board characterized in that
を形成し、絶縁基板（１）の非半田接合面に、上記導体
回路（２）の端部に接してＵＶ硬化型ソルダーレジスト
を用い、ＵＶ硬化レジスト層（３）を形成した後に、こ
のＵＶ硬化レジスト層（３）の外面に熱硬化型ソルダー
レジストを塗布し、熱硬化レジスト層（４）を、ＵＶ硬
化レジスト層（３）の境界縁（３ａ）が露出するように
形成することを特徴とするプリント配線板の製造方法。2. A conductor circuit (2) on the surface of an insulating substrate (1).
Is formed, a UV-curable solder resist is used on the non-solder joint surface of the insulating substrate (1) in contact with the end of the conductor circuit (2), and a UV-curable resist layer (3) is formed. A thermosetting solder resist is applied to the outer surface of the cured resist layer (3), and the thermosetting resist layer (4) is formed so that the boundary edge (3a) of the UV curing resist layer (3) is exposed. And a method for manufacturing a printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1175895A JPH08204316A (en) | 1995-01-27 | 1995-01-27 | Printed wiring board and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1175895A JPH08204316A (en) | 1995-01-27 | 1995-01-27 | Printed wiring board and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08204316A true JPH08204316A (en) | 1996-08-09 |
Family
ID=11786890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1175895A Withdrawn JPH08204316A (en) | 1995-01-27 | 1995-01-27 | Printed wiring board and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08204316A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005332906A (en) * | 2004-05-19 | 2005-12-02 | Matsushita Electric Ind Co Ltd | Flexible printed wiring board and its manufacturing method |
| US7520755B2 (en) | 2005-10-31 | 2009-04-21 | Unimicron Technology Corp. | Method of forming solder mask and wiring board with solder mask |
| JP2011049476A (en) * | 2009-08-28 | 2011-03-10 | Taiyo Holdings Co Ltd | Solder resist layer and printed wiring board |
| JP2013038235A (en) * | 2011-08-08 | 2013-02-21 | Kaneka Corp | Novel flexible printed circuit board integrated with conductive layer |
| JP2013074027A (en) * | 2011-09-27 | 2013-04-22 | Sekisui Chem Co Ltd | Method for manufacturing electronic component |
| CN105228362A (en) * | 2014-06-30 | 2016-01-06 | 发那科株式会社 | Printed circuit board and manufacture method thereof |
-
1995
- 1995-01-27 JP JP1175895A patent/JPH08204316A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005332906A (en) * | 2004-05-19 | 2005-12-02 | Matsushita Electric Ind Co Ltd | Flexible printed wiring board and its manufacturing method |
| JP4622308B2 (en) * | 2004-05-19 | 2011-02-02 | パナソニック株式会社 | Flexible printed wiring board |
| US7520755B2 (en) | 2005-10-31 | 2009-04-21 | Unimicron Technology Corp. | Method of forming solder mask and wiring board with solder mask |
| JP2011049476A (en) * | 2009-08-28 | 2011-03-10 | Taiyo Holdings Co Ltd | Solder resist layer and printed wiring board |
| JP2013038235A (en) * | 2011-08-08 | 2013-02-21 | Kaneka Corp | Novel flexible printed circuit board integrated with conductive layer |
| JP2013074027A (en) * | 2011-09-27 | 2013-04-22 | Sekisui Chem Co Ltd | Method for manufacturing electronic component |
| CN105228362A (en) * | 2014-06-30 | 2016-01-06 | 发那科株式会社 | Printed circuit board and manufacture method thereof |
| JP2016012702A (en) * | 2014-06-30 | 2016-01-21 | ファナック株式会社 | Print circuit board balancing wettability and anticorrosion of solder coat and manufacturing method of the same |
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Legal Events
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020402 |