JPH08204129A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08204129A JPH08204129A JP7007173A JP717395A JPH08204129A JP H08204129 A JPH08204129 A JP H08204129A JP 7007173 A JP7007173 A JP 7007173A JP 717395 A JP717395 A JP 717395A JP H08204129 A JPH08204129 A JP H08204129A
- Authority
- JP
- Japan
- Prior art keywords
- laser trimming
- trimming step
- silicon substrate
- type well
- damage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Laser Beam Processing (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本願は、半導体装置、特にレーザ
トリミング用配線層を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring layer for laser trimming.
【0002】[0002]
【従来の技術】従来、レーザトリミング用配線層を設け
たICでは、シリコン基板上に絶縁層を設け、この絶縁
層上にレーザトリミング用配線層を設けていた。2. Description of the Related Art Conventionally, in an IC provided with a wiring layer for laser trimming, an insulating layer is provided on a silicon substrate, and a wiring layer for laser trimming is provided on this insulating layer.
【0003】[0003]
【発明が解決しようとする課題】一般的に、レーザトリ
ミング用配線層をレーザで切断する場合、その影響がシ
リコン基板にまで及ぶため、シリコン基板がダメージを
受ける。従来はレーザトリミング用配線層下部のシリコ
ン基板に何ら対策がほどこされていなかったため、レー
ザトリミングの際に受けたダメージが徐々にシリコン基
板の周囲に拡がり、ICの特性や信頼性に悪影響を及ぼ
すという問題点があった。Generally, when the laser trimming wiring layer is cut by a laser, the influence extends to the silicon substrate, so that the silicon substrate is damaged. Conventionally, no measures have been taken on the silicon substrate under the laser trimming wiring layer, so damage received during laser trimming gradually spreads around the silicon substrate, which adversely affects the characteristics and reliability of the IC. There was a problem.
【0004】本願に係わる発明の目的は、レーザトリミ
ングの際に受けたダメージの影響を低減することが可能
な半導体装置を提供することである。An object of the present invention is to provide a semiconductor device capable of reducing the effect of damage received during laser trimming.
【0005】[0005]
【課題を解決するための手段】本願に係わる半導体装置
は、シリコン基板の導電型と反対の導電型のウエルと、
上記ウエル上に形成された絶縁層と、上記絶縁層上に形
成されたレーザトリミング用配線層とを有する。A semiconductor device according to the present invention comprises a well of a conductivity type opposite to that of a silicon substrate,
It has an insulating layer formed on the well and a laser trimming wiring layer formed on the insulating layer.
【0006】[0006]
【実施例】図1は、実施例を示した図である。N型シリ
コン基板11上の所定の領域にはLOCOS構造の酸化
シリコン層13が形成されており、この酸化シリコン層
13下にP型ウエル12が形成されている。P型ウエル
12はCMOSのウエル製造工程で形成され、ウエルの
深さや不純物濃度等は通常のCMOSICに用いられる
ものと同様である。P型ウエル12上にはレーザトリミ
ング用配線層14(金属配線)が形成されている。な
お、図示しない領域にはMOSトランジスタや各種配線
等が形成されている。EXAMPLE FIG. 1 is a diagram showing an example. A silicon oxide layer 13 having a LOCOS structure is formed in a predetermined region on the N-type silicon substrate 11, and a P-type well 12 is formed under the silicon oxide layer 13. The P-type well 12 is formed in a CMOS well manufacturing process, and the well depth and the impurity concentration are the same as those used in a normal CMOS IC. A laser trimming wiring layer 14 (metal wiring) is formed on the P-type well 12. It should be noted that MOS transistors, various wirings, and the like are formed in a region (not shown).
【0007】トリミングはレーザトリミング用配線層1
4をレーザで切断することにより行われるが、レーザト
リミングの際のシリコン基板11へのダメージはP型ウ
エル12内に抑えることができる。また、P型ウエル1
2内で生じたダメージがP型ウエル12外へと拡がるこ
とを防止することができる。The trimming is performed by the wiring layer 1 for laser trimming.
This is done by cutting 4 with a laser, but damage to the silicon substrate 11 during laser trimming can be suppressed within the P-type well 12. Also, P-type well 1
It is possible to prevent the damage generated inside 2 from spreading outside the P-type well 12.
【0008】以上のように、本実施例では酸化シリコン
層13下にP型ウエル12を設けたので、レーザトリミ
ングの際に受けたダメージの影響を低減することが可能
となる。したがって、予めレーザトリミング用配線層1
4を形成しておき、必要に応じてこのレーザトリミング
用配線層14を切断するという構成を、ICの特性や信
頼性の低下なしに実現させることができる。As described above, since the P-type well 12 is provided under the silicon oxide layer 13 in this embodiment, it is possible to reduce the influence of damage received during laser trimming. Therefore, the wiring layer 1 for laser trimming is previously prepared.
4 can be formed and the laser trimming wiring layer 14 can be cut as needed without any deterioration in the characteristics or reliability of the IC.
【0009】なお、上記実施例ではN型シリコン基板お
よびP型ウエルを用いたが、これとは逆にP型シリコン
基板およびN型ウエルを用いてもよい。Although the N-type silicon substrate and the P-type well are used in the above embodiment, the P-type silicon substrate and the N-type well may be used in reverse.
【0010】[0010]
【発明の効果】本願に係わる発明では、絶縁層下にウエ
ルを設けたので、レーザトリミングの際に受けたダメー
ジの影響を低減することが可能となり、ICの特性や信
頼性の低下を防止することが可能となる。According to the invention of the present application, since the well is provided under the insulating layer, it is possible to reduce the influence of damage received during laser trimming, and prevent deterioration of IC characteristics and reliability. It becomes possible.
【図1】本願に係わる発明の実施例を示した図である。FIG. 1 is a diagram showing an embodiment of the invention according to the present application.
11……シリコン基板 12……P型ウエル 13……酸化シリコン層(絶縁層) 14……レーザトリミング用配線層 11 ... Silicon substrate 12 ... P-type well 13 ... Silicon oxide layer (insulating layer) 14 ... Laser trimming wiring layer
Claims (1)
ウエルと、 上記ウエル上に形成された絶縁層と、 上記絶縁層上に形成されたレーザトリミング用配線層と
を有する半導体装置。1. A semiconductor device having a well of a conductivity type opposite to that of a silicon substrate, an insulating layer formed on the well, and a laser trimming wiring layer formed on the insulating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7007173A JPH08204129A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7007173A JPH08204129A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08204129A true JPH08204129A (en) | 1996-08-09 |
Family
ID=11658697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7007173A Pending JPH08204129A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08204129A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6373120B1 (en) | 1998-02-12 | 2002-04-16 | Nec Corporation | Semiconductor device for simultaneously achieving high reliability to laser light radiation and small occupation region and method of manufacturing it |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
-
1995
- 1995-01-20 JP JP7007173A patent/JPH08204129A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6373120B1 (en) | 1998-02-12 | 2002-04-16 | Nec Corporation | Semiconductor device for simultaneously achieving high reliability to laser light radiation and small occupation region and method of manufacturing it |
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