KR19990048298A - How to prevent overlapping etching of semiconductor devices - Google Patents

Abstract

The present invention relates to a method for preventing overlapping etching of a semiconductor device. According to the present invention, an etch stop layer is formed on the etch boundary region of the semiconductor device to prevent overlapping etch. As a result, the etching of the device isolation film or the silicide film existing in the etching boundary region is prevented.

Description

How to prevent overlapping etching of semiconductor devices

The present invention relates to a method for preventing overlapping etching of a semiconductor device, and more particularly, to a method for preventing damage to an underlying layer by overlapping etching in an etching boundary region of a semiconductor device.

In semiconductor devices, in general, an oxide film is partially etched or an ion is partially implanted in a spacer manufacturing process of an NMOS transistor or a PMOS transistor or a twin-well process for manufacturing a CMOS transistor. In order to perform such a partial process, it is a very common flow to perform the partial process around the boundary area.

Conventionally, in performing the above etching process or ion implantation process, the process can be carried out with a sufficient margin so that no misalignment margin occurs, but this has not been possible at present. For example, in the twin well process, the enwell region and the pewell region are separated by an isolation layer, and each process is performed. However, in the device isolation layer which is the boundary between the enwell region and the pewell region, the same process is performed twice during each process due to misalignment margin. As a result, the device isolation layer may be repeatedly etched to generate a fitting. In addition, when the silicide layer is formed, the silicide may be exposed due to the overlapping etching of the interlayer insulating layer on the upper portion of the silicide layer, which may cause a defect of the semiconductor device and lower the yield.

Therefore, in the current semiconductor device manufacturing field that has achieved high integration after the high integration age, it is a very important task to prevent the overlapping etching of the boundary region due to misalignment margin.

Accordingly, an object of the present invention is to provide a method for preventing overlapping etching of a boundary region having a sufficient process margin even in a highly integrated semiconductor device.

In order to achieve the above objects, the present invention provides a method for forming an etch stop layer on the etch boundary region of the semiconductor device in a method for preventing overlapping etching of the etch boundary region of the semiconductor device. .

1A is a cross-sectional view illustrating a method of preventing overlapping etching of a semiconductor device according to a first embodiment of the present invention.

FIG. 1B is a cross-sectional view illustrating a result of overlapping etching of the boundary area “A” of FIG. 1A.

2A is a cross-sectional view illustrating a method of preventing overlapping etching of a semiconductor device according to a second exemplary embodiment of the present invention.

FIG. 2B is a cross-sectional view illustrating a result of overlapping etching of the boundary area “B” of FIG. 2A.

3A is a cross-sectional view illustrating a method of preventing overlapping etching of a semiconductor device according to a third exemplary embodiment of the present invention.

FIG. 3B is a cross-sectional view illustrating a result of overlapping etching of the boundary region “C” of FIG. 3A.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a cross-sectional view of an etch stop layer 20 formed in the etch boundary region “A” to prevent overlapping etching in the etch boundary region “A” of the semiconductor device according to the first embodiment of the present invention. Referring to the drawing, an isolation layer 12 is formed on a semiconductor substrate 10. Then, after forming the enwell 14 and the pewell 16, the gate electrode 18 is formed. The area "A" where the enwells 14 and the pewells 16 meet is an etch boundary area, in which the processes of the enwells 14 and the pewells 16 are performed twice. Therefore, in the present invention, an etch stop layer 20 is formed on the device isolation layer 12 of the etch boundary region “A” to prevent the etch boundary region “A” from being etched repeatedly. The etch stop layer 20 may be formed of polysilicon, a nitride layer, etc. having an etching selectivity with the insulating layer 22. After the insulating film 22 is formed on the semiconductor substrate 10 on which the etch stop layer 20 is formed, the process is performed on the enwell 14 and the pewell 16, respectively.

FIG. 1B illustrates a result of overlapping etching of the boundary area “A” of FIG. 1A. Etching processes are respectively performed on the enwell 14 and the pewell 16 around the etching boundary region “A”. In this process, even if two etching processes are performed on the device isolation layer 12 of the etching boundary region “A”, the device isolation region 12 may be prevented from being etched due to the etch stop layer 20.

FIG. 2A illustrates a cross-sectional view of an etching preventing layer 20 formed in the etching boundary region “B” as a method for preventing overlapping etching in the etching boundary region “B” of the semiconductor device according to the second exemplary embodiment of the inventive concept. Referring to the drawings, referring to the drawings, an isolation layer 102 is formed on a semiconductor substrate 100. Then, after forming the enwell 104 and the pewell 106, the gate electrode 108 is formed, and then the insulating film 110 is formed. The region "B" where the enwells 104 and the pewell 106 meet is an etch boundary region where the processes performed on the enwells 104 and the pewell 106 are performed twice. Therefore, in the present invention, an etch stop layer 112 is formed on the insulating layer 110 formed on the device isolation layer 102 of the etch boundary region “B” to prevent the etch boundary region “B” from overlapping. The etch stop layer 20 may be formed of polysilicon, a nitride layer, etc. having an etching selectivity with the insulating layer 22.

FIG. 2B illustrates a result of performing overlap etching on the boundary area “B” of FIG. 2A. The etching process is performed on the enwell 104 and the pewell 106 with respect to the etching boundary region “B”. In this process, even if two etching processes are performed on the device isolation layer 12 of the etching boundary region “A”, the device isolation region 102 is prevented from being etched by the etching preventing layer 112.

3A illustrates a method for preventing overlapping etching in an etching boundary region “C” of a semiconductor device according to a third embodiment of the present invention. Referring to the drawing, an isolation layer 202 is formed on a semiconductor substrate 200. Then, the enwell 204 and the pewell 206 are formed, and then the silicide film 208 is formed. Subsequently, after the interlayer insulating layer 210 is formed on the silicide layer 208, the etching boundary region “C” between the enwell 204 and the pewell 206 is a region where the processes of the enwell 204 and the pewell 206 are performed twice. Accordingly, in the present invention, an etch stop layer 212 is formed in the etch boundary region “C” to prevent the silicide layer 208 and the device isolation layer 202 from being etched. The etch stop layer 212 may prevent overlapping of the silicide 208 of the etch boundary region “C” and the device isolation layer 202. The etch stop layer 212 may be formed of, for example, polysilicon or a nitride layer having an etching selectivity with the interlayer insulating layer 210.

FIG. 3B illustrates a result of overlapping etching of the boundary region “C” of FIG. 3A. Etching processes are respectively performed on the enwell 204 and the pewell 206 around the etch boundary region “C”. In this process, the silicide 208 and the isolation layer 202 of the etching boundary region “C” are etched twice. However, even in such overlapping etching, the silicide 208 and the device isolation layer 202 of the etch boundary region “C” are not etched due to the etch stop layer 212.

As described above, according to the present invention, by forming an etch stop layer in the etch boundary region overlapping the etching process has the effect of preventing the etching of the device isolation layer or the silicide layer present in the etch boundary region.

Although described with reference to the preferred embodiment of the present invention as described above, it will be understood that various modifications and changes can be made without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims (2)

In the method for preventing overlapping etching of the etching boundary region of the semiconductor device, Forming an overlapping etch stop layer over the etch boundary region of the semiconductor device. The method of claim 1, wherein the overlapping etching prevention layer is formed of a material having an etching selectivity with a material film that is the target of the overlapping etching prevention.