JPH08197771A - Thermal head driving device - Google Patents

Abstract

PURPOSE: To provide a thermal head driving device capable of achieving the shortening of a printing data forming time and the contraction of a circuit scale even in the thermal head equipped with a plurality of inputs of a sublimation type printer printing multi-gradation image data. CONSTITUTION: The thermal head driving device equipped with a plurality of heating resistor elements of a thermal transfer printer has a density flag address forming means 3, a printing element address count means 8, a memory means 16, a flag data forming means 17, a first selection means 9, a second selection means 13 and a timing control means 15 and the predetermined bit of the density flag bit of the density flag address corresponding to printing density is reversed to control printing density.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head driving device for a printer device, and more particularly to a thermal head driving device for controlling gradation of a sublimation printer device.

[0002]

2. Description of the Related Art Conventionally, a thermal head drive device of this type is disclosed in, for example, the invention of a thermal head drive device disclosed in Japanese Patent Laid-Open No. 3-95772.
In a printer device such as a video printer device that is equipped with a thermal head and configured to print multi-gradation images, the purpose is to reduce the number of data items to be transferred to the thermal head and to speed up data transfer. I was there.

FIG. 4 is a block diagram showing a conventional thermal head driving device. In FIG. 4, the image memory 101 holds the quantized image data, and the image data decoding circuit 102 converts the image data read from the image memory 101 into ON / OFF data (hereinafter, referred to as ON / OFF data of a resistor of the thermal head 107). Described as a print pattern). The data rearrangement circuit 103 outputs the print pattern output from the decoding circuit 102 to the thermal head 1.
It is rearranged in the order of transfer to 07. The RAM 104 writes and reads the rearranged print patterns.

First control signal generation circuit 105A
Performs read control of the image memory 101, write control of the image data decoding circuit 102, the data rearrangement circuit 103, and the RAM 104.

Second control signal generation circuit 105B
Is a control for reading the print pattern from the RAM 104,
Transfer control of data transfer circuit 106, thermal head 10
7 is controlled.

Here, for example, when the image data 1 dot in the image memory 101 is 6 bits / 1 byte, the RAM 104 configuration is 8 bits / 1 byte, and the number of dots of the thermal head 107 is 640 dots, the image memory 10 is first.
The image data from 1 is read for 8 dots in the transfer order of the thermal head 107, and after being decoded into a print pattern in the decoding circuit 102, it is input to the data rearrangement circuit 103 and stored in the RAM 104 as a structure of 8 dots / 1 byte. Write.

By performing this for 640 dots, all print patterns are written in the RAM 104. These operations are controlled by the control signal of the first control signal generation circuit 105A.

Next, when the data of 640 dots is transferred to the thermal head 107 via the data transfer circuit 106, the data of 640 dots rearranged in the transfer order,
That is, by reading 80 bytes of data from the RAM 104 and transferring it to the thermal head 107,
It is possible to obtain a desired print image.

[0009]

However, in the above-mentioned conventional thermal head driving device, since the input image data is decoded by the image data decoding circuit 102 into a predetermined printing pattern according to the density, the number of gradations is reduced. When the size becomes large, there is a problem that the number of times of data transfer increases, the data generation time becomes long, and it takes time to output a print.

Further, in order to read out and rearrange the data from the image memory 101, a control signal generating circuit is required in addition to the printing control, and the number of control signal generating circuits becomes two, which complicates the circuit configuration. There is a problem.

In view of such a point, the present invention shortens the print data generation time and reduces the circuit scale even in a thermal head having a plurality of inputs of a sublimation printer for printing multi-gradation image data. It is an object of the present invention to provide a thermal head drive device capable of achieving high efficiency.

[0012]

In order to achieve the above object, the thermal head driving device of the present invention is a thermal head driving device of a thermal transfer type printer device having a plurality of heat generating resistance elements, and Density flag address generating means for counting and generating a density flag address corresponding to the print density, and printing element address counting means for outputting the respective printing element addresses of the plurality of inputs of a thermal head having a plurality of inputs. Storage means for storing the density flag data at a memory address specified by the density flag address and the printing element address, and flag data for shifting the density flag data read from the storage means to the next density flag address. The memory address given to the generation means and the storage means is set to the print data. First selecting means for switching between the time of generating the print data and the time of writing the print data, and second selecting means for switching the density flag data given to the storage means between the time of generating the print data and the time of writing the print data. Access to the storage means, and the first and second
And a timing control means for controlling the switching of the selection means and the timing of the transfer data generation to the thermal head.

The thermal head driving device of the present invention is
A predetermined bit of the density flag bit included in the density flag address corresponding to the print density is inverted to control the print density.

[0014]

In the thermal head driving device of the present invention configured as described above, the print density can be controlled by only inverting the density flag bit of the density flag address corresponding to the print density by 1 bit. The time for writing transfer data for control in the buffer memory can be shortened, and the print data generation time can be shortened even in a thermal head having a plurality of inputs of a sublimation printer that prints multi-gradation image data. And the circuit scale can be reduced.

Further, since the print density is assigned as the address of the memory, even when the number of heat generating resistance elements of the thermal head is different, it can be applied only by changing the configuration of the memory.

Further, if the (n + 1) data shift write cycle is not activated, the density flag data stored in the buffer memory can be output as it is. Therefore, by writing the pattern to be energized by the CPU, as in the conventional case. It is also possible to transfer various print patterns.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a thermal head driving device of the present invention. FIG. 2 is a diagram showing the configuration of the buffer memory in this embodiment. FIG.
FIG. 7 is a diagram showing a data control timing waveform in the present embodiment.

First, the configuration of this embodiment will be described with reference to FIG. The thermal head drive device shown in FIG.
A density flag address generator 3, an adder 7, a dot address counter 8, a selector 9, a selector 13,
It has a configuration including a buffer memory 16, a flag data generation unit 17, a timing control unit 15, a data latch 22, and a thermal head 24.

In FIG. 1, a density flag address generator 3 receives a data latch clock (hereinafter referred to as HLTCK) 1 and outputs from the transfer counter 4 and the transfer counter 4 which counts the number of latches representing the print density. The adder 5 for adding "1" to the address to be stored, the output of the transfer counter 4 and the output of the adder 5 are input and selected at the timing of the data transfer clock (hereinafter referred to as HCK) 2, and the density flag Selector 6 for generating address
It is configured to have and.

The dot address counter 8 inputs HCK2 and transfers the number of data transferred between the latches (thermal head 2
The number of data corresponding to one input of 4) is counted, and the dot address in each input data of the thermal head 24 is generated.

The adder 7 includes a density flag address generator 3
The density flag address output from the dot address counter 8 and the dot address output from the dot address counter 8 are added to generate the read address of the buffer memory 16.

The selector 9 inputs the read address output from the adder 7 and the CPU address 10 at the time of writing the print data, and selects it according to the timing of the output signal of the timing control unit 15 to generate the memory address 11. The print data is represented by the density flag address of the corresponding dot address, and the density flag bit corresponding to the input data is set.

The selector 13 inputs the CPU data 14 and the output of the flag data generator 17 at the time of writing the print data and selects the timing data from the timing controller 15 to generate the density flag data 12.

The buffer memory 16 has a memory address of 1
1 is input as an address, the density flag data 12 is input as data, the control signal output from the timing control unit 15 is input as a read signal and a write signal, and the density flag data 21 for printing energization control is output. .

The flag data generation unit 17 latches the density flag data 21 read from the buffer memory 16, and clears and shifts the density flag data 21 to shorten the generation time of the density flag data 21. The configuration has an OR gate 18 and an AND gate 19 for writing.

The data latch 22 is the buffer memory 16
The density flag data 21 read from is latched to generate energization data 23 and output to the thermal head 24.

The timing controller 15 switches between the selector 9 and the selector 13 according to the writing of the density flag data 12 and the reading of the density flag data 21, and controls the read operation and the write operation of the buffer memory 16.

Next, the operation of the configuration of this embodiment shown in FIG. 1 will be described with reference to FIGS.

Generally, in a sublimation printer, the transfer amount of ink is transferred to a thermal head having a plurality of heating resistance elements by transferring control data indicating ON / OFF of energization to the same heating resistance element a plurality of times. To control the gradation. Therefore, when the number of heat generating resistance elements of the thermal head increases, the amount of transfer data also increases, resulting in a problem of increasing the data transfer time.
In order to solve this problem, the heating resistance element of the thermal head is divided into a plurality of blocks, and the data of each block is transferred in parallel to shorten the data transfer time.

Here, assuming that the number of heat generating resistance elements of the thermal head 24 is 128 for one input and eight input lines, the number is 1024 dots. If 256 gradations are controlled for this, as shown in FIG. 3, the printing of one line is divided into 256 energized portions, that is, 256 latches. A desired printing gradation can be obtained by performing energization any number of times during the 256 energization periods.

In the thermal head 24, the transfer data input from each input line is stored in an internal shift register in synchronization with HCK2, and the HLTCK1 aligns the energization control data of all the heating resistance elements and energizes as print data. To do. Therefore, in each latch cycle, HCK2 (128 clocks in FIG. 3) corresponding to the number of heating resistors of one input becomes one data transfer time, that is, the latch cycle.

As shown in FIG. 3, assuming that the gradation of the dot a is n in this embodiment, the timing controller 15 first sets the selector 9 and the selector 13 to the CPU address 10 and the CPU data when generating the print data. 14
Connect to. As a result, in the buffer memory 16,
The CPU address 10 is input as the memory address 11, and the CPU data 14 is input as the density flag data 12.

As shown in FIG. 2, in the buffer memory 16, the lower address of the memory address 11 is assigned to the density flag address generated by the density flag address generator 3, and the upper address is the dot generated by the dot address counter 8. Addresses are assigned to the addresses, and the width direction of the memory is input to the thermal head 24.

Therefore, the buffer memory 16 has a form in which the density flag data 21 for controlling the energization of each heating resistance element is arranged for each head input, and the capacity is 8 input lines of the thermal head and each input has a capacity. The number of heating resistor elements is 1
In the case of 28 elements, as shown in the following equation (1),

(Number of input lines) × (Number of input elements) × (Density flag address) (1) Therefore, in this embodiment, as shown in the following equation (2),

(8 lines) × (128 elements) × (256 gradations) (2) is the capacity of the buffer memory 16.

When the print data is generated, the CPU (not shown)
By setting the density flag bit of the buffer memory 16, the printing density of each printing dot is controlled. In other words, if the density of the dot a is n in 256 gradations, the density flag bit of the corresponding dot address (the data bit whose density flag address is n in this embodiment) is set to "0". At this time, the other density flag bits remain "1" as in the density flag data shown in FIG.
In the density flag data corresponding to one dot address, "0" is stored in only one position among the density flag addresses 0 to 255. Similarly, for other heating resistance elements, the CPU sets the density flag bit corresponding to each print density to determine the print density.

When the writing of data is completed, as shown in FIG. 3, print permission (hereinafter referred to as PCEN)
Drive the signal to enter the print cycle. When entering the print cycle, the timing control unit 15 causes the selector 9
And the selector 13 to switch the buffer memory 16
The memory address 11 is connected to the read address output from the adder 7, and the density flag data 12 is connected to the output of the flag data generator 17.

In the print cycle, the data of the same density flag address for all the heating resistance elements is read from the buffer memory 16 to control the energization. In the first energization, the transfer counter 4 that counts HLTCK1 is "0", which indicates the lowest of the density flag addresses of the buffer memory 16. Dot address counter 8
Counts up the density flag address in synchronization with HCK2 to generate as many addresses as the number of heating resistance elements at each input of the thermal head 24.

In the dot a shown in FIG. 3, since the density flag data written in the density flag address "0" is "1", "1" is read from the buffer memory 16 in the (n) data read cycle of the first half of HCK2. Is read out and stored in the data latch 22 and the data latch 20. The thermal head 24 has a data latch 2
The density flag data 21 stored in No. 2 is the energization data 23.
The dot a is energized to "1", that is, energization is turned on. At this time, selector 6
Is controlled by HCK2, and the output of the transfer counter 4 as it is on the address (n) side is selected as it is.

In the flag data generator 17, the HCK2 and the output of the data latch 20 are gated by the OR gate 18, and "1" is always output in the first half of the HCK2. Therefore, the timing control unit 15 writes the data “1” by driving the write cycle to the same density flag address after the read cycle of the density flag data. That is, the (n) data clear cycle after reading is performed.

In the latter half of HCK2, the selector 6 is switched and the address (n + 1) output by the adder 5 is output as the density flag address. That is, HCK
The address next to the density flag address of the address (n) read in the first half of 2 is selected, the (n + 1) data read cycle is performed, and the data is read from the buffer memory 16. The read density flag data and the density flag data of the density flag address (n) stored in the data latch 20 in the (n) data read cycle are AND gate 1
It is gated at 9 and stored in the data latch 20. The stored output data of the AND gate 19 is stored in the buffer memory 16 in the (n + 1) data shift write cycle.
Is written back to the density flag address (n + 1).

That is, the density flag data 21 at an address adjacent to the read density flag data is gated with the original density flag data, and if either of them has a flag, the density flag data is set to the next address. Shift light. When such an operation is performed in each latch cycle, since the density flag data “0” is written in the density flag address (n) in the dot a, the density flag read at the density flag address (n). The data "0" is gated with the density flag data "1" read in the (n + 1) data shift write cycle and written back as the density flag data "0". For this reason, the density flag data read thereafter becomes "0", and energization is not permitted when the density flag address is (n) or higher.

As described above, since the energization of each heating resistance element is controlled in the latch after the density flag bit written in the density flag address becomes "0", the gradation of the desired print is (n). Is determined as

In this way, C for performing printing data writing
Since the PU can control the print density by only inverting the density flag bit of the density flag address corresponding to the print density by 1 bit, the transfer data can be reduced as compared with the conventional control method. Further, by assigning the print density as an address of the memory, even when the number of heat generating resistance elements of the thermal head is different, it can be applied only by changing the configuration of the memory. Furthermore, (n +
1) If the data shift write cycle is not activated, the density flag data 21 stored in the buffer memory 16 can be output as it is. Therefore, by writing the pattern to be energized by the CPU, a conventional printing pattern can be obtained. You can also transfer.

Although the above-described embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, in the present embodiment, the heat generating resistance element of the thermal head 24 is 1024 dots with 128 elements for one input and eight input lines, but the present invention is not limited to this. By configuring the buffer memory 16 according to the number of elements,
It can be applied to various thermal heads. Also,
Although the control of the print density is 256 gradation control, it is not limited to this. Further, although the density flag data for controlling the printing is set to "0", the power-off state is set.
And "1" may be replaced with each other to set the ON state of energization.

[0048]

As is clear from the above description, the thermal head driving apparatus of the present invention can control the print density by only inverting the density flag bit of the density flag address corresponding to the print density by one bit. Also, it is possible to shorten the time for writing the transfer data for energization control in the buffer memory, and the print data generation time for the thermal head with multiple inputs of the sublimation type printer that prints multi-gradation image data. And the circuit scale can be reduced.

Further, by allocating the print density as the memory address, there is an effect that even when the number of heat generating resistance elements of the thermal head is different, the application can be made only by changing the configuration of the memory.

Further, if the (n + 1) data shift write cycle is not activated, the density flag data stored in the buffer memory can be output as it is, so that the CPU writes the pattern to be energized and the conventional printing pattern is obtained. Has the effect that it can also be transferred.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a thermal head driving device of the present invention.

FIG. 2 is a diagram showing a configuration of a buffer memory in this embodiment.

FIG. 3 is a diagram showing a timing waveform of data control in the present embodiment.

FIG. 4 is a block diagram showing a thermal head drive device in a conventional example.

[Explanation of symbols]

 1 Data Latch Clock (HLTCK) 2 Data Transfer Clock (HCK) 3 Density Flag Address Generation Unit 4 Transfer Counter 5, 7 Adder 6, 9, 13 Selector 8 Dot Address Counter 10 CPU Address 11 Memory Address 12, 21 Density Flag Data 14 CPU data 15 Timing control unit 16 Buffer memory 17 Flag data generation unit 18 OR gate 19 AND gate 20, 22 Data latch 23 Energization data 24 Thermal head 101 Image memory 102 Image data decoding circuit 103 Data rearranging circuit 104 RAM 105A 1st Control signal generating circuit 105B Second control signal generating circuit 106 Data transfer circuit 107 Thermal head

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Claims (2)

[Claims] 1. A density flag address generating means for counting the number of times of data transfer and generating a density flag address corresponding to a print density in a thermal head driving device of a thermal transfer printer device having a plurality of heating resistance elements, Printing element address counting means for outputting the printing element address of each of the plurality of inputs of a thermal head having a plurality of inputs; and density flag data at a memory address specified by the density flag address and the printing element address. Storage means for storing the concentration flag data read from the storage means,
Flag data generating means for shifting to the next density flag address; first selecting means for switching the memory address given to the storing means between generation of print data and writing of print data; and the density given to the storage means. Second selection means for switching flag data between the time when the print data is generated and the time when the print data is written, access to the storage means, switching between the first and second selection means, and the thermal head. And a timing control means for controlling the timing of transfer data generation of the thermal head driving device. 2. The thermal head drive device according to claim 1, wherein the print density is controlled by inverting a predetermined bit of a density flag bit included in the density flag address corresponding to the print density.