JPH08195488A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08195488A JPH08195488A JP459395A JP459395A JPH08195488A JP H08195488 A JPH08195488 A JP H08195488A JP 459395 A JP459395 A JP 459395A JP 459395 A JP459395 A JP 459395A JP H08195488 A JPH08195488 A JP H08195488A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- insulating film
- film
- region
- withstand voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Thyristors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、プレーナ型の耐圧構
造を有し、気密封止型パッケージに半導体チップを内蔵
した構造の素子で、主として車両駆動用に用いられる半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which has a planar withstand voltage structure and has a semiconductor chip built in a hermetically sealed package and is mainly used for driving a vehicle.
【０００２】[0002]
【従来の技術】絶縁ゲート形バイポーラトランジスタ
（ＩＧＢＴ）などのプレーナ型の半導体素子（以下プレ
ーナ素子と呼ぶ）ではその耐圧構造はガードリングやフ
ィールドプレートなどのプレーナ構造となっている。こ
の構造はメサ型半導体素子（以下メサ型素子と呼ぶ）と
異なり、通電する活性領域の表面と同一表面に耐圧構造
を作り込むことができ、メサ型素子の耐圧構造であるベ
ベル加工や表面処理などによる重金属汚染や機械加工歪
み等が入らずにクリーンな状態で耐圧構造を活性領域の
作り込みとほぼ同一の工程で形成できるメリットがあ
る。一方、気密封止型パッケージとしてはメサ型素子で
ある大電力用サイリスタなどで採用されているセラミッ
クケースがよく知られており、プレーナ素子のモジュー
ル構造などのパッケージで用いられるゲル等の封止材は
使わず、窒素ガス等の不活性ガスでパッケージ内を充満
させ、サイリスタのメサ型の耐圧構造部をシリコーンゴ
ムなどの表面保護膜を被覆させ耐圧構造部での放電を防
止し、長時間に亘って耐圧特性を安定に確保している。2. Description of the Related Art In a planar type semiconductor device (hereinafter referred to as a planar device) such as an insulated gate bipolar transistor (IGBT), its breakdown voltage structure is a planar structure such as a guard ring or a field plate. This structure is different from a mesa type semiconductor device (hereinafter referred to as a mesa type device), and a withstand voltage structure can be formed on the same surface as the surface of the active region to which current is applied. There is a merit that the breakdown voltage structure can be formed in almost the same process as the formation of the active region in a clean state without introducing heavy metal contamination or mechanical processing distortion due to the above. On the other hand, as a hermetically sealed package, a ceramic case adopted in a high power thyristor, which is a mesa type element, is well known, and a sealing material such as gel used in a package such as a module structure of a planar element. The inside of the package is filled with an inert gas such as nitrogen gas, and the mesa-type pressure-resistant structure of the thyristor is covered with a surface protective film such as silicone rubber to prevent discharge at the pressure-resistant structure for a long time. Stable pressure resistance characteristics are secured throughout.
【０００３】[0003]
【発明が解決しようとする課題】しかし２０００Ｖ以上
の高耐圧プレーナ素子チップをセラミック等の気密封止
パッケージに内蔵する場合、プレーナ型の耐圧構造部で
電界強度が極めて高くなり放電が発生して、耐圧構造を
破壊し、素子が正常に動作しない。この発明の目的は、
前記課題を解決して、耐圧構造部での放電を生じずに気
密封止パッケージにプレーナ型耐圧構造の半導体チップ
を内蔵した半導体装置を提供することにある。However, when a high withstand voltage planar device chip of 2000 V or more is built in a hermetically sealed package such as ceramic, the electric field strength becomes extremely high in the planar withstand voltage structure portion, and discharge occurs, The breakdown voltage structure is destroyed and the device does not operate normally. The purpose of this invention is
It is an object of the present invention to solve the above problems and provide a semiconductor device in which a semiconductor chip having a planar withstand voltage structure is built in a hermetically sealed package without causing discharge in the withstand voltage structure portion.
【０００４】[0004]
【課題を解決するための手段】前記の課題を解決するた
めに、気密封止されたパッケージを有する半導体装置に
おいて、第１導電形層の表面部に第１の第２導電形領域
が選択的に形成されるか、または、さらに第１の第２導
電形領域の表面部に高濃度第１導電形領域が選択的に形
成され、第１の第２導電形領域に挟まれる第１導電形層
の表面上にゲート絶縁膜を介してゲート電極が形成され
るもので、第１導電形層の表面部に第１の第２導電形領
域を取り囲むように一個以上の第２の第２導電形領域が
設けられ、第１の第２導電形領域と第２の第２導電形領
域に挟まれた第１導電形層の表面上および第２導電形領
域間に挟まれた第１導電形層の表面上に第１絶縁膜を形
成し、第１絶縁膜の表面上に放電保護膜としての第２絶
縁膜を形成する。To solve the above problems, in a semiconductor device having a hermetically sealed package, a first second conductivity type region is selectively formed on a surface portion of a first conductivity type layer. Or a high-concentration first conductivity type region is selectively formed on the surface portion of the first second conductivity type region and is sandwiched between the first second conductivity type regions. A gate electrode is formed on the surface of the layer via a gate insulating film, and at least one second conductive layer is formed on the surface of the first conductive layer so as to surround the first second conductive region. And a first conductivity type sandwiched between a first second conductivity type region and a second second conductivity type region, and a first conductivity type sandwiched between the second conductivity type regions. A first insulating film is formed on the surface of the layer, and a second insulating film as a discharge protection film is formed on the surface of the first insulating film.
【０００５】またこの第１絶縁膜と第２絶縁膜の間にア
モルファスシリコン膜を介在させると効果的である。さ
らに第２絶縁膜をポリイミド膜、もしくはパリレン酸化
膜で形成するとよい。It is also effective to interpose an amorphous silicon film between the first insulating film and the second insulating film. Further, the second insulating film may be formed of a polyimide film or a parylene oxide film.
【０００６】[0006]
【作用】プレーナ素子チップを樹脂封止パッケージに収
納させる場合、ゲル等の封止材を充填する。この封止材
がプレーナ素子の耐圧構造部での電界強度の緩和に寄与
している。一方メサ型素子チップを気密封止パッケージ
に収納した場合、気密封止パッケージ内は不活性ガスを
充填し、かつ耐圧構造となっているチップ周縁部はガラ
スやシリコーンゴムなどでコーテングして耐圧を維持し
ている。プレーナ素子チップを気密封止パッケージに収
納すると、プレーナ型耐圧構造が不活性ガスの雰囲気に
触れ、耐圧構造を構成している酸化膜もしくは酸化膜と
アモルファスシリコンのみでは耐圧の確保が困難であ
り、ゲル等の封止材がないために、電界強度が高まり放
電を起こす。特に２５００Ｖ以上の高耐圧になると放電
現象が起きやすくなる。このプレーナ型耐圧構造の酸化
膜や酸化膜の上のアモルファスシリコンの表面にポリイ
ミドやパリレン絶縁膜を被覆することで、電界強度の緩
和を促進し、２５００Ｖ以上の耐圧にも耐えられる気密
封止パッケージのプレーナ素子を得ることができる。When the planar element chip is housed in the resin-sealed package, it is filled with a sealing material such as gel. This sealing material contributes to the relaxation of the electric field strength in the breakdown voltage structure portion of the planar element. On the other hand, when the mesa type element chip is housed in a hermetically sealed package, the inside of the hermetically sealed package is filled with an inert gas, and the periphery of the chip, which has a pressure resistant structure, is coated with glass or silicone rubber to increase the pressure resistance. I am maintaining. When the planar element chip is housed in the hermetically sealed package, the planar withstand voltage structure comes into contact with the atmosphere of the inert gas, and it is difficult to secure the withstand voltage only with the oxide film or the oxide film and the amorphous silicon forming the withstand voltage structure. Since there is no sealing material such as gel, the electric field strength increases and discharge occurs. In particular, when the breakdown voltage is 2500 V or higher, the discharge phenomenon is likely to occur. By covering the surface of the oxide film of this planar type withstand voltage structure or the surface of the amorphous silicon on the oxide film with a polyimide or parylene insulating film, relaxation of the electric field strength is promoted, and a hermetically sealed package capable of withstanding a withstand voltage of 2500 V or more. The planar element of can be obtained.
【０００７】[0007]
【実施例】図１はこの発明をＩＧＢＴに適用した第１実
施例で、耐圧構造部を放電保護用絶縁膜で被覆した要部
断面図を示す。ｎ- 層１の表面部に第１のｐ領域２を形
成し、この第１のｐ領域２の表面部にｎ+ 領域３を形成
する。第１のｐ領域２に挟まれたｎ- 層１表面にゲート
酸化膜５を介してポリシリコンのゲート電極４が形成さ
れ、このゲート電極４の一部に金属膜でゲートパッド電
極１０が形成される。またゲート電極４上に層間絶縁膜
６を介してエミッタ電極７が形成される。第１のｐ領域
２を取り囲むように第２のｐ領域２１が第１のｐ領域２
と同時に形成され、第１と第２のｐ領域の間のｎ- 層１
上に耐圧構造を形成する酸化膜５１とこの酸化膜５１上
とエミッタ電極７上にフィールドプレートとなるアモル
ファスシリコン膜８が形成される。さらに電界強度の緩
和を促進するために、耐圧構造部上のアモルファスシリ
コン膜８上に放電保護用絶縁膜４０であるポリイミド膜
もしくはパリレン酸化膜を被覆する。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a first embodiment in which the present invention is applied to an IGBT, and shows a cross-sectional view of a main portion in which a breakdown voltage structure portion is covered with an insulating film for discharge protection. First p region 2 is formed on the surface of n − layer 1, and n + region 3 is formed on the surface of first p region 2. A gate electrode 4 of polysilicon is formed on the surface of the n − layer 1 sandwiched between the first p regions 2 via a gate oxide film 5, and a gate pad electrode 10 is formed on a part of the gate electrode 4 with a metal film. To be done. Further, an emitter electrode 7 is formed on the gate electrode 4 with an interlayer insulating film 6 interposed therebetween. The second p region 21 surrounds the first p region 2 and the first p region 2
N − layer 1 formed at the same time and between the first and second p regions
An oxide film 51 forming a breakdown voltage structure is formed thereon, and an amorphous silicon film 8 serving as a field plate is formed on the oxide film 51 and the emitter electrode 7. Further, in order to promote the relaxation of the electric field strength, a polyimide film or a parylene oxide film which is the discharge protection insulating film 40 is coated on the amorphous silicon film 8 on the breakdown voltage structure portion.
【０００８】図２はこの発明をＩＧＢＴに適用した第２
実施例で活性領域上と耐圧構造部を放電保護用絶縁膜で
被覆した要部断面図を示す。図１と異なるのは放電保護
用絶縁膜４０をゲートパッド電極１０の一部を除いた活
性領域上と耐圧構造部上とに被覆した点である。図３は
この発明を複数個のゲート電極を有するＩＧＢＴに適用
した第３実施例で耐圧構造部上を放電保護用絶縁膜で被
覆した要部断面図を示す。断面構造は図１とほぼ同じで
あるので、ここでは異なる点について説明する。ゲート
電極４が複数個に分割され、各ゲート電極に対応するよ
うにゲートパッド電極１０が形成され、ゲート電極４と
エミッタ電極７間のゲート耐圧が規格値以下のゲート電
極４を切り離し、かつ切り離したゲート電極４が浮遊電
位を持たないようにエミッタ電極７と貫通孔３２を通し
て短絡することにより、規格値を満足するゲート電極４
のみ有効に働く様にする。この貫通孔３２はゲートリペ
ア用絶縁膜９に窓開けすることで設けられる。同図では
規格値以上のゲート電極４を有する部分の要部断面図を
示し、エミッタ電極７とゲート電極４とを短絡する必要
がないため、貫通孔３２はポリイミド樹脂３３などで塞
がれている。そのポリイミド樹脂３３上とゲートパッド
電極１０上にはＡｌ配線３０、３１が形成され、ポリイ
ミド樹脂３３上のＡｌ配線３１はエミッタ電極７に接続
する。もし規格値以下のゲート電極４であればポリイミ
ド樹脂３３の代わりにＡｌ配線３１のＡｌ金属で埋めら
れ、エミッタ電極７と短絡接続される。活性領域部およ
び耐圧構造部に放電保護用保護膜４０としてのポリイミ
ド膜もしくはパリレン酸化膜を被覆する。FIG. 2 shows a second example in which the present invention is applied to an IGBT.
FIG. 3 is a cross-sectional view of a main part in which an insulating film for discharge protection covers the active region and the withstand voltage structure in the example. The difference from FIG. 1 is that the discharge protection insulating film 40 is coated on the active region excluding a part of the gate pad electrode 10 and on the breakdown voltage structure portion. FIG. 3 is a cross-sectional view of an essential part in which the present invention is applied to an IGBT having a plurality of gate electrodes, and the breakdown voltage structure part is covered with an insulating film for discharge protection in a third embodiment. Since the cross-sectional structure is almost the same as that in FIG. 1, different points will be described here. The gate electrode 4 is divided into a plurality of parts, the gate pad electrode 10 is formed so as to correspond to each gate electrode, and the gate electrode 4 whose gate breakdown voltage between the gate electrode 4 and the emitter electrode 7 is less than or equal to the standard value is cut off and cut off. By short-circuiting the emitter electrode 7 and the through hole 32 so that the gate electrode 4 does not have a floating potential, the gate electrode 4 satisfying the standard value is obtained.
Only work effectively. The through hole 32 is provided by opening a window in the gate repair insulating film 9. In the figure, a cross-sectional view of a main part of a portion having a gate electrode 4 of a standard value or more is shown, and since it is not necessary to short-circuit the emitter electrode 7 and the gate electrode 4, the through hole 32 is blocked with a polyimide resin 33 or the like. There is. Al wirings 30 and 31 are formed on the polyimide resin 33 and the gate pad electrode 10, and the Al wiring 31 on the polyimide resin 33 is connected to the emitter electrode 7. If the gate electrode 4 is less than the standard value, it is filled with the Al metal of the Al wiring 31 instead of the polyimide resin 33 and short-circuited to the emitter electrode 7. A polyimide film or a parylene oxide film as the protective film 40 for discharge protection is coated on the active region and the breakdown voltage structure.
【０００９】図４はこの発明を複数個のゲート電極を有
するＩＧＢＴに適用した第４実施例で耐圧構造部をゲー
トリペア用絶縁膜で被覆した要部断面図を示す。断面構
造は図３とほぼ同じである。ここでは異なる点について
説明する。ポリイミド膜またはパリレン酸化膜をゲート
リペア用絶縁膜９として用い、さらにこのゲートリペア
用絶縁膜９を耐圧構造部上にも被覆させ、放電保護用絶
縁膜としても用いた点が図３と異なる。このようにすれ
ば製造工程が簡略化され、図３より工程数を減少でき
る。FIG. 4 is a cross-sectional view of an essential part in which the breakdown voltage structure part is covered with an insulating film for gate repair in a fourth embodiment in which the present invention is applied to an IGBT having a plurality of gate electrodes. The sectional structure is almost the same as in FIG. Here, different points will be described. 3 is different from that in FIG. 3 in that a polyimide film or a parylene oxide film is used as the insulating film 9 for gate repair, and the insulating film 9 for gate repair is also coated on the breakdown voltage structure portion and used as an insulating film for discharge protection. In this way, the manufacturing process is simplified and the number of processes can be reduced as compared with FIG.
【００１０】図１ないし図４とも耐圧構造部上の最終被
覆材はポリイミド膜もしくはパリレン酸化膜となり、こ
れらの被覆材なしでは、２５００Ｖ以下で９０％以上放
電したのに対し、被覆材をコーティングした場合は殆ど
の素子が２５００Ｖ以下では放電しない。ここではＩＧ
ＢＴに適用した場合について説明したが、プレーナ型の
ダイオードやサイリスタにも勿論適用できる。1 to 4, the final coating material on the pressure resistant structure is a polyimide film or a parylene oxide film. Without these coating materials, 90% or more of the discharge was generated at 2500 V or less, whereas the coating material was coated. In this case, most of the devices do not discharge below 2500V. IG here
Although the case where it is applied to the BT has been described, it can be applied to a planar type diode or a thyristor.
【００１１】[0011]
【発明の効果】この発明によれば、特別な工程を追加す
ることなく、プレーナ型の耐圧構造の表面に絶縁膜を被
覆でき、気密封止パッケージにプレーナ素子チップを収
納しても、放電現象を防止でき、２５００Ｖクラスの高
耐圧のプレーナ型の半導体装置を得ることができる。According to the present invention, the surface of the planar withstand voltage structure can be covered with an insulating film without adding a special process, and even if the planar element chip is housed in the hermetically sealed package, the discharge phenomenon occurs. Can be prevented, and a planar type semiconductor device with high withstand voltage of 2500 V class can be obtained.
【図１】この発明をＩＧＢＴに適用した第１実施例の要
部断面図FIG. 1 is a sectional view of an essential part of a first embodiment in which the present invention is applied to an IGBT.
【図２】この発明をＩＧＢＴに適用した第２実施例の要
部断面図FIG. 2 is a sectional view of an essential part of a second embodiment in which the present invention is applied to an IGBT.
【図３】この発明を複数個のゲート電極を有するＩＧＢ
Ｔに適用した第３実施例の要部断面図FIG. 3 shows an IGB having a plurality of gate electrodes according to the present invention.
Sectional drawing of the principal part of 3rd Example applied to T
【図４】この発明を複数個のゲート電極を有するＩＧＢ
Ｔに適用した第４実施例の要部断面図FIG. 4 shows an IGB having a plurality of gate electrodes according to the present invention.
Sectional drawing of the principal part of 4th Example applied to T.
１ ｎ- 層 ２ 第１のｐ領域 ２１ 第２のｐ領域 ３ ｎ+ 領域 ４ ゲート電極 ５ ゲート酸化膜 ５１ 酸化膜 ６ 層間絶縁膜 ７ エミッタ電極 ８ アモルファスシリコン膜 ９ ゲートリペア用絶縁膜 １０ ゲートパッド電極 ３０ Ａｌ配線 ３１ Ａｌ配線 ３２ 貫通孔 ３３ ポリイミド樹脂 ４０ 放電保護用絶縁膜1 n − Layer 2 First p Region 21 Second p Region 3 n + Region 4 Gate Electrode 5 Gate Oxide Film 51 Oxide Film 6 Interlayer Insulation Film 7 Emitter Electrode 8 Amorphous Silicon Film 9 Insulation Film for Gate Repair 10 Gate Pad Electrode 30 Al wiring 31 Al wiring 32 Through hole 33 Polyimide resin 40 Insulation film for discharge protection
Claims (4)
装置において、第１導電形層の表面部に第１の第２導電
形領域が選択的に形成され、第１導電形層の表面部に第
１の第２導電形領域を取り囲むように一個以上の第２の
第２導電形領域が設けられ、第１の第２導電形領域と第
２の第２導電形領域に挟まれた第１導電形層の表面上お
よび第２導電形領域間に挟まれた第１導電形層の表面上
に第１の絶縁膜を形成し、第１絶縁膜の表面上に放電保
護膜としての第２絶縁膜を形成することを特徴とする半
導体装置。1. In a semiconductor device having a hermetically sealed package, a first second conductivity type region is selectively formed on a surface portion of a first conductivity type layer, and a first conductivity type layer is formed on a surface portion of the first conductivity type layer. One or more second second conductivity type regions are provided so as to surround the first second conductivity type region, and the first second conductivity type region is sandwiched between the first second conductivity type region and the second second conductivity type region. A first insulating film is formed on the surface of the conductive type layer and on the surface of the first conductive type layer sandwiched between the second conductive type regions, and a second insulating film is formed on the surface of the first insulating film as a discharge protection film. A semiconductor device comprising an insulating film.
装置において、第１導電形層の表面部に第１の第２導電
形領域が選択的に形成され、第１の第２導電形領域の表
面部に高濃度第１導電形領域が選択的に形成され、第１
の第２導電形領域に挟まれる第１導電形層の表面上にゲ
ート絶縁膜を介してゲート電極が形成され、第１導電形
層の表面部に第１の第２導電形領域を取り囲むように一
個以上の第２の第２導電形領域が設けられ、第１の第２
導電形領域と第２の第２導電形領域に挟まれた第１導電
形層の表面上および第２導電形領域間に挟まれた第１導
電形層の表面上に第１の絶縁膜を形成し、第１絶縁膜の
表面上に放電保護膜としての第２絶縁膜を形成すること
を特徴とする半導体装置。2. A semiconductor device having a hermetically sealed package, wherein a first second conductivity type region is selectively formed on a surface portion of a first conductivity type layer, and a first second conductivity type region is formed. A high-concentration first conductivity type region is selectively formed on the surface portion,
A gate electrode is formed on the surface of the first conductivity type layer sandwiched between the second conductivity type regions by a gate insulating film so as to surround the first second conductivity type region on the surface portion of the first conductivity type layer. One or more second second conductivity type regions are provided in the first second
A first insulating film is provided on the surface of the first conductivity type layer sandwiched between the conductivity type region and the second second conductivity type region and on the surface of the first conductivity type layer sandwiched between the second conductivity type regions. And a second insulating film as a discharge protection film formed on the surface of the first insulating film.
スシリコン膜を介在させることを特徴とする請求項１ま
たは２記載の半導体装置。3. The semiconductor device according to claim 1, wherein an amorphous silicon film is interposed between the first insulating film and the second insulating film.
レン酸化膜で形成されることを特徴とする請求項１また
は２記載の半導体装置。4. The semiconductor device according to claim 1, wherein the second insulating film is formed of a polyimide film or a parylene oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00459395A JP3265886B2 (en) | 1995-01-17 | 1995-01-17 | Planar type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00459395A JP3265886B2 (en) | 1995-01-17 | 1995-01-17 | Planar type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08195488A true JPH08195488A (en) | 1996-07-30 |
| JP3265886B2 JP3265886B2 (en) | 2002-03-18 |
Family
ID=11588350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00459395A Expired - Fee Related JP3265886B2 (en) | 1995-01-17 | 1995-01-17 | Planar type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3265886B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9627552B2 (en) | 2006-07-31 | 2017-04-18 | Vishay-Siliconix | Molybdenum barrier metal for SiC Schottky diode and process of manufacture |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010038933A1 (en) * | 2009-08-18 | 2011-02-24 | Denso Corporation, Kariya-City | Semiconductor chip and metal plate semiconductor device and method of manufacturing the same |
-
1995
- 1995-01-17 JP JP00459395A patent/JP3265886B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9627552B2 (en) | 2006-07-31 | 2017-04-18 | Vishay-Siliconix | Molybdenum barrier metal for SiC Schottky diode and process of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3265886B2 (en) | 2002-03-18 |
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