JPH08194826A - Graphic controller - Google Patents

Abstract

PURPOSE: To improve line plotting performance by collectively transferring pixel data constituting a horizontal line. CONSTITUTION: A control circuit in a line plotting circuit 132a detects a horizontal line segment from a straight line requested at its plotting by the use of a Bresnham error term. At the time, NOPEL indicating the number of pixels of the horizontal line segment and a data transfer request TRRQ are sent from the circuit 132a to a data transfer control unit 134. The unit 134 transfers plural data corresponding to the number of pixels constituting the horizontal line segment to a video memory as a block. Thereby pixel data constituting a horizontal line can be collectively transferred and line plotting performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphics controller for controlling a display monitor of a personal computer, and more particularly to a graphics controller having a bit map type video memory and transferring data to the video memory to draw a figure. Regarding

[0002]

2. Description of the Related Art In recent years, various portable laptop or notebook type portable personal computers have been developed. Conventionally, a graphics controller used in this type of personal computer is provided with a drawing function such as creation of a basic figure such as a straight line and filling of a region. Of these drawing functions, the drawing of a straight line is executed by a line drawing circuit provided in the graphics controller.

When the host CPU requests drawing of a straight line, the line drawing circuit calculates the two-dimensional coordinate value from the starting point coordinates to the ending point coordinates of the straight line for each pixel, and draws the drawing data in pixel units in the video memory. Transfer to. Such drawing processing is similarly performed even if the straight line to be drawn is a horizontal line.

In drawing a horizontal line, linear addresses of adjacent pixels on a video memory are continuous. Therefore, in principle, it should be possible to collectively transfer the image data of a plurality of pixels to the video memory in one memory transfer cycle.

However, in the conventional line drawing circuit, the horizontal line and other lines are not distinguished from each other as described above, and no matter what line is drawn, data is transferred in one data transfer cycle. Is always 1 pixel. Therefore, in drawing a horizontal line, as in the case of drawing other lines, it is necessary to repeatedly execute the data transfer cycle by the number of pixels forming the line, which is disadvantageous in that drawing takes a lot of time. there were.

[0006]

In the conventional line drawing circuit, the drawing data is transferred to the video memory in pixel units while calculating the two-dimensional coordinate value for each pixel. Therefore, one pixel is always transferred in one data transfer cycle. Therefore, even in the drawing of a horizontal line, it is necessary to repeat the data transfer cycle as many times as the number of pixels forming the horizontal line, and there is a drawback that drawing takes a lot of time.

The present invention has been made in view of the above point, and when a straight line to be drawn includes a horizontal line component, pixel data forming the horizontal line can be collectively transferred to draw a straight line. It is an object of the present invention to provide a graphics controller that can significantly improve speed.

[0008]

Means and Actions for Solving the Problems
In a graphics controller that has a bit map format video memory and controls a display monitor, when drawing a straight line is specified, a means for detecting a horizontal line segment included in the straight line and a detected horizontal line segment. A unit for counting the number of pixels forming each line segment, and a plurality of drawing data corresponding to the number of pixels forming each horizontal line segment are block-transferred to the video memory, and the drawing data are Data transfer means for writing to consecutive addresses on the video memory.

In this graphics controller, if a horizontal line segment is included in the straight lines requested by the host system for drawing, the horizontal line segment is detected. For example, when a horizontal line is requested to be drawn, the entire requested horizontal line is detected as a horizontal line segment. Also, when drawing a straight line having a certain inclination is required, since the straight line is usually composed of a plurality of horizontal line segments having different vertical coordinate values, each of the plurality of horizontal line segments is Because it is detected. Then, the number of pixels of each horizontal line segment is counted, and a plurality of drawing data corresponding to the number of pixels constituting each horizontal line segment are collectively transferred to the video memory.

Therefore, it is possible to greatly improve the performance of straight line drawing as compared with the conventional graphics controller which transfers data to the video memory pixel by pixel. As means for detecting the horizontal line segment, means for calculating the coordinate value for drawing the straight line for each pixel using Bresenham's argomizm and detecting the pixel position where the vertical coordinate changes is used. be able to. Bresenham's argomizm is because the coordinate value is generated by determining for each pixel whether the next coordinate value of the current coordinate value (X, Y) is (X + 1, Y) or (X + 1, Y + 1). Algorithm (X + 1, Y) and (X + 1, Y +
Which of 1) is used is determined by the value of the Bresenham error term (E). If the Bresenham error term (E) ≧ 0, (X + 1, Y + 1) is selected. Therefore, the pixel position where the Y coordinate changes in the straight line can be detected by the value of this Bresenham error term (E).

Further, by providing means for converting the value of the line parameter designating the horizontal line segment into the parameter value for the BIT block transfer, the block transfer of the pixels constituting the horizontal line segment is performed in the normal BIT block. This can be done using a transfer circuit. Since the BIT block transfer is a basic function supported by a normal graphics controller, the pixels forming the horizontal line segment can be block transferred without using dedicated hardware by using this BIT block transfer. .

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a display control subsystem using a graphics controller according to an embodiment of the present invention. The display control subsystem 4 conforms to the XGA specification and performs display control on both the flat panel display 40 that is standardly equipped in the portable computer main body and the color CRT display 50 that is detachably connected to the portable computer main body. . The display control subsystem 4 is
As shown, it is connected to a local bus 3 such as a VL bus or a PCI bus.

The display control subsystem 4 is provided with a graphics controller 10 and a video memory 30. The graphics controller 10 and the video memory 30 are mounted on the system board of the portable computer.

The graphics controller 10 is one LSI realized by a gate array, and constitutes the main part of this display control system 4. The graphics controller 10 includes a flat panel display 40 and a color CRT according to an instruction from the host CPU 1.
Control the display 50. Further, the graphics controller 10 functions as a bus master and can directly access the system memory 2.

The video memory 30 is a bit map memory for storing a screen image to be displayed on the flat panel display 40 or the color CRT display 50. This video memory 30 is, for example, a synchronous DR
It is composed of AM. The synchronous DRAM is a memory having features of clock synchronous operation, operation mode control by command, and two-bank memory cell array configuration. The video memory 30 is, for example, 256
2 synchronous DRAM chips with K × 16 bits
It can be realized by connecting them in parallel. In this case 3
Data is read / written in 2-bit width units.

Image data created by an application program or the like conforming to the XGA specifications is stored in the video memory 30 by the packed pixel method. This packed pixel method is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory. For example, a method in which one pixel is represented by 1, 2, 4, 8, 16 or 24 bits is adopted. ing. On the other hand, the VGA specification image data is created by an application program or the like conforming to the VGA specification and is stored in the video memory 30 by the memory plane method. This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address, and color information of each pixel is assigned to these planes. For example, when there are four planes, one pixel is represented by a total of 4 bits of data, one bit for each plane.

Text data is also stored in the video memory 30. Text data for one character is XG
Both the A and VGA specifications have a total size of 2 bytes consisting of an 8-bit code and an 8-bit attribute. The attribute is composed of 4-bit data specifying a foreground color and 4-bit data specifying a background color.

The graphics controller 10 includes a register control circuit 11 and a system bus interface 1.
2, graphics accelerator 13, memory control circuit 14, CRT controller (CRTC) 16, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite Color register 25, C
RT video multiplexer 26, sprite control circuit 2
7, a flat panel emulation circuit 28, and a DAC (D / A converter) 35.

The register control circuit 11 receives an address and data from the local bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers designated by the decoding result.

The system bus interface 12 controls the interface with the host CPU 1 via the local bus 3 and supports burst transfer. In addition, the system bus interface 12
Has a cache 121 built therein. The cache 121 is used to speed up the transfer of image data between the CPU 1 or the accelerator 13 and the video memory 30, and holds a part of the image data in the video memory 30. If the image data requested to be read by the CPU 1 or the accelerator 13 exists in the cache 121, the cache 121
The image data is read from and transferred to the CPU 1 or the accelerator 13. In this case, the video memory 30 is not read-accessed.

The graphics accelerator 13 is a CP
In response to an instruction from U1, the image data in the video memory 30 is provided with various drawing functions. This accelerator 13 is BitBlt (bit bl
block transfer of pixels, such as
Line drawing, arc drawing, area filling, logic between pixels /
It has arithmetic operations, screen cutout, map mask, XY coordinate addressing, memory management function by paging, and the like.

As shown in FIG. 2, the accelerator 13 includes a copro register 131, an XY address generation unit 132, and a linear address conversion unit 13.
3, a data transfer control unit 134, a paging unit 135, and an arithmetic unit (ALU) 136.

The coprocessor register 131 includes a plurality of I / O registers accessible by the CPU 1.
A parameter value for using the drawing function of the accelerator 13 is set in each of these registers.

The XY address generation unit 132 is
It generates an XY two-dimensional address for accessing a rectangular area transferred by itBlt or drawing a line. In this case, the XY address for line drawing is X-
Line drawing circuit 1 with built-in Y address generation unit 132
32a. This line drawing circuit 132
In a, in order to improve the line drawing speed, a horizontal line component included in the line to be drawn is detected, and the data transfer control unit 134 is caused to perform data transfer to the video memory 30 in units of the horizontal line. Has built-in logic. In this case, the transfer request is signal T
The data transfer control unit 1 from the line drawing circuit 132a by RRQ (Transfer request)
34 is notified, and the number of transfer pixels at that time is NOPEL
(Number of pixelto transf
er). Here, in fact, NOP
EL indicates the number of transfer pixels-1.

The configuration of the line drawing circuit 132a is a feature of the present invention, and its details will be described with reference to FIG. The linear address conversion unit 133 converts the XY address into a linear address (physical address) for memory access using segmentation or the like. In this case, the linear address conversion processing by the linear address conversion unit 133 is performed only for the start address, and the addresses subsequent to the start address are executed by the linear address control unit 134a of the data transfer control unit 134. Paging unit 1
Reference numeral 35 is for supporting the same virtual memory mechanism as the CPU 1, and when paging is valid, the linear address created by the linear address translation unit 133 or the linear address control unit 134a is translated into a real address by paging. An address translation buffer (TLB) is used in this translation. When paging is invalid, the linear address is output as it is as a real address.

The data transfer control unit 134 controls data transfer between the system memory 2 and the video memory 30, and in addition to the linear dress control unit 134a described above, a system memory interface 134b and pixel data control. Unit 1
34c.

The pixel data control unit 134c includes
A shift circuit 201 and a data buffer 202 are provided, and pixel data operations such as shift, logical arithmetic operation, bit mask, and color comparison, and VGA compatible Bi
Supports tBit function. Logical arithmetic operations are ALU
It is done in collaboration with 136.

The memory control circuit 14 of FIG. 1 is for controlling access to the video memory 30, and is a CPU.
1 and read / write access to the video memory 30 according to the read / write request of the image data from the accelerator 13 and read access to the video memory 30 for screen refreshing according to the display address from the CRTC 16.

The memory control circuit 14 incorporates an address control logic and a command control logic for improving the access efficiency to the synchronous DRAM. These logics make it possible to continuously execute a plurality of read / write cycles for the synchronous DRAM without inserting a precharge cycle. Further, the memory control circuit 14 has a built-in address counter and has a burst transfer function of continuously reading / writing data to a plurality of addresses following the read address as a start address.

The data bus width between the memory control circuit 14 and the video memory 30 is set to the same as the data transfer width of the local bus 3, for example, 32 bits. CRT controller 16, sprite memory 19, serializer 2
0, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 2
6, sprite control circuit 27, flat panel emulation circuit 28, and DAC (D / A converter)
35 is a video memory 3 for screen refresh.
A display control circuit for reading image data from 0 and converting it into a video signal is configured.

The CRT controller (CRTC) 16 is
It generates various display timing signals (horizontal synchronizing signal, vertical synchronizing signal, etc.) for controlling the flat panel display 40 or the CRT display 50, and a display address for reading image data to be displayed on the screen from the video memory 30.

Sprite data is written in the graphics mode in the sprite memory 19, and fonts are written in the text mode. In the text mode, the code of the text data read from the video memory 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a parallel / serial conversion circuit for dividing the parallel pixel data for a plurality of pixels read from the video memory 30 into pixel units (serial) and outputting the data. In the graphics mode, the serializer 20 is used. The image data read from 30 and the sprite data read from the sprite memory 19 are respectively parallel / serial converted, and in the text mode, the font data read from the sprite memory 19 is parallel / serial converted.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and holds the attribute of text data read from the video memory 30 in the text mode. The foreground / background multiplexer 22 selects one of the attribute foreground color (front color) / background color (background color) in the text mode.
This selection is controlled by the values "1" (foreground) and "0" (background) of the font data output from the serializer 20. The graphics / text multiplexer 23 is for switching between the graphics mode and the text mode. In the graphics mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background is selected. Multiplexer 22
Select the output of

The color palette control circuit 24 is for performing color conversion of graphics or text data. The color pallet control circuit 24 has a two-stage color pallet table. The first color palette table is composed of 16 color palette registers. 6-bit color palette data is stored in each color palette register. The second color pallet table is composed of 256 color pallet registers. Each color palette register stores 24-bit color data consisting of 8 bits for each of R, G, and B.

In the graphics mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without going through the first color palette table, where R, G, and B respectively. 8
Converted to color data composed of bits. The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. Then, the 6-bit color data is added with the 2-bit data output from the color selection register incorporated in the color palette control circuit 19 to make a total of 8-bit color data. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 8 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
Each of G and B is converted into color data composed of 8 bits.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits or 24 bits. In this case, the pixel data of the pixel does not go through the color palette control circuit 24. It is directly supplied to the CRT video multiplexer 26.

The sprite color register 25 stores sprite display data designating a sprite display color such as a hardware cursor. The CRT video multiplexer 26 selects the CRT video display output, and selects the output of the color palette control circuit 24, the direct color output from the serializer 20, the sprite display data, or the external video data. This selection operation is controlled by the display timing signal from the CRTC 16. The external video data is video data such as a moving image input from outside the display control system 4, for example. The sprite control circuit 27 uses the serializer 20.
The sprite display data of the sprite color register 25 is output according to the parallel / serial converted sprite data.

Flat panel emulation circuit 28
Converts the CRT video output to produce flat video data for flat panel display 40. DA
The C 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies the analog R, G, B signals to the CRT display 50.

Next, referring to FIG. 3, the accelerator 1
A specific configuration of the line drawing circuit 132a provided in No. 3 will be described. When the drawing of a straight line is designated, the line drawing circuit 132a detects a horizontal line segment included in the straight line using the error term of Bresenham algorithm, and the number of pixels to be transferred for each horizontal line segment ( NOP
EL) is calculated, and the transfer destination X
A Y address calculation circuit 201, a control circuit 202, a pixel count (PCNT) circuit 203, and a Bresenham error term calculation circuit 204 are provided.

In order to make the operation of each of these circuits easy to understand, the principle of calculation of the transfer destination XY address (DX, DY) using the Bresenham algorithm will be described first.
Bresenham's algorithm is an algorithm used to execute the line drawing function. The next coordinate value of the current coordinate value (X, Y) is (X + 1, Y) and (X +
1, Y + 1) for each pixel,
As a result, the coordinate value of each pixel connecting the start point coordinate and the end point coordinate is obtained. This algorithm uses the following three parameters normalized to the first octant (octant 0).

1. Bresenham error term E {E = 2 × deltaY-deltaX} 2. Bresenham constant K1 {K1 = 2 × deltaY} 3. Bresenham's constant K2 {K2 = 2 × (deltaY-deltaX)} where deltaX is the difference between the X address values of the end point coordinates and the start point coordinates, and deltaY is the difference between the Y address values of the end point coordinates and the start point coordinates. Is shown. For example, in FIG.
When the transfer destination start point coordinates on the destination map are (STDX, STDY) and the transfer destination end point coordinates are (LIMDX, LIMDY), deltaX = LIMDX-STDX deltaY = LIMDY-STDY. Becomes

The Bresenham error term E sets the transfer destination coordinate value next to the current transfer destination coordinate value (X, Y) to (X + 1,
Y) or (X + 1, Y + 1). If the Bresenham error term E ≧ 0, (X + 1, Y + 1) is selected. On the other hand, if the Bresenham error term E <0, (X + 1, Y) is selected.

The procedure of line drawing using the Bresenham algorithm is as shown in FIG. That is, first,
XY coordinates of the start point and the end point are given, and the parameters E, K1, and K2 are obtained according to the coordinate values and set in the copro register 131 (step S101).
Next, after the value of the X address of the starting point coordinate is incremented by 1, the Bresenham error term E is checked whether E ≧ 0 (step S104).

If E ≧ 0, the value of E is updated to E + K2, and the value of the Y address of the starting point coordinate is incremented by +1 (steps S104 and S105). As a result, the coordinate value of the pixel next to the starting point coordinates (X, Y) is (X + 1,
Y + 1) is determined.

On the other hand, if E <0, only the value of E is E + K
It is updated to 1, and the value of the Y address of the starting point coordinates is not updated (step S106). As a result, the starting point coordinates (X,
The coordinate value of the pixel next to Y) is determined to be (X + 1, Y).

When the coordinate value of the next pixel is determined, the line segment length L (L = X address of end point coordinate−X address of start point coordinate) is decremented by 1 (step S107). Step S1
The processing from 02 to S107 is repeatedly executed until the line segment length L becomes 0 (step S108). As a result, a line segment connecting the start point and the end point is drawn.

Transfer destination XY address operation circuit 20 of FIG.
1 is controlled by a control signal from the control circuit 202, and a transfer destination XY address (D
X, DY) and the number of transferred pixels (NOPEL) are calculated. The transfer destination XY address (DX, DY) is obtained for each pixel forming a straight line according to the above-mentioned Bresenham's argomizism, and the linear address conversion unit 1
Sent to 33. The number of transfer pixels (NOPEL) is the horizontal line length −1 when drawing a horizontal line,
That is, the number of pixels forming a horizontal line is -1. When drawing a straight line having a certain inclination, the pixel of the horizontal line segment to be transferred among the plurality of horizontal line segments forming the straight line Indicates the number -1.

This transfer destination XY address operation circuit 201
Is provided with a DX counter 301, a next DX (NDX) counter 302, a DY counter 303, a subtractor 304, comparators 305 and 306, and an OR gate 307.

The DX counter 301 is loaded with the transfer start destination X address (STDX). S
TDX indicates the value of the X address of the starting point coordinates. The initial value of the output DX of the DX counter 301 is STDX, and when the DX update request signal (DXUDRQ) is generated from the control circuit 202, the N output from the subtractor 304 at that time is output.
It is incremented by the value of OPEL. The output DX of the DX counter 301 is supplied to the first input of the subtractor 304.

When drawing a horizontal line, the NDX counter 302 is loaded with the destination X address limit value (LINDX) as an initial value. LIND
X becomes the X address value of the end point coordinate of the line when the end point coordinates do not cross the destination or mask map boundary, and becomes the final X address in the map when it crosses.

When drawing a line having a certain inclination, STDX is loaded as an initial value in the NDX counter 302. In this case, S of the NDX counter 302
The value of TDX is the Bresenham error term update request pulse (BETUD; Bresenh) from the control circuit 202.
am error term update request
The count is incremented for each pixel in units of +1 according to the (est pulse). The Bresenham error term update request pulse (BETUD) is a signal used to update the value of the Bresenham error term E to E + K2 or E + K1, and is generated every time the coordinate value of a pixel is determined.

The NDX counter 302 receives LINDX and ST.
Which of the DX is loaded is controlled by the control circuit 302. The output NDX of the NDX counter 302 is
It is supplied to the second input of the subtractor 304 and the first input of the comparator 305. LIMDX is input to the second input of the comparator 305.

The DY counter 303 is loaded with the transfer start destination Y address (STDY).
STDY indicates the value of the Y address of the starting point coordinates. The DY value of the DY counter 303 is counted up in units of +1 according to the DY update request signal (DYUDRQ) from the control circuit 202. DY update request signal (DYUDRQ)
Is generated when the Bresenham error term E is E ≧ 0, that is, when the coordinates (X + 1, Y + 1) are selected.

The output DY of the DY counter 303 is supplied to the first input of the comparator 306. Comparator 3
LIMDY is input to the second input of 06. L
IMDY indicates the Y address value of the end point coordinate of the line when the end point coordinate does not cross the destination or mask map boundary, and indicates the final Y address in the map when it crosses.

The subtractor 304 subtracts the value of the output DX from the DX counter 301 from the value of the output NDX from the NDX counter 302 to calculate | NDX-DX | as the transfer pixel number (NOPEL).

In the case of drawing a horizontal line, the value of the output NDX of the NDX counter 302 is equal to LIMDX, so | NDX-DX | (= NOPEL) corresponds to the number of pixels constituting a horizontal line-1.

In the case of drawing a line having a certain inclination,
The value of the output NDX of the NDX counter 302 is counted up in units of +1 for each pixel, and the DX counter 30
The output DX of 1 is | NDX-DX | (= NOPE) at each time when the DY update request signal (DYUDRQ) is generated.
L) is incremented.

Therefore, in the case of drawing a line having a certain inclination, when the DY update request signal (DYUDRQ) is generated, | NDX-DX | (= NOPEL) becomes
Among the horizontal line segments forming the drawing target line, the number of pixels of the horizontal line segment to be transferred is -1.

The comparator 305 has an NDX counter 3
The output NDX of 01 is compared with LIMDX, and when they match, the OR gate 3 outputs a match signal of logic "1" level.
It outputs to 07. The comparator 306 compares the output DY of the DY counter 301 with LIMDY, and when they match, outputs a match signal of logic “1” level to the OR gate 3.
It outputs to 07.

When the coincidence signal is output from the comparator 305 or 306, the OR gate 307 causes the control circuit 2 to
02 the final transfer signal (LASTTR; Last tra)
nsfer) is output. LASTTR indicates that the transfer end condition is satisfied and the transfer for drawing is completed in the next transfer cycle.

The control circuit 202 is a line drawing circuit 132.
The operation control of the whole a and the interface control with the data transfer control circuit 134 are executed. A transfer start pulse (TRSP) is provided between the control circuit 202 and the data transfer control circuit 134.
e), transfer request signal (TRRQ; Transfer r)
request), transfer ready signal (TRRDY; Tr
transfer ready, transfer completion signal (TREN)
D; Transferend) is given and received.

The transfer start pulse (TRSP) indicates the start of data transfer for line drawing. For example, when a line drawing command is set in the copro register 131, it is sent from the data transfer control circuit 134 to the control circuit 202. .

The transfer request signal (TRRQ) is a signal for requesting data transfer to the data transfer control unit 134 as described above, and the number of transfer pixels at that time is instructed to the data transfer control unit 134 by the NOPEL. It The transfer request signal (TRRQ) is generated when the Bresenham error term E changes from negative to E≤0 or in response to the final transfer signal (LASTTR).

The transfer ready signal (TRRDY) is a signal sent from the data transfer control unit 134 to the control circuit 202 and indicates that the transfer request signal (TRRQ) has been accepted.

The transfer completion signal (TREND) is a signal sent from the control circuit 202 to the data transfer control unit 134 and indicates that the issuance of all data transfer requests for drawing has been completed.

Control circuit 202 and address operation circuit 201
Between the last transfer signal (LASTTR),
Bresenham error term update request pulse (BETU
D), DX update request signal (DXUDRQ) and DY update request signal (DYUDRQ), as well as update request signal DXU
Ready signal DXUDR for DRQ and DYUDRQ
Y, DYUDRY, etc. are given and received.

Pixel count (PCNT) circuit 203
Counts the number of remaining pixels whose coordinate values have not been calculated in the drawing target line, and uses the pixel count signal (PE
Lcount). Pixel count signal (P
The value of CNT; PEL count) is decremented by 1 per pixel in response to the Bresenham error term update request pulse (BETUD), and the number of remaining pixels becomes zero, that is, when the transfer is completed. When drawing a horizontal line, all the pixels forming the horizontal line are transferred at one time, so the value of the pixel count signal (PEL count) is decremented by the value of NOPEL at a time.

Bresenham error term calculation circuit 204
5 sequentially updates the Bresenham error term E in accordance with the Bresenham error term described in FIG. 5, and outputs the sign bit of the Bresenham error term E. Here, the Bresenham error term E is −8192 ≦ E ≦ 8.
It is assumed that the value of 191 is taken, and the sign bit is bit 13 (BET <13>) of the error term data string (BET <13-0>).

Next, the operation of the line drawing circuit 132a shown in FIG. 3 will be described with reference to FIGS. First, with reference to the timing chart of FIG. 7, an operation when transferring a horizontal line as shown in FIG. 6 will be described. FIG. 6 exemplifies a case where the start point coordinates and the end point coordinates are designated across the destination map boundary.

In this case, since deltaY is zero,
The values of the three parameters used in Bresenham algorithm are obtained as follows. K1 = 0 K2 = −2 × deltaX E = −deltaX These parameter values are set in the copro register 131,
It is referred to by the Bresenham error term arithmetic circuit 204 and the control circuit 202.

Since K1 = 0, the control circuit 202 recognizes that the drawing target line is a horizontal line. When a transfer start pulse (TRSP) is sent from the data transfer control circuit 134 to the control circuit 202, the control circuit 20
2 loads STDX and STDY into the DX counter 301 and the DY counter 303, respectively, and
LIMDX is loaded into the NDX counter 302. In this case, LIMDX indicates the value of the final X address of the destination map. At this time, since the output NDX of the NDX counter 302 is equal to LIMDX, the final transfer signal (LASTTR) is sent to the control circuit 202.

The control circuit 202 controls the final transfer signal (LAS
In response to the TTR, a transfer request signal (TRRQ) is issued to request the data transfer control unit 134 to transfer the data. At this time, NOPEL obtained by the subtraction circuit
(= | NDX-DX |) is sent to the data transfer control unit 134 as the number of transfer pixels. Further, the output DX of the DX counter 301 and the output D of the DY counter 303
Y is sent to the linear address conversion unit 133 as a transfer start XY address, and is converted into a start address for data transfer to the video memory 30 there.

When the transfer request signal (TRRQ) is received,
The data transfer control unit 134 includes the memory control circuit 14
Is used to start the block transfer for continuously transferring | NDX-DX | +1 pixel data to the video memory 30 and writing the pixel data to successive addresses on the video memory 30.

When this data transfer is completed and the transfer ready signal (TRRDY) changes from the active state to the inactive state, the control circuit 202 issues a Bresenham error term update request pulse (BETUD). In response to the Bresenham error term update request pulse (BETUD), a pixel count signal (PC
The value of (NT) is decremented at once by the value of NOPEL to become zero. After that, the control circuit 202 issues a transfer completion signal (TREND) to notify the data transfer control unit 134 that the issuance of all data transfer requests for drawing has been completed.

As described above, when drawing a horizontal line, the number of pixels forming the horizontal line is obtained, and data for the number of pixels is transferred to the video memory 30 at one time. Therefore, the performance of drawing horizontal lines can be significantly improved over the conventional graphics controller that transfers data to the video memory on a pixel-by-pixel basis.

Next, with reference to the timing chart of FIG. 9, the operation for drawing a line including horizontal line segments as shown in FIG. 8 will be described. FIG. 8 exemplifies a case where the start point coordinates and the end point coordinates are within the destination map boundary.

In this case, since deltaY is not zero, the values of the three parameters used in Bresenham algorithm are obtained as follows. K1 = 2 × deltaY K2 = 2 × (deltaY−delta)
X) E = 2 x deltaY-deltaX These parameter values are set in the copro register 131,
It is referred to by the Bresenham error term arithmetic circuit 204 and the control circuit 202.

Since K1 and K2 are not 0, the control circuit 202 recognizes that the line to be drawn has a certain inclination. When the transfer start pulse (TRSP) is sent from the data transfer control circuit 134 to the control circuit 202, the control circuit 202 causes the DX counter 301 and D
The Y counter 303 is loaded with STDX and STDY, respectively, and the NDX counter 302 is loaded with STDX.

The control circuit 202 controls STDX and STD.
The Bresenham error term update request pulse (BET) is calculated for each pixel in order to obtain the coordinate value of the pixel following Y.
UD) is issued, and it is checked whether or not the output BET <13> from the Bresenham error term calculation circuit 204 in response to this is zero.

During the period when BET <13> is 1, that is, the Bresenham error term E <0, the DX counter 3
01 and DY counter 303 update request DXU
Neither DRQ nor DYUDRQ is generated, and only the output NDX of the NDX counter 302 is incremented by +1 in response to the Bresenham error term update request pulse (BETUD).

When BET <13> is 0, that is, when the Bresenham error term E ≧ 0, the control circuit 202 issues a transfer request signal (TRRQ) and requests the data transfer control unit 134 to transfer data.

At this time, NO obtained by the subtraction circuit
PEL (= | NDX-DX |) is sent to the data transfer control unit 134 as the number of transfer pixels. In the timing chart of FIG. 7, since NDX = STDX + 1 and DX = STDX when BET <13> first becomes 0, the value of NOPEL becomes 1.

Output DX of DX counter 301 (= STD
X) and DY counter 303 output DY (= STD
Y) is sent to the linear address conversion unit 133 as the transfer start XY address, and the video memory 30
Is converted to a start address for data transfer to.

When the transfer request signal (TRRQ) is received,
The data transfer control unit 134 includes the memory control circuit 14
Is used to start a block transfer in which NOPEL + 1 (here, two) pixel data are continuously transferred to the video memory 30, and the pixel data are written to continuous addresses on the video memory 30.

When this data transfer is completed and the transfer ready signal (TRRDY) changes from the active state to the inactive state, the control circuit 202 generates update requests DXUDRQ and DYUDRQ for the X counter 301 and DY counter 303, and The output DY of the DY counter 303 indicating the Y address of each pixel
Output to DX counter 301 while updating to +1
Is incremented by the number of transferred pixels (NOPEL + 1).

Thereafter, the update request DX to the DX counter 301 and the DY counter 303 until BET <13> becomes 0, that is, the Bresenham error term E ≧ 0.
Neither UDRQ nor DYUDRQ is generated, and only the output NDX of the NDX counter 302 is incremented by +1 in response to the Bresenham error term update request pulse (BETUD).

When BET <13> becomes 0, the control circuit 202 issues a transfer request signal (TRRQ),
The data transfer control unit 134 is requested to transfer data. At this time, NOPEL obtained by the subtraction circuit
(Here, NOPEL = 2) is sent to the data transfer control unit 134 as the number of transfer pixels.

The output DX of the DX counter 301 and the output DY of the DY counter 303 at this time are used as the transfer start XY address in the linear address conversion unit 13.
3 is converted into a start address for data transfer to the video memory 30.

When the transfer request signal (TRRQ) is received,
The data transfer control unit 134 includes the memory control circuit 14
Is used to start a block transfer in which NOPEL + 1 (here, three) pixel data are continuously transferred to the video memory 30, and the pixel data are written to continuous addresses on the video memory 30.

When this data transfer is completed and the transfer ready signal (TRRDY) changes from the active state to the inactive state, the control circuit 202 issues update requests DXUDRQ and DYUDRQ to the X counter 301 and DY counter 303, and The output DY of the DY counter 303 indicating the Y address of each pixel
Output to DX counter 301 while updating to +1
Is incremented by the number of transferred pixels (NOPEL + 1).

Then, NDX = LINDX, or DY
= LIMDY, the final transfer signal (LASTTR)
Are sent to the control circuit 202. The control circuit 202 responds to the final transfer signal (LASTTR) with the transfer request signal (T
RRQ) is issued and the data transfer is requested to the data transfer control unit 134. At this time, NOPEL (here, 0) obtained by the subtraction circuit is sent to the data transfer control unit 134 as the number of transfer pixels. Also, D
Output DX of X counter 301 and DY counter 303
Output DY is sent to the linear address conversion unit 133 as a transfer start XY address, and is converted into a start address for data transfer to the video memory 30 there.

When the transfer request signal (TRRQ) is received,
The data transfer control unit 134 includes the memory control circuit 14
Is used to transfer NOPEL + 1 pixel data to the video memory 30, and the pixel data is written on the video memory 30.

When this data transfer is completed and the transfer ready signal (TRRDY) changes from the active state to the inactive state, the control circuit 202 issues a Bresenham error term update request pulse (BETUD). In response to the Bresenham error term update request pulse (BETUD), a pixel count signal (PC
The value of (NT) becomes zero. After that, the control circuit 202 issues a transfer completion signal (TREND) to notify the data transfer control unit 134 that the issuance of all data transfer requests for drawing has been completed.

As described above, even when a line including a horizontal portion is drawn, the number of pixels forming the horizontal line portion is obtained, and data corresponding to the number of pixels is block-transferred to the video memory 30. . Therefore, even in the case of a straight line having a certain inclination, the drawing performance can be significantly improved as compared with the conventional graphics controller.

Regarding the block transfer of the pixels forming the horizontal line segment, the XY address generation circuit 1
It is preferable to utilize the BitBlt function supported by 32 and the pixel data control circuit 134c.

This is a line parameter for designating a horizontal line segment (transfer start coordinates DX, DY, transfer pixel number N).
A value indicating the height of the rectangular area by providing the hardware logic for converting the value of OPEL, the line width) into the parameter values (start point coordinates, width, and height of the rectangular area) corresponding to the BitBlt function in the accelerator 13. Can be realized by substituting for the line width of the line (for example, 1).

Specifically, as shown in FIG. 10, the parameter conversion circuit 501 and the multiplexer 502 may be provided in the accelerator 13. The parameter conversion circuit 501 uses line parameters (transfer start coordinates DX, DY, transfer pixel number NOP) that specify horizontal line segments.
The values of EL and line width) are converted into parameter values (start point coordinates, width, and height of the rectangular area) corresponding to the BitBlt function and output to the multiplexer 502. Multipuku 50
2 normally selects a parameter value for BitBlt transfer from the copro register 131 and sends it to the BitBlt transfer logic.
When set to 31, the output of the parameter conversion circuit 501 is selected and sent to the BitBlt transfer logic instead of the parameter value for BitBlt transfer.

The BitBlt transfer logic operates when either the line drawing command or the BitBlt transfer command is set in the copro register 131. BitB
Since lt is a basic function supported by the graphics controller, by using this BitBlt function, it is possible to block-transfer pixels forming a horizontal line segment without providing dedicated hardware for line transfer. .

[0101]

As described above, according to the present invention, when a horizontal line segment is included in the straight lines requested by the host system for drawing, the number of pixels of the horizontal line segment is counted. , The data of the number of pixels forming each horizontal line segment is collectively transferred to the video memory. Therefore, it is possible to greatly improve the performance of drawing a straight line as compared with the conventional graphics controller which transfers data to the video memory pixel by pixel.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a display control subsystem using a graphics controller according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a graphics accelerator provided in the graphics controller of FIG.

3 is a block diagram showing a configuration of a line drawing circuit provided in the graphics accelerator shown in FIG.

FIG. 4 is a diagram for explaining parameters of the Bresenham algorithm used by the line drawing circuit of FIG. 3;

5 is a flowchart for explaining a coordinate value determination operation using the Bresenham algorithm executed by the line drawing circuit in FIG.

6 is a diagram showing an example of horizontal lines drawn by the line drawing circuit of FIG.

FIG. 7 is a diagram when drawing the horizontal line shown in FIG. 6;
6 is a timing chart for explaining the operation of the line drawing circuit of FIG.

8 is a diagram showing an example of a straight line including a horizontal line portion drawn by the line drawing circuit of FIG.

9 is a timing chart illustrating the operation of the line drawing circuit of FIG. 3 when drawing the line of FIG.

10 is a diagram showing the configuration of a parameter conversion circuit provided in the graphics accelerator of FIG.

[Explanation of symbols]

10 ... Graphics controller, 13 ... Accelerator, 14 ... Memory control circuit, 30 ... Video memory, 13
1 ... Copro register, 132 ... XY address generation unit, 133 ... Linear address conversion unit, 134 ...
Data transfer control unit 132a ... Line drawing circuit,
201 ... Transfer destination XY address arithmetic circuit, 202 ... Control circuit, 203 ... Pixel count circuit, 204 ... Bresenham error term arithmetic circuit, 301 ... DX counter,
302 ... NDX counter, 303 ... DY counter, 30
4 ... Subtractor, 305, 306 ... Comparator, 501 ...
Parameter conversion circuit.

Claims (4)

[Claims] 1. A graphics controller having a bit map format video memory and controlling a display monitor, when drawing a straight line is specified, means for detecting a horizontal line segment included in the straight line. A means for counting the number of pixels forming each horizontal line segment detected, and a plurality of drawing data corresponding to the number of pixels forming each horizontal line segment being block transferred to the video memory And a data transfer means for writing the drawing data to consecutive addresses on the video memory. 2. The means for detecting the horizontal line segment includes means for detecting a pixel position where a vertical coordinate value changes by using Bresenham's argomizm, and the horizontal line segment is detected according to the detected pixel position. The graphics controller according to claim 1, wherein the graphics controller is detected. 3. A BIT for transferring image data to a rectangular area designated by parameter values indicating start point coordinates, width, and height in a graphics controller having a bit map format video memory and controlling a display monitor. Block transfer means, means for detecting a horizontal line segment included in the straight line when drawing of a straight line is specified, and means for counting the number of pixels constituting the horizontal line segment detected And converting the value of the line parameter designating each horizontal line segment into a parameter value for the BIT block transfer, and setting the number of pixels constituting each horizontal line segment in the BIT block transfer means. And a parameter conversion unit for transferring a plurality of corresponding drawing data to the video memory. Box controller. 4. The parameter converting means sets a value of a line parameter for designating a starting point coordinate, a length and a line width of the horizontal line segment, and a BIT for designating a starting point coordinate, a width and a height of the rectangular area. 4. The graphics controller according to claim 3, wherein the graphics controller converts each into a parameter value for block transfer.