JPH08194230A - Liquid crystal display device and its production - Google Patents

Liquid crystal display device and its production

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Publication number
JPH08194230A
JPH08194230A JP371195A JP371195A JPH08194230A JP H08194230 A JPH08194230 A JP H08194230A JP 371195 A JP371195 A JP 371195A JP 371195 A JP371195 A JP 371195A JP H08194230 A JPH08194230 A JP H08194230A
Authority
JP
Japan
Prior art keywords
film
transparent conductive
liquid crystal
display device
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP371195A
Other languages
Japanese (ja)
Other versions
JP3213790B2 (en
Inventor
Etsuko Nishimura
悦子 西村
Masaru Takahata
勝 高畠
Tomoyuki Kiyono
知之 清野
Kenichi Kizawa
賢一 鬼沢
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Abstract

PURPOSE: To eliminate disconnection and short circuiting defects and to improve a yield by improving the adhesion of a stepped part with respect to a transparent conductive film. CONSTITUTION: A nearly randomly oriented polycrystalline indium tin oxide(ITO) film 101 having the ratio of the X-ray diffraction peak intensity of the (400) face to the (222) face in the range of 25 to 75% is used as the transparent conductive film of the liquid crystal display device. Since this film has a film structure densely packed with crystal grains of a uniform size, the interior of the crystal grains and grain boundaries are uniformly etched at the time of patterning the film by a wet etching method, by which a well etched end shape 103 of a forward taper is obtd. Then, the good adhesion of the upper layer film is assured in the case the other film bestrides the difference in level of the transparent conductive film. The penetration of an etchant in the transverse direction of the stepped part is prevented even when the transparent conductive film bestrides the difference in level of the other film and, therefore, the stepwise breakage from the etched ends of the pattern is lessened and the adhesion of the transparent conductive film itself is assured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置及びその製
造方法に係り、特にエッチング端部形状及び段差部分の
付周りが良好な透明導電膜を用いて、歩留りを改善した
液晶表示装置及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device having a yield improved by using a transparent conductive film having a good shape of an etching end portion and a step portion and a liquid crystal display device thereof. The present invention relates to a manufacturing method.

【0002】[0002]

【従来の技術】液晶表示装置においては、透明導電膜を
配線、または画素電極、または端子の一部として使用し
ている。透明導電膜のパタ−ニング方法としては、透明
導電膜を形成後、フォトリソグラフィ−法によりレジス
トパタ−ンを形成し、ウエットエッチングにより膜をパ
タ−ニングする方法が用いられる。
2. Description of the Related Art In a liquid crystal display device, a transparent conductive film is used as a wiring, a pixel electrode, or a part of a terminal. As a method of patterning the transparent conductive film, a method of forming a transparent conductive film, forming a resist pattern by photolithography, and then patterning the film by wet etching is used.

【0003】透明導電膜としては、通常酸化インジウム
に酸化スズが添加された酸化インジウムスズ(ITO)膜
が用いられる。酸化インジウムスズ膜は一般にスパッタ
法により形成されるが、スパッタ方式の違い、スパッタ
パワ−やガス圧、基板温度、雰囲気ガスの種類等により
膜の性質が変わりやすいことが知られている。
As the transparent conductive film, an indium tin oxide (ITO) film in which tin oxide is added to indium oxide is usually used. The indium tin oxide film is generally formed by a sputtering method, but it is known that the properties of the film are likely to change depending on the difference in the sputtering method, the sputtering power, the gas pressure, the substrate temperature, the kind of the atmospheric gas, and the like.

【0004】透明導電膜の膜質の違いは、膜をウエット
エッチングする際のエッチング速度のばらつきの原因と
なるが、最適なエッチング速度を決定する要因が定かで
ないために、透明導電膜のパタ−ニング不良が発生し、
液晶表示装置の歩留りが低下することが知られていた。
The difference in the film quality of the transparent conductive film causes variations in the etching rate when the film is wet-etched, but since the factor that determines the optimum etching rate is not clear, the patterning of the transparent conductive film is performed. A defect occurs,
It has been known that the yield of liquid crystal display devices decreases.

【0005】透明導電膜のウエットエッチングに関し
て、例えば特開平3−166518においては、透明導
電膜を遷移温度以下で形成してアモルファス状態でパタ
−ニング後、遷移温度以上でアニ−ル処理をして多結晶
化することにより、膜のエッチング速度を大きくしてパ
タ−ニングすることが提案されている。
Regarding the wet etching of the transparent conductive film, for example, in JP-A-3-166518, the transparent conductive film is formed below the transition temperature, patterned in an amorphous state, and then annealed at the transition temperature or higher. It has been proposed to increase the etching rate of the film by performing polycrystallization to perform patterning.

【0006】また、酸化インジウムスズ膜は酸化インジ
ウムの結晶構造である立方晶bixbyite型の構造をとるが
(ASTM Card 6−0416)、特開平4−48516にお
いては、特定配向の多結晶膜を形成することにより、膜
のエッチング速度を大きくしてパタ−ニングすることが
提案されている。
The indium tin oxide film has a cubic bixbyite type structure, which is a crystal structure of indium oxide.
(ASTM Card 6-0416) and Japanese Patent Laid-Open No. 4-48516 propose that a polycrystalline film with a specific orientation is formed to increase the etching rate of the film and perform patterning.

【0007】[0007]

【発明が解決しようとする課題】上記従来例のように、
アモルファス状態の膜を用いる、あるいは特定配向の多
結晶膜を用いることにより、透明導電膜のエッチング速
度は大きくなる。
As in the above-mentioned conventional example,
The use of an amorphous film or a polycrystalline film with a specific orientation increases the etching rate of the transparent conductive film.

【0008】しかしながら、実際に膜のエッチング速度
を大きくすると、エッチング時間の制御が難しくなり、
再現性良く透明導電膜パタ−ンを形成することはかえっ
て難しくなる。
However, if the film etching rate is actually increased, it becomes difficult to control the etching time.
It is rather difficult to form a transparent conductive film pattern with good reproducibility.

【0009】また、上記従来例の様にアモルファス状態
でパタ−ニングする場合には、膜中に少しでも結晶成分
を含むとエッチングが不均一となり、エッチング後に残
渣を生じてしまうという問題がある。
Further, in the case of patterning in an amorphous state as in the above-mentioned conventional example, there is a problem that if the film contains a crystal component even a little, the etching becomes non-uniform and a residue is generated after the etching.

【0010】特定配向の多結晶膜を用いる場合において
も同様に、結晶粒界に沿ってエッチングが不均一に進行
するという問題がある。このような膜では、膜厚方向及
び膜の横方向に不均一にエッチングされるため、エッチ
ング端部の形状が膜厚方向に切り立った形状となり、極
端な場合はオ−バ−ハングの逆テ−パ−形状となる。
Similarly, when a polycrystalline film having a specific orientation is used, there is a problem that the etching progresses nonuniformly along the grain boundaries. Since such a film is etched non-uniformly in the film thickness direction and the lateral direction of the film, the shape of the etching end portion becomes sharp in the film thickness direction, and in extreme cases, the reverse hang of the overhang is performed. -It becomes a par shape.

【0011】また膜の横方向の凹凸も激しくなり、パタ
−ンの仕上がり寸法のバラツキも大きくなる。透明導電
膜のパタ−ニング不良は、その上に積層する膜の付周り
不良をも誘発する。液晶表示装置、特にアクティブマト
リックス基板を用いる液晶表示装置においては、透明導
電膜を画素電極、または配線、またはこれらの端子の一
部として使用しているが、透明導電膜パタ−ン上に直
接、または絶縁膜を介して配線、半導体膜等が接続、ま
たは交差する場所では、下層となる透明導電膜パタ−ン
のエッチング端部の段差形状が上述のように膜の断面方
向に切り立った形状であると、上層の配線、半導体、及
び絶縁膜の透明導電膜パタ−ン端部での段差付周りが悪
くなり、断線や短絡不良を生じてしまっていた。
Further, the unevenness of the film in the lateral direction becomes severe, and the variation in the finished size of the pattern also becomes large. The patterning failure of the transparent conductive film also induces the sticking failure of the film laminated thereon. In a liquid crystal display device, particularly a liquid crystal display device using an active matrix substrate, a transparent conductive film is used as a pixel electrode, a wiring, or a part of these terminals, but it is directly on the transparent conductive film pattern. Alternatively, at a place where wiring, a semiconductor film, or the like is connected or intersects via an insulating film, the step shape of the etching end portion of the transparent conductive film pattern serving as the lower layer has a shape that rises in the cross-sectional direction of the film as described above. In such a case, the wiring around the upper layer, the semiconductor, and the insulating film have a poor step around the edges of the transparent conductive film pattern, resulting in disconnection or short circuit.

【0012】また、反対に配線、半導体膜、絶縁膜、ま
たは絶縁膜と半導体膜の積層膜の段差部分を透明導電膜
パタ−ンが乗り越える場所においても、段差部分での前
記透明導電膜自身の付周りが悪いために、段差部分と交
差する透明導電膜パタ−ンのエッチング端部から横方向
に段切れを起し、前記透明導電膜の断線不良を生じてし
まっていた。従って、上記従来例においては、前記透明
導電膜パタ−ンのエッチング端部の形状、及び段差部分
での前記透明導電膜パタ−ン自身の付周りに関して全く
考慮されておらず、結果としてこれを用いる液晶表示装
置の歩留りを低下させる原因となっていた。加えて、ア
モルファス状態の膜では比抵抗、透過率等の透明導電膜
としての基本特性が悪くなるために、エッチング後にア
ニ−ル処理をして多結晶化しなければならず、工程も複
雑化していた。
On the contrary, even when the transparent conductive film pattern crosses over the step portion of the wiring, the semiconductor film, the insulating film, or the laminated film of the insulating film and the semiconductor film, the transparent conductive film itself at the step portion is not formed. Due to poor attachment, a step break was caused in the lateral direction from the etching end of the transparent conductive film pattern intersecting the step portion, resulting in a disconnection defect of the transparent conductive film. Therefore, in the above-mentioned conventional example, no consideration is given to the shape of the etching end of the transparent conductive film pattern and the surrounding of the transparent conductive film pattern itself at the step portion, and as a result, This has been a cause of lowering the yield of the liquid crystal display device used. In addition, since the basic properties of the transparent conductive film such as the specific resistance and the transmittance are deteriorated in the film in the amorphous state, the film must be annealed after the etching to be polycrystallized, which complicates the process. It was

【0013】本発明はこのような事情に鑑みてなされた
ものであり、上述した問題点を解決して歩留りの向上を
図った液晶表示装置及びその製造方法を提供することを
目的とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display device which solves the above-mentioned problems and improves the yield, and a manufacturing method thereof.

【0014】[0014]

【課題を解決するための手段】上記した目的を達成する
ために,本発明では以下の手段を講じた点に特徴があ
る。
In order to achieve the above object, the present invention is characterized in that the following means are taken.

【0015】(1)少なくとも一部に透明導電膜パタ−ン
を設けた液晶表示装置において、前記透明導電膜は、酸
化インジウムに酸化スズが添加された多結晶酸化インジ
ウムスズ(ITO)膜であって、各結晶粒は柱状晶であ
り、各結晶粒の結晶方位は特定方向に偏っていない、す
なわちランダム配向しているものを用いた。
(1) In a liquid crystal display device having a transparent conductive film pattern provided on at least a part thereof, the transparent conductive film is a polycrystalline indium tin oxide (ITO) film in which tin oxide is added to indium oxide. Each crystal grain was a columnar crystal, and the crystal orientation of each crystal grain was not biased in a specific direction, that is, a random orientation was used.

【0016】(2)上記(1)の液晶表示装置において、前
記透明導電膜として、(222)面に対する(400)面の
X線回折ピ−ク強度比が25〜75%の範囲内でランダ
ム配向した多結晶酸化インジウムスズ(ITO)膜を用い
た。
(2) In the liquid crystal display device according to the above (1), the transparent conductive film is random within a range of 25 to 75% in the X-ray diffraction peak intensity ratio of the (400) plane to the (222) plane. An oriented polycrystalline indium tin oxide (ITO) film was used.

【0017】(3)上記(1)、(2)の液晶表示装置におい
て、前記透明導電膜の膜厚は30〜500nmとした。
(3) In the liquid crystal display device of the above (1) and (2), the film thickness of the transparent conductive film is 30 to 500 nm.

【0018】(4)上記(1)〜(3)の液晶表示装置におい
て、前記透明導電膜パタ−ンの端部の段差形状を、テ−
パ−角が45度以下の順テ−パ−形状とした。
(4) In the liquid crystal display device according to any one of (1) to (3) above, the step shape at the end of the transparent conductive film pattern is changed to a tape shape.
The taper was formed into a regular taper shape with a corner angle of 45 degrees or less.

【0019】(5)上記(1)〜(4)の液晶表示装置におい
て、前記透明導電膜の結晶粒径を17〜23nmとし
た。
(5) In the liquid crystal display device according to the above (1) to (4), the crystal grain size of the transparent conductive film is set to 17 to 23 nm.

【0020】(6)上記(1)〜(5)の液晶表示装置にい
て、前記透明導電膜の表面の凹凸を、膜厚に対して30
%以下とした。
(6) In the liquid crystal display device according to the above (1) to (5), the unevenness of the surface of the transparent conductive film is 30 with respect to the film thickness.
% Or less.

【0021】(7)上記(1)〜(6)の液晶表示装置におい
て、前記透明導電膜の酸化スズの添加量は3〜12重量
%とした。
(7) In the liquid crystal display device according to the above (1) to (6), the amount of tin oxide added to the transparent conductive film is 3 to 12% by weight.

【0022】(8)上記(1)〜(7)の液晶表示装置におい
て、前記透明導電膜を配線、または画素電極、または外
部駆動回路との接続のための引出し端子の一部として用
いた。
(8) In the liquid crystal display device according to the above (1) to (7), the transparent conductive film is used as a part of a lead-out terminal for connection with a wiring, a pixel electrode, or an external drive circuit.

【0023】(9)上記(1)〜(8)の液晶表示装置におい
て、前記液晶表示装置の一部に、前記透明導電膜パタ−
ン上の少なくとも一部分に絶縁膜を積層した構造とし
た。
(9) In the liquid crystal display device according to the above (1) to (8), the transparent conductive film pattern is formed in a part of the liquid crystal display device.
The insulating film is laminated on at least a part of the screen.

【0024】(10)上記(1)〜(8)の液晶表示装置にお
いて、前記液晶表示装置の一部に、前記透明導電膜パタ
−ン上の少なくとも一部分に金属膜、合金膜、または金
属シリサイド膜を直接、または絶縁膜を介して積層した
構造とした。
(10) In the liquid crystal display device according to the above (1) to (8), a metal film, an alloy film, or a metal silicide is formed on at least a part of the transparent conductive film pattern in a part of the liquid crystal display device. The film has a structure in which the films are laminated directly or via an insulating film.

【0025】(11)上記(1)〜(8)の液晶表示装置にお
いて、前記液晶表示装置の一部に、前記透明導電膜パタ
−ン上の少なくとも一部分に半導体膜を積層した構造と
した。
(11) In the liquid crystal display device of the above (1) to (8), a semiconductor film is laminated on at least a part of the transparent conductive film pattern in a part of the liquid crystal display device.

【0026】(12)上記(1)〜(8)の液晶表示装置にお
いて、前記液晶表示装置の一部に、絶縁膜の段差部分の
少なくとも一部分を乗り越えるように、前記透明導電膜
パタ−ンを積層した構造とした。
(12) In the liquid crystal display device according to the above (1) to (8), the transparent conductive film pattern is provided in a part of the liquid crystal display device so as to cross over at least a part of the step portion of the insulating film. It has a laminated structure.

【0027】(13)上記(1)〜(8)の液晶表示装置にお
いて、前記液晶表示装置の一部に、金属膜、合金膜、ま
たは金属シリサイド膜の段差部分の少なくとも一部分を
直接、または絶縁膜を介して乗り越えるように、前記透
明導電膜パタ−ンを積層した構造とした。
(13) In the liquid crystal display device according to the above (1) to (8), at least a part of the stepped portion of the metal film, the alloy film, or the metal silicide film is directly or insulated from a part of the liquid crystal display device. The transparent conductive film pattern is laminated so that the transparent conductive film pattern is laminated over the film.

【0028】(14)上記(1)〜(8)の液晶表示装置にお
いて、前記液晶表示装置の一部に、半導体膜、あるいは
絶縁膜上に半導体膜を積層した構造の段差部分の少なく
とも一部分を乗り越えるように、前記透明導電膜パタ−
ンを積層した構造とした。
(14) In the liquid crystal display device according to the above (1) to (8), at least a part of a step portion of a structure in which a semiconductor film or a semiconductor film is laminated on an insulating film is formed on a part of the liquid crystal display device. The transparent conductive film pattern
It has a laminated structure.

【0029】(15)上記(12)〜(14)の液晶表示装置
において、前記透明導電膜パタ−ンが乗り越える段差部
分の形状を、テ−パ−角が90度以下の順テ−パ−形状
とした。
(15) In the liquid crystal display device according to the above (12) to (14), the shape of the step portion over which the transparent conductive film pattern is overlaid is a forward taper having a taper angle of 90 degrees or less. Shaped.

【0030】(16)上記(9)〜(15)の液晶表示装置に
おいて、前記金属膜、合金膜、または金属シリサイド膜
として、Al、Cr、Ta、Ti、Mo等の金属膜、合
金膜、金属シリサイド膜、またはこれらの積層膜を、前
記絶縁膜として窒化シリコン膜、酸化シリコン膜、また
は前記金属の一部表面を酸化して形成した酸化膜、また
はこれらの積層膜を、前記半導体膜として非晶質シリコ
ン、または多結晶シリコン膜をそれぞれ用いた。
(16) In the liquid crystal display device according to any one of (9) to (15), as the metal film, alloy film or metal silicide film, a metal film such as Al, Cr, Ta, Ti or Mo, an alloy film, A metal silicide film or a laminated film of these is used as the insulating film such as a silicon nitride film, a silicon oxide film, or an oxide film formed by oxidizing a part of the surface of the metal, or a laminated film of these is used as the semiconductor film. Amorphous silicon or polycrystalline silicon film was used, respectively.

【0031】(17)上記(1)〜(16)の液晶表示装置の
製造方法において、前記透明導電膜をウエットエッチン
グ法でパタ−ニングした。
(17) In the method for manufacturing a liquid crystal display device according to (1) to (16) above, the transparent conductive film is patterned by a wet etching method.

【0032】(18)上記(17)の液晶表示装置の製造方
法において、前記ウエットエッチング法のエッチャント
として、塩化第二鉄/塩酸溶液、または塩酸、シュウ
酸、ヨウ化水素酸等のハロゲン酸,または王水を用い
た。
(18) In the method of manufacturing a liquid crystal display device according to the above (17), a ferric chloride / hydrochloric acid solution or a halogen acid such as hydrochloric acid, oxalic acid or hydroiodic acid is used as an etchant for the wet etching method. Alternatively, aqua regia was used.

【0033】[0033]

【作用】上記(1)、(2)、(3)、(5)、(6)、(7)の膜
構造の多結晶酸化インジウムスズ膜を液晶表示装置の透
明導電膜として用いることで、上記(4)の良好なエッチ
ング端部形状が容易に得られる。
By using the polycrystalline indium tin oxide film having the film structure of (1), (2), (3), (5), (6) and (7) as a transparent conductive film of a liquid crystal display device, The good etching end shape of the above (4) can be easily obtained.

【0034】また、上記(1)〜(7)の多結晶酸化インジ
ウムスズ膜を透明導電膜として用いる(8)の構成によれ
ば、透明導電膜に係る段差部分の付周りを改善できるた
め、配線の断線、短絡不良を低減でき、歩留りの良い液
晶表示装置が得られる。
Further, according to the constitution (8) in which the polycrystalline indium tin oxide film of the above (1) to (7) is used as the transparent conductive film, the circumference of the step portion of the transparent conductive film can be improved. It is possible to obtain a liquid crystal display device which can reduce disconnection of wiring and a short circuit defect and has a high yield.

【0035】具体的には上記(9)〜(16)の構成によれ
ば、透明導電膜パタ−ン上に絶縁膜、配線、半導体を積
層する場合においても、透明導電膜パタ−ン端部での段
差付周りが良くなり、短絡や断線不良がない液晶表示装
置が得られる。
Specifically, according to the above configurations (9) to (16), even when the insulating film, the wiring, and the semiconductor are laminated on the transparent conductive film pattern, the transparent conductive film pattern end portion is formed. In this case, the stepped area is improved, and a liquid crystal display device without a short circuit or a disconnection defect can be obtained.

【0036】また、絶縁膜、配線、半導体、及び絶縁膜
と半導体膜の積層膜の段差部分を透明導電膜パタ−ンが
乗り越える場合においても、段差部分での前記透明導電
膜自身の付周りが改善されるため、前記透明導電膜の断
線不良がない液晶表示装置が得られる。
Further, even when the transparent conductive film pattern crosses over the step portion of the insulating film, the wiring, the semiconductor, and the laminated film of the insulating film and the semiconductor film, the surrounding of the transparent conductive film itself at the step portion. As a result, it is possible to obtain a liquid crystal display device in which there is no disconnection defect of the transparent conductive film.

【0037】また、(17)、(18)の方法で透明導電膜
をパタ−ニングすることで、(1)〜(16)の液晶表示装
置が歩留り良く得られる。
By patterning the transparent conductive film by the methods (17) and (18), the liquid crystal display devices (1) to (16) can be obtained with a high yield.

【0038】[0038]

【実施例】以下、本発明の実施例を図面を参照して説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0039】本発明の発明者逹が,酸化インジウムスズ
膜の膜構造とエッチング挙動との関係を調査したとこ
ろ、これらの間に強い相関を有することを発見した。実
施例の説明に先立ち、初めに図1〜図4を参照して、膜
の配向性(基板面に対する決勝の成長方位の依存性)、
結晶粒径、表面の凹凸等の膜構造とエッチング端部形
状、エッチング速度、サイドエッチ量との関係について
新たに見出した事実について説明する。
The inventor of the present invention investigated the relationship between the film structure of the indium tin oxide film and the etching behavior, and found that there was a strong correlation between them. Prior to the description of the examples, first, referring to FIGS. 1 to 4, the orientation of the film (dependence of the growth orientation of the final on the substrate surface),
The facts newly found regarding the relationship between the crystal grain size, the film structure such as surface irregularities, the etching edge shape, the etching rate, and the side etching amount will be described.

【0040】図1は多結晶酸化インジウムスズの膜構造
とエッチング端部形状との関係を、膜の配向、具体的に
はX線回折スペクトル測定により得られるピ−ク強度比
に着目してまとめた結果を示している。多結晶酸化イン
ジウムスズ膜はRFスパッタリング法、またはDCスパ
ッタリング法において条件を変えて形成した。例えば、
タ−ゲットは酸化スズの添加量が3〜12重量%の酸化
インジウムスズを用い、スパッタガスはAr、または約
5%の酸素添加Arを用いた。スパッタパワ−は100
〜1000W、スパッタガス圧力は2〜10mTorr、基
板温度180〜350℃とした。膜厚は30〜500nm
である。エッチャントは塩化第二鉄/塩酸溶液、または
塩酸、シュウ酸、ヨウ化水素酸等のハロゲン酸、または
王水を用いた。図1中のエッチング端部の表面形状、及
び断面形状において、符号101は多結晶酸化インジウ
ムスズ膜、102はガラス基板、103は良好なエッチ
ング端部形状を示す部分である。
FIG. 1 summarizes the relationship between the film structure of polycrystalline indium tin oxide and the shape of the etching edge, focusing on the film orientation, specifically, the peak intensity ratio obtained by X-ray diffraction spectrum measurement. The results are shown. The polycrystalline indium tin oxide film was formed by changing the conditions in the RF sputtering method or the DC sputtering method. For example,
The target used was indium tin oxide in which the amount of tin oxide added was 3 to 12% by weight, and the sputtering gas used was Ar or approximately 5% oxygen-added Ar. Sputter power is 100
˜1000 W, sputter gas pressure 2 to 10 mTorr, and substrate temperature 180 to 350 ° C. Film thickness is 30 ~ 500nm
Is. A ferric chloride / hydrochloric acid solution, a halogen acid such as hydrochloric acid, oxalic acid, or hydroiodic acid, or aqua regia was used as the etchant. In the surface shape and sectional shape of the etching end portion in FIG. 1, reference numeral 101 is a polycrystalline indium tin oxide film, 102 is a glass substrate, and 103 is a portion showing a good etching end shape.

【0041】多結晶酸化インジウムスズ膜のエッチング
は結晶粒内、及び結晶粒界に沿って進行するが、結晶粒
界に沿ったエッチングが支配的になると、膜厚方向及び
膜の横方向(膜厚方向に垂直な方向)にエッチングの不均
一を生じるため、良好なエッチング端部形状が得られな
い。具体的には,膜の(222)配向が強くなると(領域
A)、(222)配向粒子が突起状の異常成長を起す。こ
のような膜では粒界に沿ってエッチングが進み、異常成
長粒子104の脱離が起こるためにエッチングが不均一
となり、良好なエッチング端部形状が得られない。エッ
チング端部の断面は逆テ−パ−形状となる。また突起状
の異常成長粒子104のために、膜表面の凹凸が膜厚の
30%以上になり、透過率の低下を招く。
The etching of the polycrystalline indium tin oxide film proceeds in the crystal grains and along the crystal grain boundaries. When the etching along the crystal grain boundaries becomes dominant, the film thickness direction and the lateral direction of the film (film Since a non-uniform etching occurs in the direction perpendicular to the thickness direction), a good etching end shape cannot be obtained. Specifically, when the (222) orientation of the film becomes strong (region A), the (222) oriented particles cause abnormal growth in a projection shape. In such a film, the etching progresses along the grain boundaries, and the abnormal growth particles 104 are desorbed, so that the etching becomes non-uniform and a good etching end shape cannot be obtained. The cross section of the etching end has an inverted taper shape. Further, due to the abnormal growth particles 104 in the shape of protrusions, the unevenness of the film surface becomes 30% or more of the film thickness, and the transmittance is lowered.

【0042】一方、膜の(400)配向が強くなると(領
域C)、結晶粒界105の明瞭な膜となる。この場合に
結晶粒界に沿ってエッチャントがしみ込むため、結晶粒
単位の急激な剥離状エッチングが起り、エッチング端部
形状を全く制御できなくなる。パタ−ンのエッチング端
部は横方向に細かい亀裂状の凹凸106が生じ、端部の
断面も逆テ−パ−形状となる。
On the other hand, when the (400) orientation of the film becomes strong (region C), the film has clear crystal grain boundaries 105. In this case, the etchant permeates along the crystal grain boundaries, causing abrupt peeling etching in crystal grain units, making it impossible to control the etching edge shape at all. At the etching end of the pattern, fine crack-shaped irregularities 106 are generated in the lateral direction, and the cross section of the end also has an inverted taper shape.

【0043】これらのことから逆に、透明導電膜として
基板に対して、各結晶粒の結晶方位が特定方向に偏って
いない、すなわちランダム配向した多結晶酸化インジウ
ムスズ膜を用いることにより、上述のような異常エッチ
ングを防止でき、良好なエッチング端部形状103を得
ることができることがわかる。
On the contrary, by using a polycrystalline indium tin oxide film in which the crystal orientation of each crystal grain is not biased in a specific direction with respect to the substrate as the transparent conductive film, that is, the above-mentioned transparent indium tin oxide film is used. It can be seen that such abnormal etching can be prevented and a good etching edge shape 103 can be obtained.

【0044】このような透明導電膜のランダム配向の度
合いは、(222)面に対する(400)面のX線回折ピ−
ク強度比((400)/(222))が25〜75%の範囲(領
域B)である。この範囲内では均一な大きさの結晶粒が
緻密に充填される膜構造となり、そのため、結晶粒内及
び結晶粒界が均一にエッチングされて、良好なエッチン
グ端部形状103が得られる。この場合のエッチング端
部形状103は、傾斜角45度以下の順テ−パ−とな
る。
The degree of random orientation of such a transparent conductive film is determined by the X-ray diffraction peaks of the (400) plane with respect to the (222) plane.
The intensity ratio ((400) / (222)) is in the range of 25 to 75% (region B). Within this range, a film structure is formed in which crystal grains of uniform size are densely packed, so that the inside of the crystal grains and the crystal grain boundaries are uniformly etched, and a good etching edge shape 103 is obtained. In this case, the etching edge shape 103 is a forward taper having an inclination angle of 45 degrees or less.

【0045】また、結晶粒界に沿ったエッチャントの横
方向のしみ込みがなくなるため、パタ−ン端部に生じる
亀裂状の凹凸106も低減される。下地であるガラス基
板102との密着性も良好である。なお、完全なランダ
ム配向を示す粉末標準試料の(400)/(222)ピ−ク
強度比は30%であり(ASTM Card 6−0416)、良好
なエッチング端部形状103を示す本発明の範囲(領域
B)は、標準試料の0.8〜2.5倍のピ−ク強度比の
範囲内にあたる。
Further, since the etchant is not soaked in the lateral direction along the crystal grain boundaries, the crack-like unevenness 106 generated at the pattern end is also reduced. Adhesion to the glass substrate 102 as the base is also good. The (400) / (222) peak intensity ratio of the powder standard sample showing completely random orientation is 30% (ASTM Card 6-0416), and the range of the present invention showing a good etching edge shape 103. (Region B) is in the range of 0.8 to 2.5 times the peak intensity ratio of the standard sample.

【0046】また、(222)面に対する(400)面以外
の面、例えば(440)面の(222)面に対するX線回折
ピ−ク強度比は、(222)面に対する(400)面のX線
回折ピ−ク強度比の大きさに係らず30〜40%付近で
一定であり、ほぼランダム配向を示していることも追確
認した。なお、完全なランダム配向を示す、粉末標準試
料の(440)/(222)ピ−ク強度比は35%であり(AS
TM Card 6−0416)、30〜40%の範囲は標準試
料の0.85〜1.15倍のピ−ク強度比にあたる。
Further, the intensity ratio of the X-ray diffraction peak to the (222) plane other than the (400) plane, for example, the (440) plane to the (222) plane is X-ray of the (400) plane to the (222) plane. It was additionally confirmed that it was constant in the vicinity of 30 to 40% regardless of the magnitude of the line diffraction peak intensity ratio, and that it showed almost random orientation. The (440) / (222) peak intensity ratio of the powder standard sample showing completely random orientation was 35% (AS
TM Card 6-0416), the range of 30 to 40% corresponds to a peak strength ratio 0.85 to 1.15 times that of the standard sample.

【0047】図2に(400)/(222)ピ−ク強度比と
結晶粒径の関係を示す。(400)/(222)ピ−ク強度
比が本発明の範囲内(領域B)にある膜は、結晶粒径は1
7〜23nmの範囲内であり、均一な大きさの結晶粒が
緻密に充填された膜構造を示している。
FIG. 2 shows the relationship between the (400) / (222) peak intensity ratio and the crystal grain size. A film having a (400) / (222) peak intensity ratio within the range of the present invention (region B) has a crystal grain size of 1
It is within the range of 7 to 23 nm, and shows a film structure in which crystal grains of uniform size are densely packed.

【0048】図3に(400)/(222)ピ−ク強度比と
膜のエッチング速度との関係を、図4に(400)/(22
2)ピ−ク強度比とサイドエッチ量との関係をそれぞ
れ、示す。これらの図において本発明の範囲内(領域B)
の膜のエッチング速度は、50℃の塩化第二鉄/塩酸溶
液(38%FeCl3:36%HCl=1:1)を用いた
場合で1〜4nm/sである。サイドエッチ量は120
sのエッチングで1μm以下である。この範囲を外れる
と、膜のエッチング速度、及びサイドエッチ量は急激に
大きくなり、パタ−ンの寸法精度も急激に低下する。
FIG. 3 shows the relationship between the (400) / (222) peak intensity ratio and the film etching rate, and FIG. 4 shows (400) / (22).
2) The relationship between the peak intensity ratio and the side etch amount is shown. In these figures, within the scope of the present invention (region B)
The etching rate of the film is 1 to 4 nm / s when a ferric chloride / hydrochloric acid solution (38% FeCl 3 : 36% HCl = 1: 1) at 50 ° C. is used. Side etch amount is 120
s is 1 μm or less. If the thickness is out of this range, the etching rate of the film and the amount of side etching increase rapidly, and the dimensional accuracy of the pattern also decreases sharply.

【0049】以上、図1〜図4で説明した酸化インジウ
ムスズ膜の膜構造とエッチング挙動との関係は,検討の
範囲内で酸化インジウムスズの膜厚、及び酸化スズの添
加量には依存しない。例えば、酸化スズの添加量が3〜
12重量%、膜厚が30〜500nmの範囲においても膜
の配向が等しければ同じエッチング挙動を示すことを確
認した。
As described above, the relationship between the film structure and the etching behavior of the indium tin oxide film described with reference to FIGS. 1 to 4 does not depend on the thickness of indium tin oxide and the amount of tin oxide added within the range of investigation. . For example, the addition amount of tin oxide is 3 to
It was confirmed that the same etching behavior is exhibited if the film orientation is the same even in the range of 12% by weight and the film thickness of 30 to 500 nm.

【0050】また、エッチャントとして塩化第二鉄/塩
酸溶液、または塩酸、シュウ酸、ヨウ化水素酸等のハロ
ゲン酸、または王水を用いたが、エッチング速度の絶対
値は変わるものの、得られたエッチング挙動はエッチャ
ントの種類、組成及び濃度、液温には依存しないことを
確認した。
Further, a ferric chloride / hydrochloric acid solution, a halogen acid such as hydrochloric acid, oxalic acid, hydroiodic acid, or aqua regia was used as an etchant, but the absolute value of the etching rate was changed, but it was obtained. It was confirmed that the etching behavior did not depend on the type, composition and concentration of the etchant, and the liquid temperature.

【0051】以下、図5〜図17を用いて、アクティブ
マトリックス基板を例にとり、液晶表示装置において、
透明導電膜が関与する各段差部分の付周りへの本発明の
適用例について説明する。
In the following, referring to FIGS. 5 to 17, taking an active matrix substrate as an example, in a liquid crystal display device,
An example of application of the present invention to the surroundings of each step portion involving the transparent conductive film will be described.

【0052】図5は、上記した透明導電膜をアクティブ
マトリックス基板の一部に利用した、カラ−液晶表示装
置の構成を示した斜視図である。同図において、ガラス
基板102上には前記した透明導電膜からなる画素電極
501、スイッチング素子である薄膜トランジスタ(T
FT)502、TFT502を駆動するための信号を各
TFT502に伝達、保持するための走査配線503、
信号配線504等が形成されてアクティブマトリックス
基板505を構成している。
FIG. 5 is a perspective view showing the structure of a color liquid crystal display device in which the above transparent conductive film is used as a part of an active matrix substrate. In the figure, on the glass substrate 102, the pixel electrode 501 formed of the transparent conductive film and the thin film transistor (T
FT) 502, scanning wiring 503 for transmitting and holding a signal for driving the TFT 502 to each TFT 502,
The signal wiring 504 and the like are formed to form an active matrix substrate 505.

【0053】アクティブマトリックス基板505の表面
には、液晶層506を介して対向電極507上にカラ−
フィルタ508が形成され、カラ−フィルタ508上に
は絶縁基板509が形成されている。前記ガラス基板1
02及び絶縁基板509の外部に露出した主表面には偏
光板510が形成されている。このような構成のアクテ
ィブマトリックス基板では、TFT502を介して画素
電極501へ電圧を印加し、光源からの光を調整するこ
とによってカラ−表示が可能になる。
On the surface of the active matrix substrate 505, a counter electrode 507 is colored through a liquid crystal layer 506.
A filter 508 is formed, and an insulating substrate 509 is formed on the color filter 508. The glass substrate 1
02 and the insulating substrate 509, a polarizing plate 510 is formed on the main surface exposed to the outside. In the active matrix substrate having such a configuration, color display is possible by applying a voltage to the pixel electrode 501 via the TFT 502 and adjusting the light from the light source.

【0054】本実施例では、本発明の透明導電膜を画素
電極501に用いているため、画素電極501が関与す
る段差部分の付周りを改善することができる。この場合
の付周りとしては大別して次の2通りがあるが、そのど
ちらにおいても次の改善効果が得られ、従って段差部分
での断線、短絡不良を低減することができる。画素電
極501の段差を他の膜が乗り越える場合においても、
画素電極501が均一な大きさの結晶粒が緻密に充填さ
れた膜構造となるため、結晶粒内及び結晶粒界が均一に
エッチングされ、画素電極501のエッチング端部は順
テ−パ−の良好なエッチング端部形状となる。これによ
り、画素電極501の段差の上を他の膜が乗り越える場
合においても、良好な付周りが確保できる。反対に他
の膜の段差を画素電極501が乗り越える場合において
も、画素電極501が均一な大きさの結晶粒が緻密に充
填された膜構造となり、結晶粒内及び結晶粒界が均一に
エッチングされるため,結晶粒界に沿ったエッチャント
の横方向のしみ込みを防止でき、従って、パタ−ンの交
差部分のように粒界の生じやすい段差部分においても、
画素電極501のエッチング端部からの段切れを低減で
きる。下地との密着性も良好となり、段差部分での画素
電極501自身の付周りが確保できる。
In this embodiment, since the transparent conductive film of the present invention is used for the pixel electrode 501, it is possible to improve the circumference of the step portion where the pixel electrode 501 is involved. In this case, there are roughly two types of attachments, and the following improvement effects can be obtained in both of them, and therefore disconnection and short circuit defects at the step portion can be reduced. Even when another film gets over the step of the pixel electrode 501,
Since the pixel electrode 501 has a film structure in which crystal grains of a uniform size are densely packed, the inside of the crystal grains and the crystal grain boundaries are uniformly etched, and the etching end portion of the pixel electrode 501 is a normal taper. A good etching edge shape is obtained. Accordingly, even when another film crosses over the step of the pixel electrode 501, good coverage can be secured. On the contrary, even when the pixel electrode 501 crosses the step of another film, the pixel electrode 501 has a film structure in which crystal grains of uniform size are densely packed, and the crystal grains and the crystal grain boundaries are uniformly etched. Therefore, it is possible to prevent the etchant from penetrating in the lateral direction along the crystal grain boundaries, and therefore, even in a step portion where grain boundaries are likely to occur, such as a crossing portion of patterns.
It is possible to reduce disconnection of the pixel electrode 501 from the etching end. Adhesion with the base is also improved, and the periphery of the pixel electrode 501 itself can be secured in the step portion.

【0055】次に、図5で述べたアクティブマトリック
ス基板において、本発明の透明導電膜を、透明導電膜が
関与する各段差部分の付周りに適用した実施例の具体例
を示す。
Next, a specific example of an embodiment in which the transparent conductive film of the present invention is applied to the periphery of each step portion in which the transparent conductive film participates in the active matrix substrate described in FIG. 5 will be described.

【0056】図6は逆スタガ型のTFTをスイッチング
素子に用いたアクティブマトリックス基板の、一画素の
断面の実施例を示す。図6において、ガラス基板102
上の一部にゲ−ト電極601、本発明の透明導電膜から
なる画素電極501が形成され、その上にゲ−ト絶縁膜
602が全面に形成される。ゲ−ト電極601上には、
ゲ−ト絶縁膜602を介してTFT502のチャネル半
導体層となる非晶質シリコン膜603、及びコンタクト
を補償するためにリン等の不純物をド−プした非晶質シ
リコン膜からなる電極層604を積層した島が形成され
る。この島上の一部に、ソ−ス/ドレイン電極605が
形成される。ソ−ス/ドレイン電極605のパタ−ンを
マスクに、不純物をド−プした非晶質シリコン膜からな
る電極層604の一部分が除去され、TFT502のチ
ャネル部分606が形成される。
FIG. 6 shows an embodiment of a cross section of one pixel of an active matrix substrate using a reverse stagger type TFT as a switching element. In FIG. 6, the glass substrate 102
A gate electrode 601 and a pixel electrode 501 made of the transparent conductive film of the present invention are formed on a part of the upper portion, and a gate insulating film 602 is formed on the entire surface thereof. On the gate electrode 601,
An amorphous silicon film 603 to be a channel semiconductor layer of the TFT 502 via an gate insulating film 602 and an electrode layer 604 made of an amorphous silicon film doped with impurities such as phosphorus for compensating for a contact are formed. Stacked islands are formed. A source / drain electrode 605 is formed on a part of the island. Using the pattern of the source / drain electrode 605 as a mask, a part of the electrode layer 604 made of an amorphous silicon film doped with impurities is removed to form a channel portion 606 of the TFT 502.

【0057】また画素電極501上のゲ−ト絶縁膜60
2の一部に開口部607が設けられ,この開口部607
を介して画素電極501とソ−ス/ドレイン電極605
が接続される。
Further, the gate insulating film 60 on the pixel electrode 501.
2 is provided with an opening 607 in a part thereof.
Through the pixel electrode 501 and the source / drain electrode 605.
Is connected.

【0058】さらにTFT502、及び画素電極501
上の全面を覆うように、パッシベ−ション膜608が形
成される。ゲ−ト電極601、及びソ−ス/ドレイン電
極605は、延長部分でそれぞれ図5中の走査配線50
3,信号配線504になる。ゲ−ト電極601、及びソ
−ス/ドレイン電極605は、例えばスパッタリング、
または蒸着法等で形成されたAl、Cr、Ta、Ti、
Mo等の金属,合金または金属シリサイド、またはこれ
らの積層膜で構成されている。
Further, the TFT 502 and the pixel electrode 501
A passivation film 608 is formed so as to cover the entire upper surface. The gate electrode 601 and the source / drain electrode 605 are extended portions, respectively, for the scanning wiring 50 in FIG.
3, signal wiring 504. The gate electrode 601 and the source / drain electrode 605 are formed by, for example, sputtering,
Alternatively, Al, Cr, Ta, Ti formed by a vapor deposition method,
It is composed of a metal such as Mo, an alloy, a metal silicide, or a laminated film thereof.

【0059】ゲ−ト絶縁膜602、及びパッシベ−ショ
ン膜608は、例えばプラズマCVD、またはスパッタ
リング法等で形成された窒化シリコン膜、または酸化シ
リコン膜等の絶縁膜で構成される。ゲ−ト絶縁膜602
は、ゲ−ト電極601、及び走査配線503の一部表面
を酸化して形成しても良い。
The gate insulating film 602 and the passivation film 608 are composed of an insulating film such as a silicon nitride film formed by plasma CVD or a sputtering method, or a silicon oxide film. Gate insulating film 602
May be formed by oxidizing part of the surfaces of the gate electrode 601 and the scanning wiring 503.

【0060】また、これらの酸化膜と窒化シリコン膜、
または酸化シリコン膜等との積層膜で構成しても良い。
Further, these oxide film and silicon nitride film,
Alternatively, it may be formed of a laminated film with a silicon oxide film or the like.

【0061】配線または、ゲ−トチャネル半導体層60
3、及び電極層604は、例えばプラズマCVD法で形
成された非晶質シリコン膜、または熱処理によって多結
晶化した多結晶シリコン膜で構成される。
Wiring or gate channel semiconductor layer 60
3 and the electrode layer 604 are composed of, for example, an amorphous silicon film formed by a plasma CVD method or a polycrystalline silicon film polycrystallized by heat treatment.

【0062】本実施例において、画素電極501のエッ
チング端部の形状609は順テ−パ−の良好なエッチン
グ端部形状となるため、ゲ−ト絶縁膜602を介してソ
−ス/ドレイン電極605のエッチング端部での段差付
周りが良くなり、端部での段切れによる断線不良を防止
できる。
In the present embodiment, the shape 609 of the etching end portion of the pixel electrode 501 is a good etching end shape of the normal taper, and therefore the source / drain electrode is formed through the gate insulating film 602. The area around the stepped portion 605 having a step is improved, and disconnection failure due to step breakage at the edge can be prevented.

【0063】また、画素電極501の反対側のエッチン
グ端部610においても、ゲ−ト絶縁膜602、及びパ
ッシベ−ション膜608の段差付周りが良くなり、端部
での絶縁破壊による短絡不良を防止できる。
Also, in the etching end portion 610 on the opposite side of the pixel electrode 501, the gate insulating film 602 and the passivation film 608 are better provided with steps, so that a short circuit failure due to dielectric breakdown at the end portion is prevented. It can be prevented.

【0064】図7は、図6の実施例における走査配線5
03と信号配線504の交差部分の断面の構成例を示し
ている。同図において走査配線503と信号配線504
はゲ−ト絶縁膜602を挟んで互いに直交している。
FIG. 7 shows the scanning wiring 5 in the embodiment of FIG.
03 shows an example of a cross-sectional configuration of the intersection of the signal line 03 and the signal wiring 504. In the figure, the scanning wiring 503 and the signal wiring 504
Are orthogonal to each other with the gate insulating film 602 interposed therebetween.

【0065】図8は,図6の実施例における走査配線5
03の、外部駆動回路との接続のための引出し端子部分
の断面の構成例を示す。走査配線503の露出部分は、
大気に曝されると容易に腐食されてしまうため、露出部
分を透明導電膜で被覆する端子構成となる。具体的には
ガラス基板102上の一部に走査配線503が形成さ
れ、その上に端子の露出部分を覆うように、本発明の透
明導電膜からなる保護電極801が形成される。
FIG. 8 shows the scanning wiring 5 in the embodiment of FIG.
3 shows an example of a cross-sectional configuration of a lead-out terminal portion for connection with an external drive circuit of No. 03. The exposed portion of the scanning wiring 503 is
Since it is easily corroded when exposed to the air, the exposed part is covered with the transparent conductive film. Specifically, the scanning wiring 503 is formed on a part of the glass substrate 102, and the protective electrode 801 made of the transparent conductive film of the present invention is formed thereon so as to cover the exposed portion of the terminal.

【0066】保護電極801は画素電極と同時に形成さ
れ、ゲ−ト絶縁膜602、及びパッシベ−ション膜60
8は、保護電極801が露出するように、保護電極80
1上の一部分がエッチングにより除去される。
The protective electrode 801 is formed at the same time as the pixel electrode, and has a gate insulating film 602 and a passivation film 60.
8 is a protective electrode 80 so that the protective electrode 801 is exposed.
A part on 1 is removed by etching.

【0067】走査配線503の端部段差部分802にお
いても、透明導電膜からなる保護電極801の付周りが
確保されるため、端子の被覆保護が完全となり、従っ
て、腐食による走査配線503の端子部分での断線を防
止できる。
Even at the end step portion 802 of the scanning wiring 503, the surrounding of the protective electrode 801 made of a transparent conductive film is secured, so that the terminal covering is completely protected, and therefore the terminal portion of the scanning wiring 503 due to corrosion is formed. It is possible to prevent disconnection at.

【0068】図9は、図6の実施例における信号配線5
04の端子部分の断面の構成例を示している。図8で述
べた走査配線503の端子部分の構成と同じ理由で、信
号配線504を露出させることはできない。そこで,走
査配線503を形成する際に、信号配線504の端子部
分に信号配線引出用の引き出し電極901が形成され
る。信号配線504は引き出し電極901に接続され、
引き出し電極901を中継して外部へ露出される。引き
出し電極901の表面には、図8で述べた走査配線50
3の端子部分の構成と同じように、本発明の透明導電膜
からなる保護電極801が形成される。
FIG. 9 shows the signal wiring 5 in the embodiment of FIG.
The example of a cross section of the terminal part 04 is shown. For the same reason as the configuration of the terminal portion of the scanning wiring 503 described in FIG. 8, the signal wiring 504 cannot be exposed. Therefore, when forming the scanning wiring 503, the lead electrode 901 for leading the signal wiring is formed at the terminal portion of the signal wiring 504. The signal wiring 504 is connected to the extraction electrode 901,
The lead electrode 901 is relayed and exposed to the outside. On the surface of the extraction electrode 901, the scanning wiring 50 described in FIG.
The protective electrode 801 made of the transparent conductive film of the present invention is formed in the same manner as in the configuration of the terminal portion 3 of FIG.

【0069】引き出し電極901の端部段差部分902
部分においても、図8と同様に保護電極801の付周り
が確保されるため、腐食による信号配線504の端子部
分での断線を防止できる。
Stepped portion 902 at the end of the extraction electrode 901
As in the case of FIG. 8, the surroundings of the protective electrode 801 are secured in the portion as well, so that disconnection at the terminal portion of the signal wiring 504 due to corrosion can be prevented.

【0070】また、保護電極801のエッチング端部の
段差部分は良好な端部形状が確保されるため、信号配線
504が引き出し電極901へ接続する部分903にお
いても、ゲ−ト絶縁膜602を介した信号配線504の
段切れによる断線を防止できる。
Further, since a good end shape is ensured in the step portion of the etching end portion of the protective electrode 801, even in the portion 903 where the signal wiring 504 is connected to the lead electrode 901, the gate insulating film 602 is interposed. It is possible to prevent disconnection due to disconnection of the signal wiring 504.

【0071】図6〜図9の実施例では、画素電極501
はゲ−ト電極601と同層で、最下層に形成されていた
が、画素電極501はゲ−ト電極601より上層に形成
されてもよい。
In the embodiment shown in FIGS. 6 to 9, the pixel electrode 501 is used.
Is the same layer as the gate electrode 601 and is formed in the lowermost layer, but the pixel electrode 501 may be formed in a layer above the gate electrode 601.

【0072】図10は画素電極501がチャネル半導体
層となる非晶質シリコン膜603と同層にある場合の実
施例である。この場合、画素電極501のエッチング端
部の段差1001をソ−ス/ドレイン電極605が直接
乗り越えることになる。
FIG. 10 shows an embodiment in which the pixel electrode 501 is in the same layer as the amorphous silicon film 603 which becomes the channel semiconductor layer. In this case, the source / drain electrode 605 directly goes over the step 1001 at the etching end of the pixel electrode 501.

【0073】図11は画素電極501がソ−ス/ドレイ
ン電極605の上層にある場合の実施例である。この場
合、図10の実施例とは反対にソ−ス/ドレイン電極6
05の段差1101を画素電極501が直接乗り越える
ことになる。図10、図11のいずれの実施例において
も、本発明の透明導電膜を適用することによりソ−ス/
ドレイン電極605、または画素電極501の断線を防
止できる。
FIG. 11 shows an embodiment in which the pixel electrode 501 is on the upper layer of the source / drain electrode 605. In this case, contrary to the embodiment of FIG. 10, the source / drain electrode 6
The pixel electrode 501 directly crosses over the step 1101 of 05. In any of the embodiments shown in FIGS. 10 and 11, by applying the transparent conductive film of the present invention,
It is possible to prevent disconnection of the drain electrode 605 or the pixel electrode 501.

【0074】図6〜図11の実施例では、本発明の透明
導電膜を画素電極501、及び端子部分の保護電極80
1のみに適用しているが、配線に適用しても良い。
In the embodiments of FIGS. 6 to 11, the transparent conductive film of the present invention is used as the pixel electrode 501 and the protective electrode 80 of the terminal portion.
Although it is applied only to No. 1, it may be applied to wiring.

【0075】図12は、画素電極501と、例えばソ−
ス/ドレイン電極605及び信号配線504を兼用し
て、本発明の透明導電膜を適用した実施例である。図1
2において、1201は画素電極501とソ−ス/ドレ
イン電極605が一体となったパタ−ンである。この場
合、透明導電膜パタ−ン1201は、チャネル半導体層
となる非晶質シリコン膜603、及び不純物をド−プし
た非晶質シリコン膜からなる電極層604を積層した島
パタ−ンの端部1202を直接乗り越えるとともに、ゲ
−ト電極601の端部1203をゲ−ト絶縁膜602、
チャネル半導体層となる非晶質シリコン膜603、及び
不純物をド−プした非晶質シリコン膜からなる電極層6
04を介して乗り越えることになる。透明導電膜を配線
と兼用することにより、透明導電膜が関与する段差の付
周り部分が多くなるが、本発明の透明導電膜を適用する
ことで付周り部分の断線、短絡不良を防止できる。
FIG. 12 shows a pixel electrode 501 and, for example, a source electrode.
This is an example in which the transparent conductive film of the present invention is applied by also using the drain / electrode 605 and the signal wiring 504. FIG.
2, 1201 is a pattern in which the pixel electrode 501 and the source / drain electrode 605 are integrated. In this case, the transparent conductive film pattern 1201 is an end of an island pattern in which an amorphous silicon film 603 to be a channel semiconductor layer and an electrode layer 604 made of an amorphous silicon film doped with impurities are stacked. While directly overcoming the portion 1202, the end portion 1203 of the gate electrode 601 is connected to the gate insulating film 602,
Amorphous silicon film 603 to be a channel semiconductor layer, and electrode layer 6 made of an amorphous silicon film doped with impurities
You will get through 04. By using the transparent conductive film also as the wiring, the surrounding portion of the step involving the transparent conductive film is increased, but by applying the transparent conductive film of the present invention, disconnection and short-circuit failure of the surrounding portion can be prevented.

【0076】図13は、図12の実施例における走査配
線503と信号配線504の交差部分の断面の構成例を
示す。図7で説明したように、走査配線503と信号配
線504はゲ−ト絶縁膜602を挟んで互いに直交する
が、信号配線504に本発明の透明導電膜を適用するこ
とにより、信号配線504の断線不良を防止できる。
図14は、図12の実施例における走査配線503の端
子部分の断面の構成例、図15は、図12の実施例にお
ける信号配線504の端子部分の断面の構成例をそれぞ
れ、示している。
FIG. 13 shows an example of a cross section of the intersection of the scanning wiring 503 and the signal wiring 504 in the embodiment of FIG. As described with reference to FIG. 7, the scanning wiring 503 and the signal wiring 504 are orthogonal to each other with the gate insulating film 602 interposed therebetween. However, by applying the transparent conductive film of the present invention to the signal wiring 504, It is possible to prevent disconnection defects.
FIG. 14 shows a cross-sectional configuration example of the terminal portion of the scanning wiring 503 in the embodiment of FIG. 12, and FIG. 15 shows a cross-sectional configuration example of the terminal portion of the signal wiring 504 in the embodiment of FIG. 12, respectively.

【0077】図14において、透明導電膜からなる保護
電極801は、走査配線の段差部分1401、及びゲ−
ト絶縁膜602の段差部分1402を乗り越えることに
なる。 また、図15において、透明導電膜からなる信
号配線504は、ゲ−ト絶縁膜602の段差部分150
1を乗り越えることになる。図14、図15の実施例の
いずれの場合も、透明導電膜が関与する付周り部分の断
線、短絡不良を防止できる。
In FIG. 14, a protective electrode 801 made of a transparent conductive film is provided with a step portion 1401 of the scanning wiring and a gate.
The step portion 1402 of the insulating film 602 is overcome. Further, in FIG. 15, the signal wiring 504 made of a transparent conductive film is provided with the step portion 150 of the gate insulating film 602.
You will get over 1. In any of the embodiments shown in FIGS. 14 and 15, it is possible to prevent disconnection and short-circuiting defects in the surrounding part involving the transparent conductive film.

【0078】図6〜図15の実施例では、本発明の透明
導電膜を、逆スタガ型のTFTをスイッチング素子に用
いたアクティブマトリックス基板に適用した例を説明し
たが、本発明はこれのみに限定されるものではなく、例
えば正スタガ型のTFT等、異なる構造のTFTを用い
た場合にも適用可能である。
In the embodiments of FIGS. 6 to 15, the transparent conductive film of the present invention is applied to an active matrix substrate using a reverse stagger type TFT as a switching element, but the present invention is not limited to this. The present invention is not limited to this, and can be applied to the case where a TFT having a different structure such as a positive staggered TFT is used.

【0079】図16は正スタガ型のTFTをスイッチン
グ素子に用いたアクティブマトリックス基板の、一画素
の断面の実施例を示す。図16において、ガラス基板1
02上の一部に、層間絶縁膜1601を介して、裏面か
らの光照射を遮るための遮光膜1602を設ける。遮光
膜1602は、例えばスパッタリング、または蒸着法等
で形成されたAl、Cr、Ta、Ti、Mo等の金属、
合金または金属シリサイド膜等で構成されている。
FIG. 16 shows an embodiment of a cross section of one pixel of an active matrix substrate using a positive stagger type TFT as a switching element. In FIG. 16, the glass substrate 1
A light-shielding film 1602 for blocking light irradiation from the back surface is provided on a part of 02 through the interlayer insulating film 1601. The light-shielding film 1602 is made of metal such as Al, Cr, Ta, Ti, Mo formed by, for example, sputtering or vapor deposition,
It is composed of an alloy or a metal silicide film.

【0080】層間絶縁膜1601上には、本発明の透明
導電膜からなる画素電極501、及びソ−ス/ドレイン
電極605が形成される。ソ−ス/ドレイン電極605
の上部表面には、チャネル半導体層603とのコンタク
トを補償するためにリン等の不純物をド−プした電極層
1603が形成される。その上にゲ−ト絶縁膜602を
介して、TFT502のチャネル半導体層となる非晶質
シリコン膜603の島が形成される。この島上の一部に
ゲ−ト電極601が形成される。
A pixel electrode 501 and a source / drain electrode 605 made of the transparent conductive film of the present invention are formed on the interlayer insulating film 1601. Source / drain electrode 605
An electrode layer 1603 doped with impurities such as phosphorus is formed on the upper surface of the substrate to compensate for contact with the channel semiconductor layer 603. An island of an amorphous silicon film 603 which will be a channel semiconductor layer of the TFT 502 is formed on the gate insulating film 602. A gate electrode 601 is formed on a part of this island.

【0081】さらにTFT502、及び画素電極501
上の全面を覆うように、パッシベ−ション膜608が形
成される。ゲ−ト電極601、及びソ−ス/ドレイン電
極605は、延長部分でそれぞれ走査配線503、信号
配線504になる。
Further, the TFT 502 and the pixel electrode 501
A passivation film 608 is formed so as to cover the entire upper surface. The gate electrode 601 and the source / drain electrode 605 become the scanning wiring 503 and the signal wiring 504, respectively, in the extended portions.

【0082】本実施例においても、画素電極501のエ
ッチング端部の形状1604、1605は順テ−パ−の
良好なエッチング端部形状となるため、ソ−ス/ドレイ
ン電極605、ゲ−ト絶縁膜602、及びパッシベ−シ
ョン膜608のエッチング端部での段差付周りが良くな
り、端部での断線、絶縁破壊による短絡不良を防止でき
る。
Also in this embodiment, since the shapes 1604 and 1605 of the etching end portions of the pixel electrode 501 have a good etching end shape of the forward taper, the source / drain electrode 605 and the gate insulation are formed. Around the etching end portions of the film 602 and the passivation film 608, a step difference is improved, and disconnection at the end portions and short circuit defects due to dielectric breakdown can be prevented.

【0083】図17は、図16において画素電極501
と、ソ−ス/ドレイン電極605及び信号配線504を
兼用して、本発明の透明導電膜を適用した実施例であ
る。図17において、1701は画素電極501とソ−
ス/ドレイン電極605が一体となったパタ−ンであ
る。この場合、透明導電膜パタ−ン1701のエッチン
グ端部1702を、チャネル半導体層となる非晶質シリ
コン膜603の島パタ−ンが直接乗り越えることにな
る。
FIG. 17 shows a pixel electrode 501 shown in FIG.
And the source / drain electrode 605 and the signal wiring 504 are also used as the transparent conductive film of the present invention. In FIG. 17, reference numeral 1701 denotes a pixel electrode 501 and a source electrode.
This is a pattern in which the drain / electrode 605 is integrated. In this case, the island pattern of the amorphous silicon film 603 to be the channel semiconductor layer directly crosses over the etching end 1702 of the transparent conductive film pattern 1701.

【0084】また、透明導電膜パタ−ン1701は、層
間絶縁膜1601を介して遮光膜1602の段差部分1
703を乗り越えることになる。本実施例においても、
本発明の透明導電膜を適用することで付周り部分の断
線、短絡不良を防止できる。
In addition, the transparent conductive film pattern 1701 has the step portion 1 of the light shielding film 1602 with the interlayer insulating film 1601 interposed therebetween.
You will get over 703. Also in this embodiment,
By applying the transparent conductive film of the present invention, it is possible to prevent disconnection and short circuit defects in the surrounding portion.

【0085】以上の実施例において、絶縁膜、または金
属膜、合金膜、金属シリサイド膜、または半導体膜、ま
たはこれらの積層膜からなる段差部分での、前記透明導
電膜パタ−ン自身の付周りの改善効果は、透明導電膜パ
タ−ンが乗り越える段差部分の形状に依存し、テ−パ−
角が90度以下の順テ−パ−形状において有効であるこ
とを確認した。
In the above embodiments, the transparent conductive film pattern itself is attached to the step portion formed of an insulating film, a metal film, an alloy film, a metal silicide film, a semiconductor film, or a laminated film thereof. The improvement effect depends on the shape of the step portion that the transparent conductive film pattern gets over, and the taper
It was confirmed that the taper was effective in the normal taper shape having an angle of 90 degrees or less.

【0086】以上の実施例では、本発明の透明導電膜
を、図5に示したカラ−液晶表示装置のアクティブマト
リックス基板505に適用した例を説明したが、本発明
はこれのみに限定されるものではなく、例えば透明導電
膜をパタ−ニングした電極構成を一部に有する液晶表示
装置であれば、本発明を適用することによって、透明導
電膜が関与する段差の付周り改善に対して同様の効果を
得ることができる。
Although the transparent conductive film of the present invention is applied to the active matrix substrate 505 of the color liquid crystal display device shown in FIG. 5 in the above embodiments, the present invention is not limited to this. For example, if the present invention is applied to a liquid crystal display device having a part of an electrode configuration obtained by patterning a transparent conductive film, it is possible to improve the surrounding of a step involving the transparent conductive film. The effect of can be obtained.

【0087】[0087]

【発明の効果】本発明によれば、透明導電膜として、基
板に対してランダム配向した多結晶酸化インジウムスズ
膜を用いることにより、均一な大きさの結晶粒が緻密に
充填される膜構造が得られる。そのため、結晶粒内、及
び結晶粒界が均一にエッチングされて良好なエッチング
端部形状が得られる。これにより透明導電膜パタ−ン上
に絶縁膜、配線、半導体を積層する場合においても、透
明導電膜パタ−ン端部での段差付周りが良くなり、短絡
や断線不良がない液晶表示装置が得られる。
According to the present invention, by using a polycrystalline indium tin oxide film randomly oriented with respect to a substrate as a transparent conductive film, a film structure in which crystal grains of uniform size are densely packed is formed. can get. Therefore, the inside of the crystal grain and the crystal grain boundary are uniformly etched, and a good etching end shape is obtained. As a result, even when the insulating film, the wiring, and the semiconductor are laminated on the transparent conductive film pattern, the step around the edge of the transparent conductive film pattern is improved, and a liquid crystal display device without a short circuit or a disconnection defect is provided. can get.

【0088】また、絶縁膜、配線、半導体、及び絶縁膜
に開口したスル−ホ−ルの段差部分を透明導電膜パタ−
ンが乗り越える場合においても、段差部分での前記透明
導電膜自身の付周りが改善されるため、前記透明導電膜
の断線不良がない液晶表示装置が得られる。
Further, the step portions of the insulating film, the wiring, the semiconductor, and the through hole opened in the insulating film are formed on the transparent conductive film pattern.
Even in the case where the transparent conductive film gets over, the surrounding of the transparent conductive film itself at the step portion is improved, so that a liquid crystal display device without the disconnection defect of the transparent conductive film can be obtained.

【0089】以上のように、本発明によれば前記透明導
電膜が関与する、段差部分での付周りが改善されるた
め、配線の断線、短絡不良を低減でき、歩留りの向上を
図った液晶表示装置が得られる。
As described above, according to the present invention, since the wiring around the step portion, which involves the transparent conductive film, is improved, disconnection of wiring and short circuit defects can be reduced, and the yield is improved. A display device is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】多結晶酸化インジウムスズの膜構造とエッチン
グ端部形状の関係を示す模式図である。
FIG. 1 is a schematic diagram showing a relationship between a film structure of polycrystalline indium tin oxide and a shape of an etching end portion.

【図2】本発明に係る液晶表示装置に使用される多結晶
酸化インジウムスズ膜の(222)面に対する(400)面
のX線回折ピ−ク強度比と結晶粒径の関係を示す説明図
である。
FIG. 2 is an explanatory diagram showing the relationship between the crystal grain size and the X-ray diffraction peak intensity ratio of (400) plane to (222) plane of the polycrystalline indium tin oxide film used in the liquid crystal display device according to the present invention. Is.

【図3】本発明に係る液晶表示装置に使用される多結晶
酸化インジウムスズ膜の(222)面に対する(400)面
のX線回折ピ−ク強度比とエッチング速度の関係を示す
特性図である。
FIG. 3 is a characteristic diagram showing the relationship between the X-ray diffraction peak intensity ratio of the (400) plane to the (222) plane of the polycrystalline indium tin oxide film used in the liquid crystal display device according to the present invention and the etching rate. is there.

【図4】本発明に係る液晶表示装置に使用される多結晶
酸化インジウムスズ膜の(222)面に対する(400)面
のX線回折ピ−ク強度比とサイドエッチ量の関係を示す
特性図である。
FIG. 4 is a characteristic chart showing the relationship between the X-ray diffraction peak intensity ratio of the (400) plane to the (222) plane of the polycrystalline indium tin oxide film used in the liquid crystal display device according to the present invention and the side etch amount. Is.

【図5】透明導電膜としてランダム配向の多結晶酸化イ
ンジウムスズ膜をアクティブマトリックス基板の一部に
用いたカラ−液晶表示装置の一実施例の構成を示す斜視
図である。
FIG. 5 is a perspective view showing a configuration of an example of a color liquid crystal display device using a randomly oriented polycrystalline indium tin oxide film as a transparent conductive film as a part of an active matrix substrate.

【図6】本発明に係る液晶表示装置におけるアクティブ
マトリックス基板の一画素の断面構成の第1の例を示す
断面図である。
FIG. 6 is a sectional view showing a first example of a sectional configuration of one pixel of an active matrix substrate in a liquid crystal display device according to the present invention.

【図7】図6に示す本発明に係る液晶表示装置のアクテ
ィブマトリックス基板における走査配線と信号配線の交
差部分の断面構成例を示す断面図である。
7 is a cross-sectional view showing an example of a cross-sectional configuration of an intersection of a scanning wiring and a signal wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図8】図6に示す本発明に係る液晶表示装置のアクテ
ィブマトリックス基板における走査配線の端子部分の断
面構成例を示す断面図である。
8 is a cross-sectional view showing a cross-sectional configuration example of a terminal portion of a scanning wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図9】図6に示す本発明に係る液晶表示装置のアクテ
ィブマトリックス基板における走査配線の端子部分の断
面構成例を示す断面図である。
9 is a cross-sectional view showing a cross-sectional configuration example of a terminal portion of a scanning wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図10】本発明に係る液晶表示装置におけるアクティ
ブマトリックス基板の一画素の断面構成の第2の例を示
す断面図である。
FIG. 10 is a sectional view showing a second example of the sectional configuration of one pixel of the active matrix substrate in the liquid crystal display device according to the present invention.

【図11】本発明に係る液晶表示装置におけるアクティ
ブマトリックス基板の一画素の断面構成の第3の例を示
す断面図である。
FIG. 11 is a sectional view showing a third example of the sectional configuration of one pixel of the active matrix substrate in the liquid crystal display device according to the present invention.

【図12】本発明に係る液晶表示装置におけるアクティ
ブマトリックス基板の一画素の断面構成の第4の例を示
す断面図である。
FIG. 12 is a sectional view showing a fourth example of the sectional configuration of one pixel of the active matrix substrate in the liquid crystal display device according to the present invention.

【図13】図12に示す本発明に係る液晶表示装置のア
クティブマトリックス基板における走査配線と信号配線
の交差部分の断面構成例を示す断面図である。
13 is a cross-sectional view showing an example of a cross-sectional configuration of an intersection of a scanning wiring and a signal wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図14】図12に示す本発明に係る液晶表示装置のア
クティブマトリックス基板における走査配線の端子部分
の断面構成例を示す断面図である。
14 is a cross-sectional view showing a cross-sectional configuration example of a terminal portion of a scanning wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図15】図12に示す本発明に係る液晶表示装置のア
クティブマトリックス基板における信号配線の端子部分
の断面構成例を示す断面図である。
15 is a cross-sectional view showing a cross-sectional configuration example of a terminal portion of a signal wiring in the active matrix substrate of the liquid crystal display device according to the present invention shown in FIG.

【図16】本発明に係る液晶表示装置におけるアクティ
ブマトリックス基板の一画素の断面構成の第5の例を示
す断面図である。
FIG. 16 is a sectional view showing a fifth example of the sectional configuration of one pixel of the active matrix substrate in the liquid crystal display device according to the present invention.

【図17】本発明に係る液晶表示装置におけるアクティ
ブマトリックス基板の一画素の断面構成の第6の例を示
す断面図である。
FIG. 17 is a sectional view showing a sixth example of the sectional configuration of one pixel of the active matrix substrate in the liquid crystal display device according to the present invention.

【符号の説明】[Explanation of symbols]

101 多結晶酸化インジウムスズ(ITO)膜 102 ガラス基板 103 良好なエッチング端部形状を示す部分 104 異常成長粒子 105 結晶粒界 501 画素電極 502 TFT 503 走査配線 504 信号配線 505 アクティブマトリックス基板 506 液晶層 507 対向電極 508 カラ−フィルタ 509 絶縁基板 510 偏向板 601 ゲ−ト電極 602 ゲ−ト絶縁膜 603 非晶質シリコン膜 604 不純物をド−プした非晶質シリコン膜 605 ソ−ス/ドレイン電極 606 TFTのチャネル部分 607 開口部 608 パッシベ−ション膜 801 端子部分の保護電極 901 端子部分の引き出し電極 1201 透明導電膜パタ−ン 1701 透明導電膜パタ−ン 1601 層間絶縁膜 1602 遮光膜, 1603 不純物をド−プした電極層 101 Polycrystalline Indium Tin Oxide (ITO) Film 102 Glass Substrate 103 Part Showing Good Etching Edge Shape 104 Abnormal Growth Particles 105 Crystal Grain Boundary 501 Pixel Electrode 502 TFT 503 Scanning Wiring 504 Signal Wiring 505 Active Matrix Substrate 506 Liquid Crystal Layer 507 Counter electrode 508 Color filter 509 Insulating substrate 510 Deflection plate 601 Gate electrode 602 Gate insulating film 603 Amorphous silicon film 604 Amorphous silicon film doped with impurities 605 Source / drain electrode 606 TFT Channel part 607 Opening part 608 Passivation film 801 Terminal part protection electrode 901 Terminal part extraction electrode 1201 Transparent conductive film pattern 1701 Transparent conductive film pattern 1601 Interlayer insulating film 1602 Light shielding film, 1603 Impurity doping Electrode layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鬼沢 賢一 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Onizawa 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (18)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板の一主面上の少なくとも一部に
透明導電膜パタ−ンを設けてなる絶縁基板と、絶縁基板
の一主面上の少なくとも一部に対向電極を設けてなる絶
縁基板を、互いの一主面側が対向するように向い合わせ
て得られる間隙に液晶を挟持した構造を有する液晶表示
装置において、 前記透明導電膜は、酸化インジウムに酸化スズが添加さ
れた多結晶酸化インジウムスズ(ITO)膜であって、各
結晶粒は柱状晶であり、ランダム配向していることを特
徴とする液晶表示装置。
1. An insulating substrate having a transparent conductive film pattern provided on at least a part of a main surface of an insulating substrate, and an insulating substrate having a counter electrode provided on at least a part of the main surface of the insulating substrate. In a liquid crystal display device having a structure in which liquid crystal is sandwiched in a gap obtained by facing the substrates so that their main surfaces are opposed to each other, the transparent conductive film is polycrystalline oxide in which tin oxide is added to indium oxide. A liquid crystal display device, which is an indium tin (ITO) film, in which each crystal grain is a columnar crystal and is randomly oriented.
【請求項2】 前記透明導電膜として、(222)面に対
する(400)面のX線回折ピ−ク強度比が25〜75%
の範囲内でランダム配向した多結晶酸化インジウムスズ
(ITO)膜を用いたことを特徴とする請求項1に記載の
液晶表示装置。
2. The transparent conductive film has an X-ray diffraction peak intensity ratio of (400) plane to (222) plane of 25 to 75%.
Randomly oriented polycrystalline indium tin oxide in the range
The liquid crystal display device according to claim 1, wherein an (ITO) film is used.
【請求項3】 前記透明導電膜の膜厚は、30〜500
nmであることを特徴とする請求項1または2のいずれ
かに記載の液晶表示装置。
3. The transparent conductive film has a thickness of 30 to 500.
The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a thickness of nm.
【請求項4】 前記透明導電膜パタ−ンの端部の段差形
状は、テ−パ−角が45度以下の順テ−パ−形状である
ことを特徴とする請求項1乃至3のいずれかに記載の液
晶表示装置。
4. The step shape of the end portion of the transparent conductive film pattern is a forward taper shape having a taper angle of 45 degrees or less. The liquid crystal display device according to claim 1.
【請求項5】 前記透明導電膜の結晶粒径は、17〜2
3nmであることを特徴とする請求項1乃至4のいずれ
かに記載の液晶表示装置。
5. The crystal grain size of the transparent conductive film is 17-2.
It is 3 nm, The liquid crystal display device in any one of Claim 1 thru | or 4 characterized by the above-mentioned.
【請求項6】 前記透明導電膜の表面の凹凸は、膜厚に
対して30%以下であることを特徴とする請求項1乃至
5のいずれかに記載の液晶表示装置。
6. The liquid crystal display device according to claim 1, wherein the unevenness on the surface of the transparent conductive film is 30% or less with respect to the film thickness.
【請求項7】 前記透明導電膜の酸化スズの添加量は、
3〜12重量%であることを特徴とする請求項1乃至6
のいずれかに記載の液晶表示装置。
7. The amount of tin oxide added to the transparent conductive film is
The amount is 3 to 12% by weight.
The liquid crystal display device according to any one of 1.
【請求項8】 前記透明導電膜を配線、または画素電
極、または外部駆動回路との接続のための引出し端子の
一部として用いたことを特徴とする請求項1乃至7のい
ずれかに記載の液晶表示装置。
8. The method according to claim 1, wherein the transparent conductive film is used as a wiring, a pixel electrode, or a part of a lead terminal for connection with an external driving circuit. Liquid crystal display device.
【請求項9】 前記透明導電膜パタ−ン上の少なくとも
一部分に絶縁膜を積層した構造を有することを特徴とす
る請求項1乃至8のいずれかに記載の液晶表示装置。
9. The liquid crystal display device according to claim 1, which has a structure in which an insulating film is laminated on at least a part of the transparent conductive film pattern.
【請求項10】 前記透明導電膜パタ−ン上の少なくと
も一部分に金属膜、合金膜、または金属シリサイド膜を
直接、または絶縁膜を介して積層した構造を有すること
を特徴とする請求項1乃至8のいずれかに記載の液晶表
示装置。
10. A structure in which a metal film, an alloy film, or a metal silicide film is laminated on at least a part of the transparent conductive film pattern directly or with an insulating film interposed therebetween. 9. The liquid crystal display device according to any one of 8.
【請求項11】 前記透明導電膜パタ−ン上の少なくと
も一部分に半導体膜を積層した構造を用いたことを特徴
とする請求項1乃至8のいずかに記載の液晶表示装置。
11. The liquid crystal display device according to claim 1, wherein a structure in which a semiconductor film is laminated on at least a part of the transparent conductive film pattern is used.
【請求項12】 絶縁膜の段差部分の少なくとも一部分
を乗り越えるように、前記透明導電膜パタ−ンを積層し
た構造を有することを特徴とする請求項1乃至8のいず
れかに記載の液晶表示装置。
12. The liquid crystal display device according to claim 1, having a structure in which the transparent conductive film patterns are laminated so as to get over at least a part of the stepped portion of the insulating film. .
【請求項13】 金属膜、合金膜、または金属シリサイ
ド膜の段差部分の少なくとも一部分を直接、または絶縁
膜を介して乗り越えるように、前記透明導電膜パタ−ン
を積層した構造を有することを特徴とする請求項1乃至
8のいずれかに記載の液晶表示装置。
13. A structure in which the transparent conductive film pattern is laminated so as to pass over at least a part of the stepped portion of the metal film, the alloy film, or the metal silicide film directly or via the insulating film. The liquid crystal display device according to any one of claims 1 to 8.
【請求項14】 半導体膜、あるいは絶縁膜上に半導体
膜を積層した構造の段差部分の少なくとも一部分を乗り
越えるように、前記透明導電膜パタ−ンを積層したこと
を特徴とする請求項1乃至8のいずれかに記載の液晶表
示装置。
14. The transparent conductive film pattern is laminated so as to cross over at least a part of a step portion of a structure in which a semiconductor film is laminated on a semiconductor film or an insulating film. The liquid crystal display device according to any one of 1.
【請求項15】 前記透明導電膜パタ−ンが乗り越える
段差部分の形状は、テ−パ−角が90度以下の順テ−パ
−形状であることを特徴とする請求項12乃至14のい
ずれかに記載の液晶表示装置。
15. The stepped portion over which the transparent conductive film pattern rides has a shape of a forward taper having a taper angle of 90 degrees or less. The liquid crystal display device according to claim 1.
【請求項16】 前記金属膜、合金膜、または金属シリ
サイド膜としてAl、Cr、Ta、Ti、Mo等の金属
膜、合金膜、金属シリサイド膜、またはこれらの積層膜
を、前記絶縁膜として窒化シリコン膜、酸化シリコン
膜、または前記金属の一部表面を酸化して形成した酸化
膜、またはこれらの積層膜を、前記半導体膜として非晶
質シリコン、または多結晶シリコン膜をそれぞれ用いた
ことを特徴とする請求項9乃至15のいずかに記載の液
晶表示装置。
16. A metal film of Al, Cr, Ta, Ti, Mo, etc., an alloy film, a metal silicide film, or a laminated film thereof is nitrided as the insulating film as the metal film, alloy film, or metal silicide film. A silicon film, a silicon oxide film, an oxide film formed by oxidizing a part of the surface of the metal, or a laminated film thereof is used as the semiconductor film, which is an amorphous silicon film or a polycrystalline silicon film, respectively. 16. The liquid crystal display device according to claim 9, wherein the liquid crystal display device is a liquid crystal display device.
【請求項17】 上記請求項1〜16の液晶表示装置の
製造方法において,前記透明導電膜をウエットエッチン
グ法でパタ−ニングすることを特徴とする液晶表示装置
の製造方法。
17. The method of manufacturing a liquid crystal display device according to claim 1, wherein the transparent conductive film is patterned by a wet etching method.
【請求項18】 前記ウエットエッチング法のエッチャ
ントとして、塩化第二鉄/塩酸溶液、または塩酸、シュ
ウ酸、ヨウ化水素酸等のハロゲン酸、または王水を用い
たことを特徴とする請求項17に記載の液晶表示装置の
製造方法。
18. The ferric chloride / hydrochloric acid solution, a halogen acid such as hydrochloric acid, oxalic acid, or hydroiodic acid, or aqua regia is used as the etchant for the wet etching method. A method for manufacturing a liquid crystal display device according to item 1.
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