JPH081926B2 - Method for manufacturing isolation groove - Google Patents

Method for manufacturing isolation groove

Info

Publication number
JPH081926B2
JPH081926B2 JP5900489A JP5900489A JPH081926B2 JP H081926 B2 JPH081926 B2 JP H081926B2 JP 5900489 A JP5900489 A JP 5900489A JP 5900489 A JP5900489 A JP 5900489A JP H081926 B2 JPH081926 B2 JP H081926B2
Authority
JP
Japan
Prior art keywords
groove
silicate glass
semiconductor substrate
manufacturing
bpsg3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5900489A
Other languages
Japanese (ja)
Other versions
JPH02238647A (en
Inventor
浩 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5900489A priority Critical patent/JPH081926B2/en
Publication of JPH02238647A publication Critical patent/JPH02238647A/en
Publication of JPH081926B2 publication Critical patent/JPH081926B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置における絶縁分離溝の製造方法に
関し、特に溝内にシリコン酸化物からなる絶縁材料を充
填した絶縁分離溝の製造方法に関する。
The present invention relates to a method for manufacturing an insulation separation groove in a semiconductor device, and more particularly to a method for manufacturing an insulation separation groove in which a groove is filled with an insulating material made of silicon oxide.

〔従来の技術〕[Conventional technology]

従来のこの種の製造方法の一例を第3図(a)及び
(b)の縦断面図に示す。
An example of a conventional manufacturing method of this type is shown in the vertical sectional views of FIGS. 3 (a) and 3 (b).

先ず、同図(a)のように、半導体基板1の素子を絶
縁分離する目的で作られた溝2にホウ素・リン・ケイ酸
ガラス(BPSG)3を気相成長法により堆積させる。この
とき、BPSG3は、例えばテトラエチル・オルソ・ケイ酸
塩(Si(OC2H5)を主原料としてトリメチル・ホウ
酸塩(B(OCH3)とフォスフィン(PH3)と酸素(O
2)とを混合させて減圧状態で熱分解させ、形成させる
ことが可能である。
First, as shown in FIG. 3A, boron-phosphorus-silicate glass (BPSG) 3 is deposited by vapor phase growth method in a groove 2 formed for the purpose of insulating and separating the elements of the semiconductor substrate 1. At this time, oxygen BPSG3, for example tetraethyl ortho-silicate and (Si (OC 2 H 5) 4) and trimethyl borate as the main raw material (B (OCH 3) 3) and phosphine (PH 3) ( O
2 ) and can be mixed and pyrolyzed under reduced pressure to form.

この場合、一般的には同図(a)で示すようなボイド
4が溝2の内部に発生する。しかしながら、この状態で
900〜1000℃の熱処理を行うと、同図(b)のように、
ボイド4は消滅し、溝2の内部はBPSG3によって完全に
充填される。
In this case, generally, a void 4 as shown in FIG. However, in this state
When heat treatment at 900-1000 ℃ is performed, as shown in Fig.
The void 4 disappears and the inside of the groove 2 is completely filled with BPSG3.

その後、半導体基板1の表面に存在しているBPSG3を
エッチング除去することで絶縁分離溝が製造される。
After that, BPSG3 existing on the surface of the semiconductor substrate 1 is removed by etching to manufacture the insulating separation groove.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来の製造方法では、溝2の内部をBPSG3に
よって充填させる際に生じるボイド4をその後の熱処理
時に消滅させているが、この消滅に際しては溝2の上部
に存在するBPSG3がボイド4を埋込んでしまう機構とな
っている。この結果、溝2内ではボイド4の体積に対応
する量だけ溝2の上部におけるBPSG3の膜厚が薄くな
る。
In the above-described conventional manufacturing method, the void 4 generated when the inside of the groove 2 is filled with BPSG3 is eliminated during the subsequent heat treatment. At the time of this elimination, the BPSG3 existing above the groove 2 fills the void 4. It is a complicated mechanism. As a result, the film thickness of BPSG3 in the upper portion of the groove 2 is thinned in the groove 2 by an amount corresponding to the volume of the void 4.

したがって、第4図(a)で示すように、密に集中し
ている溝12aと疎な溝12bが存在する半導体基板11に適用
した場合には、密に集中している溝12a上のBPSG13の膜
厚が粗な溝12b上の膜厚よりも薄くなる。このため、半
導体基板11上のBPSG3を全てエッチング除去したときに
は、第4図(b)に示すように、密に集中している溝12
aのBPSG13が過度にエッチングされてしまい、この領域
における半導体基板11の表面の凹凸が激しくなる。この
凹凸は半導体基板11の上部に形成される素子に、特に金
属配線の断線などの悪影響をおよぼし半導体装置の信頼
性および製品歩留りの低下を低き起こすことになる。
Therefore, as shown in FIG. 4 (a), when applied to the semiconductor substrate 11 having the densely concentrated grooves 12a and the sparse grooves 12b, the BPSG13 on the densely concentrated grooves 12a is formed. Is thinner than the film thickness on the rough groove 12b. Therefore, when the BPSG3 on the semiconductor substrate 11 is completely removed by etching, as shown in FIG.
The BPSG 13 of a is excessively etched, and the unevenness of the surface of the semiconductor substrate 11 in this region becomes severe. These irregularities adversely affect the elements formed on the semiconductor substrate 11, especially the disconnection of metal wiring, and lower the reliability of the semiconductor device and the reduction in product yield.

本発明は表面の凹凸を生じることがない絶縁分離溝の
製造方法を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing an insulation separation groove that does not cause surface irregularities.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の絶縁分離溝の製造方法は、半導体基板に設け
た溝を含む領域に、シリコン酸化物を主体としかつ不純
物として第3族,第4族,第5族の何れか又はこれらを
組合せた元素を含むケイ酸ガラスを化学的気相成長法に
より形成する工程と、溝内の前記ケイ酸ガラス内に生じ
たボイドが露出するまで該ケイ酸ガラスをエッチング除
去する工程と、熱処理を行って前記ケイ酸ガラスを一旦
溶融させる工程と、全面に前記ケイ酸ガラスと同一又は
異なる不純物を含むケイ酸ガラスを化学的気相成長法に
より形成する工程と、前記半導体基板上のケイ酸ガラス
をエッチング除去する工程とを含んでいる。
According to the method of manufacturing an insulating separation groove of the present invention, in a region including a groove provided in a semiconductor substrate, silicon oxide is mainly used and any one of Group 3, Group 4 and Group 5 as impurities or a combination thereof is used. A step of forming a silicate glass containing an element by chemical vapor deposition, a step of etching and removing the silicate glass until the voids formed in the silicate glass in the groove are exposed, and a heat treatment is performed. A step of once melting the silicate glass, a step of forming a silicate glass containing the same or different impurities as the silicate glass on the entire surface by a chemical vapor deposition method, and etching the silicate glass on the semiconductor substrate And a removing step.

〔作用〕[Action]

上述した製造方法では、溝内にのみケイ酸ガラスを残
した状態で溶融させ、再度ケイ酸ガラスをエッチング除
去するため、各溝は略同一条件で各工程が行われること
になり、溝の密度に関係なくケイ酸ガラスの充填が実現
される。
In the above-described manufacturing method, since the silicate glass is melted only in the grooves and the silicate glass is removed by etching again, each groove is subjected to each step under substantially the same condition, and thus the density of the grooves is increased. Filling of silicate glass is realized regardless of.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a)乃至(d)は本発明の一実施例を製造工
程順に示した縦断面図である。
FIGS. 1A to 1D are vertical sectional views showing an embodiment of the present invention in the order of manufacturing steps.

先ず、同図(a)のように、半導体装置の素子を絶縁
分離する目的で半導体基板1に形成された絶縁分離溝2
内にホウ素・リン・ケイ酸ガラス(BPSG)3を減圧気相
成長法により堆積させる。このBPSG3は従来方法と同様
にテトラエチル・オルソ・ケイ酸塩を主原料としてトリ
メチル・ホウ酸塩とフォスフィンと酸素とを混合させて
熱分解により形成させる。このBPSG3に含まれるホウ素
およびリンの含有量はそれぞれ3〜4重量%,4〜5重量
%になるように形成する。この結果、従来と同様に溝2
の内部にはボイド4が発生する。
First, as shown in FIG. 1A, an insulating separation groove 2 formed in a semiconductor substrate 1 for the purpose of insulating and separating the elements of a semiconductor device.
Boron / phosphorus / silicate glass (BPSG) 3 is deposited therein by a low pressure vapor phase epitaxy method. This BPSG3 is formed by thermal decomposition by mixing trimethyl borate, phosphine and oxygen with tetraethyl orthosilicate as the main raw material as in the conventional method. The BPSG3 is formed so that the contents of boron and phosphorus contained therein are 3 to 4% by weight and 4 to 5% by weight, respectively. As a result, as in the conventional case, the groove 2
A void 4 is generated inside the.

次に、同図(b)のように、半導体基板1の表面のBP
SG3をエッチング除去し、更に溝2内部のボイド4が露
呈されるまで更にエッチングする。
Next, as shown in FIG. 2B, BP on the surface of the semiconductor substrate 1
SG3 is removed by etching, and further etching is performed until the void 4 inside the groove 2 is exposed.

そして、この状態で900〜1000℃の熱処理をおこなう
と、同図(c)のようにBPSG3が流動して溝2内の底側
になだらかな形状で溜り、溝2内部のボイド4は除去さ
れる。
Then, when heat treatment is performed at 900 to 1000 ° C. in this state, BPSG3 flows and accumulates in a gentle shape on the bottom side in the groove 2 as shown in FIG. 2C, and the void 4 inside the groove 2 is removed. It

次に、同図(d)のように、同じ原料から形成されか
つホウ素およびリンの含有量の等しいBPSG5を基板表面
に堆積させる。このとき、前工程までで溝2の実効的な
深さは浅くされているため、溝2の内部にはほとんどボ
イドは発生しない。また、発生しても非常に小さなボイ
ドとなる。その後、900〜1000℃の熱処理を行うとボイ
ドは完全に消滅され、溝2の内部はBPSG3,5によって完
全に充填される。
Next, as shown in FIG. 3D, BPSG5 formed from the same raw material and having the same boron and phosphorus contents is deposited on the substrate surface. At this time, since the effective depth of the groove 2 is shallowed up to the previous step, almost no void is generated inside the groove 2. Moreover, even if it occurs, it becomes a very small void. After that, when heat treatment is performed at 900 to 1000 ° C., the voids are completely eliminated, and the inside of the groove 2 is completely filled with BPSG 3, 5.

なお、その後に半導体基板1の表面に存在しているBP
SG5をエッチング除去することで、溝2内にのみBPSG3,5
が残され、絶縁分離溝の製造が完了する。
After that, BP existing on the surface of the semiconductor substrate 1
By removing SG5 by etching, BPSG3,5 only in the groove 2
Is left, and the manufacturing of the insulating separation groove is completed.

したがって、この製造方法を第2図(a)のように、
密に集中している溝12aと疎な溝12bとを有する半導体基
板11に適用したときには、全ての溝12a,12bにおいて同
一条件で第1図(a)乃至(d)の工程によりBPSG13が
充填されることになり、半導体基板11の表面に形成され
るBPSG15の膜厚は略一定となる。但し、密な溝12aの部
分では、各溝12a内に充填される分が多いだけ、その部
分の膜厚は多少薄くなる。
Therefore, this manufacturing method is performed as shown in FIG.
When applied to the semiconductor substrate 11 having the densely concentrated grooves 12a and the sparse grooves 12b, the BPSG 13 is filled in all the grooves 12a, 12b under the same conditions by the steps of FIGS. 1 (a) to (d). As a result, the film thickness of the BPSG 15 formed on the surface of the semiconductor substrate 11 becomes substantially constant. However, in the dense groove 12a portion, the film thickness of that portion is somewhat thinned because the groove 12a is filled with a large amount.

このため、第2図(b)のように、後工程において半
導体基板11の表面上のBPSG15を全てエッチング除去して
も、いずれの溝12a,12bに対しても略一様にBPSG13,15を
充填でき、半導体基板11表面上の凹凸を非常に小さくで
きる。
Therefore, as shown in FIG. 2B, even if all the BPSG15 on the surface of the semiconductor substrate 11 is removed by etching in the subsequent step, the BPSG13, 15 are substantially evenly formed in any of the grooves 12a, 12b. It can be filled and the irregularities on the surface of the semiconductor substrate 11 can be made very small.

なお、前述した実施例では溝に充填する材料にBPSGを
用いたがホウ素・ケイ酸ガラス,ゲルマニウム・ケイ酸
ガラス又はリン・ケイ酸ガラスを用いて同様の方法で溝
による絶縁分離を行うことも可能である。
Although BPSG was used as the material for filling the groove in the above-described embodiment, it is also possible to perform insulation isolation by the groove in the same manner using boron / silicate glass, germanium / silicate glass or phosphorus / silicate glass. It is possible.

また、リンの不純物原料としてフォスフィンを使用し
たがその代わりにリンを含むアルコラート系、たとえば
トリメチル・リン酸塩(PO(OCH3)を使用してもな
んら問題はない。
Although phosphine was used as an impurity raw material of phosphorus, an alcoholate containing phosphorus, for example, trimethyl phosphate (PO (OCH 3 ) 3 ) may be used instead of phosphine without any problem.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、溝内にのみケイ酸ガラ
スを残した状態でボイドを除去し、再度ケイ酸ガラスを
充填させた上で半導体基板のケイ酸ガラスをエッチング
除去しているため、各溝は夫々同一条件で各工程が実行
されることになり、半導体基板の溝の密度の相違にかか
わらず全ての溝に均等にケイ酸ガラスを充填することが
可能となる。これにより、半導体基板の表面を平坦化
し、半導体装置の設計,製造を容易にし、かつ半導体装
置の信頼性および歩留りが向上できる効果が得られる。
As described above, the present invention removes voids in a state where the silicate glass is left only in the groove, and etches and removes the silicate glass of the semiconductor substrate after filling the silicate glass again. Since each groove is subjected to each process under the same condition, it is possible to uniformly fill all the grooves with silicate glass regardless of the difference in the density of the grooves of the semiconductor substrate. As a result, the surface of the semiconductor substrate can be flattened, the semiconductor device can be easily designed and manufactured, and the reliability and yield of the semiconductor device can be improved.

【図面の簡単な説明】 第1図(a)乃至(d)は本発明の一実施例を製造工程
順に示す縦断面図、第2図(a)及び(b)は第1図の
製造方法を適用した例を製造工程順に示す縦断面図、第
3図(a)及び(b)は従来の製造方法を工程順に示す
縦断面図、第4図(a)及び(b)は第3図の製造方法
を適用した例を製造工程順に示す縦断面図である。 1,11……半導体基板、2,12a,12b……溝、3,13……BPS
G、4,14……ボイド、5,15……BPSG。
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (d) are vertical sectional views showing an embodiment of the present invention in the order of manufacturing steps, and FIGS. 2 (a) and 2 (b) are manufacturing methods of FIG. FIG. 3A is a vertical cross-sectional view showing an example of applying the method in the order of manufacturing steps, FIGS. 3A and 3B are vertical cross-sectional views showing the conventional manufacturing method in the order of steps, and FIGS. 4A and 4B are FIG. FIG. 6 is a vertical cross-sectional view showing an example in which the manufacturing method of is applied in the order of manufacturing steps. 1,11 …… Semiconductor substrate, 2,12a, 12b …… Groove, 3,13 …… BPS
G, 4,14 …… Void, 5,15 …… BPSG.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に設けた溝を含む領域に、シリ
コン酸化物を主体としかつ不純物として第3族,第4
族,第5族の何れか又はこれらを組合せた元素を含むケ
イ酸ガラスを化学的気相成長法により形成する工程と、
溝内の前記ケイ酸ガラス内に生じたボイドが露出するま
で該ケイ酸ガラスをエッチング除去する工程と、熱処理
を行って前記ケイ酸ガラスを一旦溶融させる工程と、全
面に前記ケイ酸ガラスと同一又は異なる不純物を含むケ
イ酸ガラスを化学的気相成長法により形成する工程と、
前記半導体基板上のケイ酸ガラスをエッチング除去する
工程とを含むことを特徴とする絶縁分離溝の製造方法。
1. A semiconductor substrate containing a groove, which is mainly composed of silicon oxide and contains impurities of groups 3 and 4 in a region including a groove.
Forming a silicate glass containing an element of any one of Group 5 and Group 5 or a combination thereof by a chemical vapor deposition method,
The step of etching away the silicate glass until the voids formed in the silicate glass in the groove are exposed, the step of performing heat treatment to once melt the silicate glass, and the same surface as the silicate glass Or a step of forming a silicate glass containing different impurities by a chemical vapor deposition method,
And a step of etching away the silicate glass on the semiconductor substrate.
JP5900489A 1989-03-10 1989-03-10 Method for manufacturing isolation groove Expired - Fee Related JPH081926B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5900489A JPH081926B2 (en) 1989-03-10 1989-03-10 Method for manufacturing isolation groove

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5900489A JPH081926B2 (en) 1989-03-10 1989-03-10 Method for manufacturing isolation groove

Publications (2)

Publication Number Publication Date
JPH02238647A JPH02238647A (en) 1990-09-20
JPH081926B2 true JPH081926B2 (en) 1996-01-10

Family

ID=13100708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5900489A Expired - Fee Related JPH081926B2 (en) 1989-03-10 1989-03-10 Method for manufacturing isolation groove

Country Status (1)

Country Link
JP (1) JPH081926B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831926A (en) * 1994-07-15 1996-02-02 Nec Corp Manufacture of semiconductor device
KR100344766B1 (en) * 1999-10-26 2002-07-19 주식회사 하이닉스반도체 Method for isolating semiconductor devices
KR20020055938A (en) * 2000-12-29 2002-07-10 박종섭 Method of forming a isolation layer deposition in a semiconductor device
WO2002069394A1 (en) * 2001-02-27 2002-09-06 Fairchild Semiconductor Corporation Process for depositing and planarizing bpsg for dense trench mosfet application
US20070132056A1 (en) 2005-12-09 2007-06-14 Advanced Analogic Technologies, Inc. Isolation structures for semiconductor integrated circuit substrates and methods of forming the same

Also Published As

Publication number Publication date
JPH02238647A (en) 1990-09-20

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