JPH081893B2 - Dislocation reduction layer - Google Patents
Dislocation reduction layerInfo
- Publication number
- JPH081893B2 JPH081893B2 JP63110806A JP11080688A JPH081893B2 JP H081893 B2 JPH081893 B2 JP H081893B2 JP 63110806 A JP63110806 A JP 63110806A JP 11080688 A JP11080688 A JP 11080688A JP H081893 B2 JPH081893 B2 JP H081893B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dislocation reduction
- layers
- compound semiconductor
- dislocations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、異種基板上に成長した結晶の転位低減が
可能な転位低減層に関するものである。TECHNICAL FIELD The present invention relates to a dislocation reduction layer capable of reducing dislocations in a crystal grown on a heterogeneous substrate.
第２図はJapanese Journal of Applied Physics VOL.
26,NO7,1987 p1141〜に示された従来の転位低減に用い
られたバッファ層の構造を示す図である。この図におい
て、１はSi基板、２は約２μｍのGaAs層、４は100ÅのG
aAs層、５は最表面のGaAs層、６は100ÅのInxGa1-xAs層
である。Figure 2 shows the Japanese Journal of Applied Physics VOL.
26, NO7, 1987 p1141 to FIG. 14 is a diagram showing a structure of a conventional buffer layer used for dislocation reduction. In this figure, 1 is a Si substrate, 2 is a GaAs layer of about 2 μm, and 4 is a 100 Å G.
The aAs layer, 5 is the outermost GaAs layer, and 6 is the 100 Å In x Ga 1-x As layer.
次に、その作用について説明する。 Next, the operation will be described.
Si基板１上に成長された約２μｍのGaAs層２はアニー
ルによって107cm-2程度まで転位が低減されている。そ
して、この上にはGaAs層２よりも格子定数のわずかに大
きいInxGa1-xAs層６が100Å成長され、さらに、交互に1
00ÅのGaAs層４と100ÅのInxGa1-xAs層６が成長されて
いる。このため、転位はこの交互層間の張力によって曲
げられ、成長方向への転位の伝搬は減少している。この
場合、効果の大きいInの組成比ｘは0.06％以上であり、
その層数は10層であった。The GaAs layer 2 of about 2 μm grown on the Si substrate 1 has the dislocations reduced to about 10 7 cm −2 by annealing. Then, an In x Ga 1-x As layer 6 having a lattice constant slightly larger than that of the GaAs layer 2 is grown on this by 100Å, and further, 1
A 00Å GaAs layer 4 and a 100Å In x Ga 1-x As layer 6 are grown. Therefore, the dislocations are bent by the tension between the alternating layers, and the propagation of the dislocations in the growth direction is reduced. In this case, the composition ratio x of In having a large effect is 0.06% or more,
The number of layers was 10.
上記のような従来の転位低減用のバッファ層は、InxG
a1-xAa層６とGaAs層４の総厚みは1000Åと厚く、臨界膜
厚を越えており、GaAs層２とSi基板１との界面からの転
位は低減するものの、GaAs層５とInxGa1-xAs層６との界
面で新たな転位が発生しているため十分な転位低減効果
が得られないという問題点があった。また、この場合、
クロスハッチモホロジとなるために、転位とは異なる点
欠陥の問題が生じていた。The conventional buffer layer for dislocation reduction as described above is In x G
The total thickness of the a 1-x Aa layer 6 and the GaAs layer 4 is as thick as 1000Å, which exceeds the critical thickness, and although dislocations from the interface between the GaAs layer 2 and the Si substrate 1 are reduced, Since new dislocations are generated at the interface with the x Ga 1-x As layer 6, there is a problem that a sufficient dislocation reduction effect cannot be obtained. Also in this case,
Due to the crosshatch morphology, there was a problem of point defects different from dislocations.
この発明は、かかる課題を解決するためになされたも
ので、最表面層と転位低減層との間での新たな転位の発
生を防ぐとともに、クロスハッチの発生しない結晶が得
られる転位低減層を得ることを目的とする。The present invention has been made in order to solve the above problems, and a dislocation reduction layer that prevents the generation of new dislocations between the outermost surface layer and the dislocation reduction layer and obtains a crystal without crosshatch The purpose is to get.
この発明に係る転位低減層は、基板上に異種の化合物
半導体層と、この化合物半導体層とわずかに格子定数の
異なる半導体層とを交互に成長させて構成される転位低
減層の化合物半導体層と半導体層間の格子定数差を最表
面層に向って次第に少なくしたものである。A dislocation reduction layer according to the present invention is a compound semiconductor layer of a dislocation reduction layer formed by alternately growing different kinds of compound semiconductor layers on a substrate and semiconductor layers having a slightly different lattice constant from the compound semiconductor layer. The difference in lattice constant between the semiconductor layers is gradually reduced toward the outermost surface layer.
この発明においては、最表面層と転位低減層との間で
新たな転位が発生しなくなり、また、クロスハッチも発
生しなくなる。In the present invention, new dislocations do not occur between the outermost surface layer and the dislocation reduction layer, and crosshatch does not occur.
第１図はこの発明の転位低減層の一実施例を示す図で
ある。この図において、第２図と同一符号は同一のもの
を示し、３は100ÅのInxGa1-xAs層で、Inの組成比ｘが
下から最表面層に向って、例えば0.12〜0.01（12％〜１
％）としだいに小さくなっている。FIG. 1 is a diagram showing an embodiment of the dislocation reduction layer of the present invention. In this figure, the same symbols as those in FIG. 2 indicate the same things, and 3 is a 100 Å In x Ga 1-x As layer, the composition ratio x of In is from the bottom to the outermost surface layer, for example, 0.12 to 0.01 (12% to 1
%) And become smaller gradually.
次に作用について説明する。 Next, the operation will be described.
この発明のものも従来のものと同様に、Si基板１上に
成長された約２μｍのGaAs層２が、アニールによって10
7cm-2程度まで転位が低減されている。しかし、この発
明ではこの後この上にInの組成比ｘを次第に減じながら
InxGa1-xAs層３とGaAs層４を交互に成長させている。す
なわち、このようにGaAs層２とInxGa1-xAs層３との界面
でInの組成比ｘを0.12と充分大きくすれば、下からの伝
搬転位は充分曲げられ、また、最表面のGaAs層５とInxG
a1-xAs層３との界面でInの組成比ｘを0.01として格子の
ずれを小さくすれば、新たな転位の発生やクロスハッチ
ホモロジの発生もなくなり、良好なGaAs層５が得られ
る。In the present invention as well as the conventional one, the GaAs layer 2 of about 2 μm grown on the Si substrate 1 is annealed by annealing.
Dislocations are reduced to about 7 cm -2 . However, in the present invention, after that, the In composition ratio x is gradually reduced on top of this.
In x Ga 1-x As layers 3 and GaAs layers 4 are grown alternately. That is, if the composition ratio x of In at the interface between the GaAs layer 2 and the In x Ga 1-x As layer 3 is made sufficiently large as 0.12 in this way, propagating dislocations from below can be sufficiently bent, and GaAs layer 5 and In x G
If the composition ratio x of In is set to 0.01 at the interface with the a 1-x As layer 3 to reduce the lattice shift, new dislocations and crosshatch homology are eliminated, and a good GaAs layer 5 is obtained. .
なお、上記実施例ではIII−Ｖ族の化合物半導体とし
てGaAaを用いたが、他のIII−Ｖ族化合物半導体とし
て、例えばInPを用いた場合でも、また、これらの混晶
を用いた場合でも同様である。また、転位低減層もInxG
a1-xAs-GaAsの交互の層のみでなく、格子定数差があれ
ば他の混晶交互層を用いることも可能である。Although GaAa was used as the III-V group compound semiconductor in the above-described examples, the same applies when InP is used as another III-V group compound semiconductor, or when a mixed crystal thereof is used. Is. In addition, the dislocation reduction layer also has In x G
Not only alternating layers of a 1-x As-GaAs but other mixed crystal alternating layers can be used if there is a difference in lattice constant.
この発明は以上説明したとおり、基板上に異種の化合
物半導体層と、この化合物半導体層とわずかに格子定数
の異なる半導体層とを交互に成長させて構成される転位
低減層の化合物半導体層と半導体層間の格子定数差を最
表面層に向って次第に少なくしたので、新たな転位を発
生させることなく転位を充分低減でき、クロスハッチモ
ホロジのない良好な結晶を得ることが可能になるという
効果がある。As described above, the present invention is directed to a compound semiconductor layer and a semiconductor of a dislocation reducing layer formed by alternately growing different kinds of compound semiconductor layers on a substrate and semiconductor layers having slightly different lattice constants from the compound semiconductor layer. Since the difference in lattice constant between the layers is gradually reduced toward the outermost surface layer, dislocations can be sufficiently reduced without generating new dislocations, and it is possible to obtain a good crystal without crosshatch morphology. is there.
第１図はこの発明の転位低減層の一実施例の構造を示す
図、第２図は従来の転位低減層の構造を示す図である。 図において、１はSi基板、2,4,5はGaAs層、３はこの発
明のInxGa1-xAs層である。 なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a diagram showing the structure of an embodiment of the dislocation reducing layer of the present invention, and FIG. 2 is a diagram showing the structure of a conventional dislocation reducing layer. In the figure, 1 is a Si substrate, 2, 4 and 5 are GaAs layers, and 3 is an In x Ga 1-x As layer of the present invention. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
合物半導体層とわずかに格子定数の異なる半導体層とを
交互に成長させて構成される転位低減層において、前記
化合物半導体層と前記半導体層間の格子定数差を最表面
層に向って次第に少なくしたことを特徴とする転位低減
層。1. A dislocation reduction layer formed by alternately growing different kinds of compound semiconductor layers on a substrate and semiconductor layers having slightly different lattice constants from the compound semiconductor layers, wherein the compound semiconductor layer and the semiconductor A dislocation reduction layer characterized in that the difference in lattice constant between layers is gradually reduced toward the outermost surface layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110806A JPH081893B2 (en) | 1988-05-07 | 1988-05-07 | Dislocation reduction layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63110806A JPH081893B2 (en) | 1988-05-07 | 1988-05-07 | Dislocation reduction layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01281719A JPH01281719A (en) | 1989-11-13 |
| JPH081893B2 true JPH081893B2 (en) | 1996-01-10 |
Family
ID=14545129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63110806A Expired - Lifetime JPH081893B2 (en) | 1988-05-07 | 1988-05-07 | Dislocation reduction layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH081893B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3616745B2 (en) * | 1994-07-25 | 2005-02-02 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61104611A (en) * | 1984-10-27 | 1986-05-22 | Matsushita Electric Ind Co Ltd | Si substrate with iii-v group compound single crystal thin film and manufacture thereof |
-
1988
- 1988-05-07 JP JP63110806A patent/JPH081893B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01281719A (en) | 1989-11-13 |
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