JPH08186485A - Switch circuit for monolithic microwave integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a depletion-type MOSFET switch circuit operated with a positive voltage as to an ultrahigh frequency monolithic integrated circuit to which only a positive power supply voltage is applied. CONSTITUTION: The circuit is provided with a depletion-type 1st MOSFET 201 whose gate receives an input signal and whose drain provides an output of an output signal, a 2nd MOSFET 203 whose source connects to the source of the 1st MOSFET 201 and whose gate connects to an interruption adjustment power supply Vc, and a 3rd MOSFET 205 whose drain connects to the sources of the 1st and 2nd MOSFETs 201, 203, whose source and gate connect respectively to ground and acting like a constant current source.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a gallium arsenide (GaAs) metal-semiconductor field effect transistor-as an active element.
(Metal-semiconductor field effect transistor: M
OSFET) monolithic microwave integrated circuits (M)
MIC) and the like for a switch circuit for the intermittence of the input signal, particularly a depletion-type n-channel MOSFET (used in a circuit which allows only a positive power supply voltage (positive voltage) supply). de
pletion mode n-channel metal oxide semiconductor f
ield effect transistor) is a switch circuit composed of.

[0002]

2. Description of the Related Art In the case where only a positive power supply voltage is allowed from an MMIC, a switch circuit for interrupting an input signal generally has a more complicated structure than a depletion type MOSFET and is difficult to manufacture. Enhancement mode n-channel MOSFETs must be used.

When a depletion type n-channel MOSFET (hereinafter referred to as "D-FET") is used as the switch circuit, a separate negative power supply voltage (ne
supply of gative voltage) is required.

FIG. 1 shows a conventional switch circuit composed of D-FETs.

The conventional technique will be described with reference to FIG.

A conventional switch circuit is a D-FET (10
1), a drain bias resistor (102) connected between the drain of the D-FET (101) and a positive power supply (Vdd), and the source of the D-FET (101) and ground. Self-biasing resistor connected to (103)
And a bypass capacitor (1 connected in parallel with the self-biasing resistor (103) to flow an RF signal to the ground.
04), a power supply (Vc) for intermittent control and the D-FET
It is composed of a gate bias resistor (105) connected to the gate of (101) and an intermittent bias resistor (106) connected to the intermittent adjustment power source (Vc) and ground.

From FIG. 1, reference numerals in and out in the drawings respectively denote an input end to which an input signal is input and an output end to which an output signal is output.

In such a switch circuit, the input signal is applied to the gate of the D-FET (101) and the output signal is D
Obtained from the drain of the FET (101).

In this circuit, the power supply for intermittent control (V
When c) is applied above the critical voltage (Vt) of the D-FET (101), the D-FET (101) is in the amplification mode (amplif).
ication mode), which is a cut-off mode applied below the critical voltage (Vt).

[0010]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since (101) has a negative critical voltage (Vt), in order to implement the switch function, as described above,
It is necessary to supply a negative voltage as the power supply (Vc) for intermittent control.

An object of the present invention is to provide a D-FET switch circuit capable of operating at a positive voltage for an ultra high frequency monolithic integrated circuit to which only a positive power supply voltage is supplied.

[0012]

A switch circuit of the present invention for achieving the above object has a first D having a gate to which an input signal is input and a drain to which an output signal is output.
-FET, a drain bias first resistance of the first D-FET connected between the drain of the first D-FET and a positive power supply (Vdd), and the positive power supply (Vdd)
A second D-FET having a drain connected to the first D-FET, a source connected to the source of the first D-FET, and a gate connected to a power source (Vc) for controlling the interruption, and the second D-FET.
The second D connected between the gate of the FET and the ground
A second resistor for gate bias of the FET, a constant current source between the sources of the first and second D-FETs and the ground, and a third current source between the drain of the third D-FET and the ground. A bypass capacitor connected in parallel with the FET and sending an RF signal to ground, and connected between the gate of the first D-FET and the ground.
It is composed of a third resistor for gate bias of the first D-FET.

In the circuit of the present invention, the constant current source includes a D-FET having a drain connected to the sources of the first and second D-FETs and a source and a gate connected to the ground, respectively.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating the configuration of the switch circuit according to the present invention.

Referring to FIG. 2, the switch circuit of the present invention has a first D-FET (201) whose gate receives an input signal and whose drain outputs an output signal, and whose source is the first D-FET.
A second D-FET (203) connected to the source of the -FET (201), a drain connected to the positive power supply (Vdd), and a gate connected to the intermittent adjustment power supply (Vc);
The drain has first and second D-FETs (201, 20
3) is connected to the source, the source and the gate are respectively connected to ground, and acts as a constant current source.
It includes a D-FET (205).

The first D-FET (20) is provided between the drain of the first D-FET (201) and the positive power source (Vdd).
The first resistor (202) for drain bias of 1) is connected.

A second resistor (204) for gate bias of the second D-FET (203) is connected between the gate of the second D-FET (203) and the ground.

A bias capacitor (206) for flowing an RF signal to the ground is connected in parallel with the third D-FET (205) between the drain of the third D-FET (205) and the ground.

The third resistor (207) for gate bias of the first D-FET (201) is connected between the gate of the first D-FET (201) and the ground.

From FIG. 2, reference numerals in and out in the drawing respectively denote an input end to which an input signal is input and an output end to which an output signal is output.

In the switch circuit of the present invention having such a configuration, first, when the intermittent adjustment power supply voltage (Vc) is 0, the third D-FET acts as a constant current source.
Due to the voltage drop of (205), the first and second D-F
The first D-FET from the source of ET (201, 203)
When a positive bias (Vs) smaller than the absolute value of the critical voltage (Vt) of (201) is applied, the first D-FET
(201) is in the amplification mode and amplifies and outputs the input signal with a predetermined gain.

When the intermittent adjustment power supply voltage (Vc) is increased from such a state, the drain-source current (Ids) of the second D-FET (203) is increased.

At this time, the third D acting as a constant current source
Since the drain-source current (Ids) of the -FET (205) is constant, the drain-source current (Ids) of the first D-FET (201) is the drain-source current (Ids) from the third D-FET (205). ) Must be reduced by the amount of increase.

Therefore, the source voltage (Vs) of the first D-FET (201) increases due to the decrease of the drain-source current (Ids).

At this time, when the source voltage (Vs) of the first D-FET (201) becomes higher than its critical voltage (Vt), the first D-FET (201) is pinched off (pinc).
The output signal is not output from the output end (out) in the h-off) mode.

FIG. 3 shows that the circuit of the present invention has a frequency of 830 MHz.
The characteristics of the power gain when an input signal of z, -30 dBm is provided are illustrated. The gain of the power from the switch-off state is the gain of the power from the switch-on state (-2
28 dB was -30 dB, which is smaller than dB).

[0028]

According to the present invention, it is possible to obtain a D-FET switch circuit capable of operating at a positive voltage for an ultra high frequency monolithic integrated circuit to which only a positive power supply voltage is supplied.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional switch circuit using a depletion type FET.

FIG. 2 is a circuit diagram of a switch circuit using a depletion type FET according to an embodiment of the present invention.

FIG. 3 is a diagram showing a gain characteristic of electric power depending on ON / OFF in the example.

[Explanation of symbols]

 201 1st D-FET 202 1st resistance for drain bias 203 2nd D-FET 205 3rd D-FET 206 Capacitor for bias

 ─────────────────────────────────────────────────── ───Continued from the front page (72) Inventor, Lee Chang-suk, Kunnamaw Apartment, Tunsan-dong, Nishi-gu, Daejeon, Republic of Korea 206-1308 (72) Inventor, Mr. Norimo Park Park, Hanulu, Shinseong-dong, Yuseong-gu, Republic of Korea Part 109-501

Claims (2)

[Claims] 1. A first depletion type MOSFE having a gate to which an input signal is input and a drain to which an output signal is output.
The first depletion type M connected between T (201) and the drain of the first depletion type MOSFET (201) and the positive power source (Vdd).
A first drain bias resistor (202) of the OSFET (201), a drain connected to the positive power supply (Vdd), a source connected to the source of the first depletion type MOSFET (201), and intermittent adjustment. The second depletion type MOSFET (203) having a gate connected to the power supply (Vc) for use, and the second depletion type MOSFET connected to the ground of the gate of the second depletion type MOSFET (203). MOSFET
A second resistor (204) for gate bias of (203), and the first and second depletion type MOSFETs (201, 20)
3) a constant current source (205) connected between the source and the ground, and a constant current source (205) connected in parallel with the constant current source (205) between the constant current source (205) and the ground, A bypass capacitor (206) for flowing an RF signal to the ground, and the first depletion type MOSFET connected between the gate of the first depletion type MOSFET (201) and the ground.
A switch circuit for a monolithic microwave integrated circuit including a third resistor (207) for gate bias of (201). 2. The constant current source (205) has a drain when connected to the sources of the first and second depletion type MOSFETs (201, 203), and a source and a gate connected to the ground, respectively. Depletion type MOSFET
The switch circuit for a monolithic microwave integrated circuit according to claim 1, wherein