JPH04212508A - Cmos amplifier circuit - Google Patents

Abstract

PURPOSE:To offer the CMOS amplifier circuit to obtain an enough amplifying gain even in a high frequency area by eliminating negative feedback. CONSTITUTION:The output terminal of a second CMOS inverted amplifier 4 connected through an analog switch 2 having an ON state between input/ output terminals is connected to the input terminal of a first CMOS inverted amplifier 1, and the first CMOS inverted amplifier 1 is turned to an optimum bias state. Thus, the gain is not lowered by the negative feedback, and the deterioration of characteristics in the high frequency area can be suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS amplifier circuit, and more particularly to a CMOS amplifier circuit that amplifies an analog signal using a CMOS inverting amplifier.

0002

2. Description of the Related Art FIG. 2 shows a CMOS amplifier circuit using a conventional CMOS inverting amplifier. 1 is P-type MOSFET
This is a CMOS inverting amplifier composed of a transistor Q1 and an N-type MOSFET transistor Q2. This CMOS inverting amplifier 1 operates as an analog amplifier that inverts and amplifies the input analog signal and outputs it when the bias voltage V at point A on the input terminal side reaches a certain value close to 1/2 of the power supply voltage Vcc. do. Hereinafter, the voltage V at this time will be referred to as the optimum bias voltage.

If the voltage at point A deviates from the optimum bias voltage, distortion will occur in the amplified signal. Therefore,
Conventionally, points B and A on the output terminal side are connected via an analog switch 2 in order to maintain the voltage at point A at the optimum bias voltage. Analog switch 2 is N type CMO
It is composed of an SFET transistor Q5 and a P-type CMOSFET transistor Q6. Since the power supply voltage Vcc is applied to the gate terminal of the transistor Q5 and the gate terminal of the transistor Q6 is grounded, both the transistors Q5 and Q6 are in an on state. If the on-resistance of the analog switch 2 is low, the amplification gain will decrease due to negative feedback of the signal from point B to point A. Therefore, the on-resistance of the analog switch 2 used in such a CMOS amplifier circuit is usually Several hundred [kΩ]
It has a fairly high resistance value. Also, since point A is connected to another circuit via capacitor 3, no direct current flows through analog switch 2, and points A and B
The voltages of are equal in direct current. Therefore, when there is no signal, the voltages at points A and B are equal, and the voltage at this time is the optimal bias voltage.

When the voltage at point A becomes higher than the optimum bias voltage, the resistance value between the source and drain of transistor Q1 of CMOS inverting amplifier 1 increases, and the resistance value between the source and drain of transistor Q2 increases. Therefore, the voltage at point B is lower than the optimal bias voltage. At this time, the voltage at point B is fed back to point A via analog switch 2, lowering the voltage at point A. As a result, the voltage at point A returns to the optimum bias voltage. on the other hand,
When the voltage at point A becomes lower than the optimum bias voltage, the resistance value between the source and drain of transistor Q1 of CMOS inverting amplifier 1 decreases, and the resistance value between the source and drain of transistor Q2 of CMOS inverting amplifier 1 decreases.
Since the resistance value between the source and drain of
voltage will be higher than the optimal bias voltage. At this time,
The voltage at point B is fed back to point A via analog switch 2, increasing the voltage at point A. As a result, the voltage at point A returns to the optimum bias voltage.

Since the analog switch 2 is used to equalize the voltages at points A and B in terms of direct current, it is also possible to replace it with a resistor. However, since forming a resistive element on a semiconductor chip causes problems such as deterioration of area efficiency, analog switches are usually used.

[0006]

[Problem to be Solved by the Invention] However, in the conventional technology in which points A and B are connected via the analog switch 2, negative feedback is applied from point B to point A as described above. Therefore, there is a problem that the amplification gain decreases.

In addition, in order to prevent the amplification gain from decreasing, the on-resistance of the analog switch 2 is increased by increasing the gate length of the transistors Q5 and Q6, and the on-resistance of the analog switch 2 is increased.
It is necessary to reduce the negative feedback to the analog switch 2, but this causes a problem in that the amplification gain decreases due to the effect of stray capacitance caused by the circuit of the analog switch 2 in the high frequency range of several tens to hundreds of MHz.

The present invention is intended to solve the problems of the prior art as described above, and eliminates negative feedback from the output side to the input side of a CMOS inverting amplifier, thereby achieving sufficient amplification gain even in the high frequency region. The object of the present invention is to provide a CMOS amplifier circuit that can obtain the following characteristics.

[0009]

[Means for Solving the Problems] The features of the present invention for achieving this object include a first CMOS inverting amplifier that inverts and amplifies an input signal and outputs the inverted signal, and an input terminal of the first CMOS inverting amplifier. a second CMOS inverting amplifier whose output terminal or input terminal is connected to via a resistor;
A CMOS amplifier circuit comprising an analog switch having a first terminal connected to an input terminal of a MOS inverting amplifier and a second terminal connected to an output terminal of a second CMOS inverting amplifier, the analog switch being in an on state. maintained in the first
The ratio of the gate width of the P-type MOSFET of the CMOS inverting amplifier to the gate width of the P-type MOSFET of the second CMOS inverting amplifier, and the ratio of the gate width of the P-type MOSFET of the first CMOS inverting amplifier
ET gate length and P-type MO of the second CMOS inverting amplifier
The ratio of the gate length of the SFET to the gate width of the N-type MOSFET of the first CMOS inverting amplifier to the gate width of the N-type MOSFET of the second CMOS inverting amplifier; The four ratios of the gate length of the MOSFET and the gate length of the N-type MOSFET of the second CMOS inverting amplifier are the same.

0010

[Operation] P-type MOSFET of the first CMOS inverting amplifier
gate width and P-type MOSF of the second CMOS inverting amplifier
ET, the ratio of the gate length of the P-type MOSFET of the first CMOS inverting amplifier to the gate length of the P-type MOSFET of the second CMOS inverting amplifier, and the ratio of the gate length of the P-type MOSFET of the first CMOS inverting amplifier;
The ratio of the gate width of the N-type MOSFET of the OS inverting amplifier to the gate width of the N-type MOSFET of the second CMOS inverting amplifier, and the gate length of the N-type MOSFET of the first CMOS inverting amplifier and the gate width of the N-type MOSFET of the second CMOS inverting amplifier. N-type MOSFE
Since the four ratios of T and the gate length are the same, and the input and output terminals of the second CMOS inverting amplifier are connected via the analog switch in the on state, the second CMOS
The voltage at the output terminal of the S-inverting amplifier is equal to the optimum bias voltage of the first CMOS inverting amplifier. Therefore, by supplying this voltage as the input bias of the first CMOS inverting amplifier, the DC voltage at the input terminal of the first CMOS inverting amplifier can be increased without providing a feedback path between the input and output terminals of the first CMOS inverting amplifier. can be set to the optimum bias voltage.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a CMOS amplifier circuit according to the present invention. The signal input to this CMOS amplifier circuit via the capacitor 3 is transmitted to the first CMOS amplifier circuit.
The signal is inverted and amplified by the S inverting amplifier 1 and output. The circuit consisting of the analog switch 2 and the second CMOS inverting amplifier 4 is connected to the input terminal of the first CMOS inverting amplifier 1 (
This is to make the DC voltage at point A') the optimum bias voltage. The second CMOS inverting amplifier 4 has an output terminal (
Point P) is connected to point A' via a resistor 6, and input and output terminals are connected via an analog switch 2. Here, regarding the N-type MOSFET transistor Q5' and the P-type MOSFET transistor Q6' that constitute the analog switch 2, the gate terminal of the transistor Q5' is connected to the power supply, and the gate terminal of the transistor Q6' is grounded. Therefore, the analog switch 2 is in the on state.

Regarding the first CMOS inverting amplifier 1, the gate width of the transistor Q1 is W1, and the gate length is L1.
, the gate width of transistor Q2 is W2 and the gate length is L2, and for the second CMOS inverting amplifier 4, the gate width of transistor Q3 is W3 and the gate length is L3.
, the gate width of transistor Q4 is W4, and the gate length is L4. Between these values, W3 = W1 /K L3 = L1 /K W4 = W2 /K L4 = L2 /K (however, K is 1 The above real numbers) holds true. In other words, P-type and N-type MOSF
For each of the ETs, a second CMOS inverting amplifier 4
is such that the gate width and gate length of the first CMOS inverting amplifier 1 are 1/K. Therefore, when the input and output terminals of the second CMOS inverting amplifier 4 are connected via the on-state analog switch 2, the voltages at the input terminal and output terminal (point P) of the second CMOS inverting amplifier 4 are as follows.
It is equal to the optimum bias voltage of the first CMOS inverting amplifier 1. As a result, the DC voltage at the input terminal of the first CMOS inverting amplifier 1 can be maintained at this optimum bias voltage without providing a feedback loop using an analog switch in the first CMOS inverting amplifier 1.

Here, for each of the P-type and N-type MOSFETs, each dimension of the second CMOS inverting amplifier 4 gates is 1/K of that of the first CMOS inverting amplifier 1 because the second This is to make the power consumed by the CMOS inverting amplifier 4 lower than the power consumed by the first CMOS inverting amplifier 1, thereby making the second CMOS inverting amplifier the same as the first CMOS inverting amplifier. This makes it possible to reduce power consumption. Additionally, the chip area is also reduced.

As described above, in order to ensure the stability of the bias voltage, a capacitor 5 may be provided between the output terminal (point P) of the second CMOS inverting amplifier 4 and the ground point. Further, depending on the circuit design, it is also possible to configure the input terminal of the second CMOS inverting amplifier to be connected to the point A' via the resistor 6.

[0015]

[Effects of the Invention] As explained above, in the present invention, a feedback path is provided between the input and output terminals of the first CMOS inverting amplifier by a circuit consisting of the second CMOS inverting amplifier and the analog switch. Therefore, the DC voltage at the input terminal of the first CMOS inverting amplifier can be set to the optimum bias voltage. As a result, a conventional CMO with a return path
There is no decrease in gain due to negative feedback, which was a problem with S amplifier circuits. Furthermore, since there is no effect of stray capacitance in the feedback path in the high frequency range, deterioration of characteristics in the high frequency range can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a CMOS amplifier circuit of the present invention.

FIG. 2 represents a CMOS amplification circuit using a conventional CMOS inverting amplifier.

[Explanation of symbols]

1 First CMOS inverting amplifier 2 Analog switch 3 Capacitor 4 First CMOS inverting amplifier 5 Capacitor 6 Resistance

Claims (1)

[Claims] 1. A first CMOS inverting amplifier that inverts and amplifies an input signal and outputs the inverted signal, and a second CMOS inverting amplifier whose output terminal or input terminal is connected to the input terminal of the first CMOS inverting amplifier via a resistor. CMOS inverting amplifier and second CMO
The first terminal is connected to the input terminal of the S-inverting amplifier, and the second terminal is connected to the input terminal of the S-inverting amplifier.
and an analog switch whose second terminal is connected to the output terminal of the first CMOS inverting amplifier, the analog switch being maintained in the on state, and the gate of the P-type MOSFET of the first CMOS inverting amplifier. The ratio of the gate width of the P-type MOSFET of the second CMOS inverting amplifier to the gate width of the P-type MOSFET of the first CMOS inverting amplifier;
FET gate length and P-type M of the second CMOS inverting amplifier
the ratio of the gate length of the OSFET, the ratio of the gate width of the N-type MOSFET of the first CMOS inverting amplifier to the gate width of the N-type MOSFET of the second CMOS inverting amplifier, and the ratio of the gate width of the N-type MOSFET of the first CMOS inverting amplifier;
C, characterized in that four ratios of the gate length of the N-type MOSFET of the CMOS inverting amplifier and the gate length of the N-type MOSFET of the second CMOS inverting amplifier are the same.
MOS amplifier circuit.