JPH08186184A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent a crystal silicon film and a metal film constituting a control gate electrode from being peeled off by forming an insulation film around a stacked gate electrode and on the element activated region of a semiconductor substrate by mans of the vapor deposition method. CONSTITUTION: A stacked gate electrode 30 is formed by a control gate electrode 29 consisting of tungsten silicide film 26 which is formed on P-type silicon substrate 21 and is subjected to patterning and polycrystalline silicon film 25, an interlayer insulation film 24, a floating gate electrode 23, and a tunnel oxide film 22. Then, with the floating gate electrode 23 and the control gate electrode 29 as masks, P ions are introduced into an element activated region through the silicon oxide film 27. Then, by heat-treating the impurity layer where P ions are introduced, N-layers which are source activated region 28a and drain activated region 28b are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In a conventional method for manufacturing a nonvolatile semiconductor memory device, a stacked gate electrode composed of a tunnel insulating film, a floating gate electrode, an interlayer insulating film, and a control gate electrode is patterned from the bottom on a semiconductor substrate. After that, an oxide film is formed around the stacked gate electrode and on the element active region of the semiconductor substrate which does not overlap the stacked gate electrode by a thermal oxidation method to insulate the control gate electrode. As a result, when the source / drain diffusion is performed by the ion implantation, the charge-up that causes the deterioration of the interlayer insulating film is suppressed, and the deterioration of the reliability of the nonvolatile semiconductor memory device is prevented.

[0003]

However, in the conventional method for manufacturing a non-volatile semiconductor memory device, in order to further reduce the deterioration of the interlayer insulating film sandwiched between the floating gate electrode and the control gate electrode, a thicker insulating film is used. When forming an oxide film, thermal oxidation must be performed for a long time. For this reason,
There is a problem that the crystalline silicon film forming the control gate electrode is separated from the metal film.

The present invention has been made based on the above circumstances, prevents the crystalline silicon film forming the control gate electrode from being separated from the metal film, and causes deterioration of the interlayer insulating film during ion implantation. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of suppressing the charge-up that causes

[0005]

In order to solve the above problems, a method of manufacturing a semiconductor device according to a first aspect of the present invention is a method of manufacturing a semiconductor device including a floating gate type MOS transistor, wherein the first conductivity type is used. Forming a laminated gate electrode by patterning a first insulating film, a first crystalline silicon film, a second insulating film, a second crystalline silicon film and a metal film sequentially formed on a semiconductor substrate of the And a step of forming a third insulating film around the stacked gate electrode and on the element active region of the semiconductor substrate by a vapor deposition method,
Forming a source diffusion region and a drain diffusion region by introducing an impurity of the second conductivity type into the semiconductor substrate through the third insulating film by an ion implantation method. .

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein the metal film contains tungsten.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first or second aspect, wherein the third insulating film is a silicon oxide film.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first, second or third aspect, wherein the second insulating film is a dielectric multilayer film. .

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first, second, third or fourth aspect, wherein the first conductivity type is p type and the second conductivity type is n type. It is characterized by being.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first, second, third, fourth or fifth aspect, wherein the semiconductor device is a non-volatile semiconductor memory device. Is.

[0011]

According to the method of manufacturing a semiconductor device of the invention described above, the third insulating film is formed by the vapor deposition method instead of the thermal oxidation method, so that the second crystalline silicon film and the metal film forming the control gate electrode are formed. Can be prevented from peeling.
In addition, by introducing the second conductivity type impurity into the semiconductor substrate through the third insulating film using the laminated gate electrode as a mask, charge-up that causes deterioration of the interlayer insulating film made of the second insulating film is performed. Can be suppressed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic sectional view showing a situation in each step of a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view of a nonvolatile semiconductor memory device manufactured by the method according to the present embodiment. Is.

As shown in FIG. 2, the nonvolatile semiconductor memory device manufactured by the method of this embodiment has a p-type silicon substrate 21, a stacked gate electrode 30 formed on the p-type silicon substrate 21, and a p-type silicon substrate. A silicon oxide film 27 having a film thickness of about 500 Å formed on the element active region of the silicon substrate 21 by the CVD method, and a channel region of the element active region of the p-type silicon substrate 21 located below the stacked gate electrode 30. And an n-type source active region 28a and a drain active region 28b which are formed apart from each other. The laminated gate electrode 30 includes a tunnel gate oxide film 22 formed of a silicon oxide film having a film thickness of about 150 Å on a p-type silicon substrate 21, and a polycrystalline film having a film thickness of about 4000 Å on the tunnel gate oxide film 22. Floating gate electrode 23 formed of silicon film
And an interlayer insulating film 24 having a thickness of about 200 angstroms, which is formed of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film, on the floating gate electrode 23, and a film having a thickness of about 2000 angstroms on the interlayer insulating film 24. It has a control gate electrode 29 formed of two layers of a thick polycrystalline silicon film 25 and a tungsten silicide film 26 having a thickness of about 2000 angstrom.

The nonvolatile semiconductor memory device manufactured by the method of this embodiment holds the memory state depending on whether or not electric charges are accumulated in the floating gate electrode 23. Floating gate electrode 2
In order to accumulate the charges in 3, the charges in the channel region of the p-type silicon substrate 21 are injected into the floating gate electrode 23 through the tunnel gate oxide film 22 by applying a voltage to the control gate electrode 29. The interlayer insulating film 24 prevents the accumulated charges from being discharged to the outside when the floating gate electrode 23 stores the charges, and the floating gate electrodes 23 stores the charges when the charges are not stored in the floating gate electrode 23. It must be capable of suppressing leakage of charges so as not to be injected into the electrode 23. Therefore, the interlayer insulating film 24
Must be sufficiently reliable, and deterioration of the interlayer insulating film 24 leads to deterioration in reliability of the nonvolatile semiconductor memory device.

Next, the method of this embodiment will be described. First, as shown in FIG. 1A, the specific resistance is 10 Ω / cm ²
By thermally oxidizing the p-type silicon substrate 21 to a degree,
A silicon oxide film 12 having a film thickness of about 150 Å is formed on the surface of the element active region of the p-type silicon substrate 21. Then, a 4 film is formed on the silicon oxide film 12 by the CVD method.
A polycrystalline silicon film 13 having a film thickness of about 000 angstrom is deposited. Next, the surface of the polycrystalline silicon film 13 is heated to 100 by thermally oxidizing the polycrystalline silicon film 13.
After forming a silicon oxide film having a film thickness of approximately angstrom, a silicon nitride film having a film thickness of approximately 90 angstrom is formed on the silicon oxide film by the CVD method.
After that, by thermally oxidizing this silicon nitride film,
A silicon oxide film having a film thickness of about 40 Å is formed on the surface of the silicon nitride film. As a result, the dielectric multilayer film 14 including three layers of the silicon oxide film, the silicon nitride film and the silicon oxide film is formed.

Next, after depositing a polycrystalline silicon film 25 having a film thickness of about 2000 angstroms on the dielectric multilayer film 14 by the CVD method, a film having a film thickness of about 2000 angstroms is deposited on the polycrystalline silicon film 25 by a sputtering method. A tungsten silicide film 26 is deposited. Then, the tungsten silicide film 26, the polycrystalline silicon film 25, the dielectric multilayer film 14, the polycrystalline silicon film 13 and the silicon oxide film 12 are patterned into a linear shape having a width of 0.8 mm or less by lithography. As a result, as shown in FIG. 1B, the control gate electrode 29 including the tungsten silicide film 26 and the polycrystalline silicon film 25, the interlayer insulating film 24 including the dielectric multilayer film 14, and the polycrystalline silicon film 13 are removed. Floating gate electrode 23 and silicon oxide film 1
A stacked gate electrode 30 including the tunnel gate oxide film 22 of 2 is manufactured.

Next, as shown in FIG. 1C, a film of about 500 angstroms is formed by a CVD method on the periphery of the laminated gate electrode 30 and on the element active region which does not overlap the laminated gate electrode 30 of the p-type silicon substrate 21. After depositing a thick silicon oxide film 27, the floating gate electrode 23 and the control gate electrode 29 are used as a mask, and a dose amount of 4.0 × 10 ²⁰ / is applied to the element active region through the silicon oxide film 27 by an ion implantation method. ²⁰ ke of P ions of about cm ²
It is introduced with energy of about V. Then, by heat-treating the impurity layer into which the P ions have been introduced, N ⁺ which is the source active region 28a and the drain active region 28b.
Form the layers. Through the above steps, a main part of the nonvolatile semiconductor memory device is formed.

According to the present embodiment described above, the silicon oxide film 27 is formed by the CVD method instead of the thermal oxidation method on the periphery of the stacked gate electrode 30 and on the element active region of the p-type silicon substrate 21 which does not overlap with the stacked gate electrode 30. Therefore, it is possible to prevent the polycrystalline silicon film 25 and the tungsten silicide film 26 forming the control gate electrode 29 from peeling off. The silicon oxide film 2 is formed by using the floating gate electrode 23 and the control gate electrode 29 as a mask.
Since the P ions are introduced into the p-type silicon substrate 21 via the electrode 7, it is possible to suppress charge-up that causes deterioration of the interlayer insulating film 24 made of the dielectric multilayer film 14, and thereby to achieve high reliability. A non-volatile semiconductor memory device can be manufactured.

The present invention is not limited to the above embodiment, but various modifications can be made within the scope of the invention.
For example, although the control gate electrode 29 formed of the polycrystalline silicon film 25 and the tungsten silicide film 26 is formed in the above embodiment, the present invention is not limited to this, and the control gate electrode is a crystal. What is formed is a silicon film and a metal film.

Although the floating gate electrode 23 formed of the polycrystalline silicon film 13 is formed in the above embodiment, the present invention is not limited to this, and the floating gate electrode is a crystalline silicon film. It may be formed of.

Furthermore, although the silicon oxide film 27 is formed as the third insulating film in the above embodiment, the present invention is not limited to this. The third insulating film may be any film that can be formed by the CVD method.

Further, in the above-mentioned embodiment, the dielectric multi-layer film 14 formed of three layers of the silicon oxide film, the silicon nitride film and the silicon oxide film is formed as the interlayer insulating film, but the present invention is not limited to this. It is not limited. The interlayer insulating film may be any film as long as it can insulate the floating gate electrode and the control gate electrode.

Further, in the above embodiment, the semiconductor substrate is provided with p
Although a type silicon substrate is used, the present invention is not limited to this, and an n type silicon substrate, for example, may be used as the semiconductor substrate. Furthermore, although the above embodiments have been described as a method of manufacturing a nonvolatile semiconductor memory device, the present invention can be applied to all semiconductor devices including a floating gate type MOS transistor.

[0024]

As described above, according to the present invention, by forming the third insulating film by the vapor deposition method instead of the thermal oxidation method, the second crystalline silicon film forming the control gate electrode is formed. It is possible to prevent peeling from the metal film, and by introducing impurities into the semiconductor substrate through the third insulating film using the laminated gate electrode as a mask, the interlayer insulating film made of the second insulating film is formed. It is possible to suppress charge-up that causes deterioration of the film, and thus it is possible to provide a semiconductor device manufacturing method capable of manufacturing a highly reliable semiconductor device.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a situation in each step of a method for manufacturing a nonvolatile semiconductor memory device which is an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a nonvolatile semiconductor memory device manufactured by the method of this embodiment.

[Explanation of symbols]

 12, 25, 27 Silicon oxide film 13 Polycrystalline silicon film 14 Dielectric multilayer film 21 p-type silicon substrate 22 Tunnel gate oxide film 23 Floating gate electrode 24 Interlayer insulating film 26 Tungsten silicide film 28a Source active region 28b Drain active region 29 Control Gate electrode 30 Laminated gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device including a floating gate type MOS transistor, comprising: a first insulating film, a first crystalline silicon film, and a second film, which are sequentially formed on a first conductivity type semiconductor substrate. A step of forming a laminated gate electrode by patterning the insulating film, the second crystalline silicon film and the metal film, and a third step around the laminated gate electrode and the element active region of the semiconductor substrate by a vapor deposition method. And forming a source diffusion region and a drain diffusion region by introducing an impurity of the second conductivity type into the semiconductor substrate through the third insulating film by an ion implantation method. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film contains tungsten. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is a silicon oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a dielectric multilayer film. 5. The first conductivity type is p-type and the second conductivity type is n-type.
Or the method for manufacturing a semiconductor device according to item 4. 6. The semiconductor device is a non-volatile semiconductor memory device, 1, 2, 3, 4 or 5.
The manufacturing method of the semiconductor device described in the above.