JPH08181730A - Digital automatic gain control circuit - Google Patents

Abstract

PURPOSE: To obtain a coding gain as a theoretical value even in the case of error correction without causing deterioration in a characteristic of clock and carrier recovery even in the case of a low Eb/No. CONSTITUTION: A gain control input data calculation circuit 23 calculates a deviation of a mean value of the sum of the two systems of demodulation data outputted from a digital demodulator 14 from its expected value. An initial gain control input data calculation circuit 22 subtracts a double value of a squared expected value from the sum of squared demodulation data. A switch circuit 24 selects an output of the initial gain control input data calculation circuit 22 in the carrier locking process and selects an output of the initial gain control input data calculation circuit 23 when the carrier is locked. A control voltage calculation circuit 25 calculates a control voltage based on output data of the switch circuit 24 and gives the voltage to a multiplier 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital automatic gain control circuit, and more particularly to a digital automatic gain control circuit used in a digital demodulator for receiving and demodulating a signal modulated by a phase modulation method.

[0002]

2. Description of the Related Art Conventionally, when a digital signal is transmitted, a transmitting side generates a modulated wave by applying a predetermined modulation method among various modulation methods to a carrier as a baseband digital signal as a modulation signal. The modulated wave is transmitted to the transmission system. On the receiving side, the above-mentioned modulated wave received through the transmission system is level-corrected by the digital automatic gain control (AGC) circuit in the digital demodulator, and then the carrier wave is reproduced.
And the clock reproduction is performed, and the transmitted baseband digital signal is reproduced as a demodulation signal. In addition, when the error correction represented by the convolutional coding / Viterbi decoding system is performed, the error correction decoding process is performed on the demodulated signal.

As a modulation method used in such a digital signal communication system, BPSK (Bina) is used.
ry Phase Shift Keying method and QPSK (Quadrature Phase Shii)
A phase modulation (phase shift keying) method such as an ft Keying method is known. As is well known, the modulated wave of the BPSK method is a binary digital signal that is a modulated signal.
1 "and" 0 "correspond to 0 degrees and 180 degrees of the phase of the carrier wave. Further, the modulated wave of the QPSK system is a combination of 2-bit values of a binary digital signal which is a modulation signal.
Values correspond to 0, 90, 180 and 270 degrees of the carrier phase, respectively.

Of these, the signal points of the digital signal demodulated by the digital demodulator for demodulating the QPSK modulated wave are represented by black circles in FIG.
One signal point is located in each of the four quadrants. Also, the area around the black circle indicates noise. In the digital demodulator, when the amplitude of the received modulated wave fluctuates greatly, the signal point of the received signal largely shifts from the original signal point position among the above four signal points, and the bit error rate (BER) characteristic deteriorates.

Therefore, in order to improve the bit error rate characteristic and sufficiently maintain the functions of clock recovery (correction) and carrier recovery (correction), the amplitude fluctuation of the received modulated wave is corrected and the signal amplitude level is kept constant. A digital AGC circuit for controlling the above is used. Conventionally, the level correction by the digital AGC circuit utilizes the in-phase component P and the quadrature component Q of the demodulated data in the digital demodulator so that the root mean square of the demodulated data becomes a constant level (the average power of the input signal is (To be constant). This level correction operation is represented by the following equation.

AVE {P ² + Q ² } = constant Here, AVE {X} indicates the average value of X (hereinafter the same).

The QPSK demodulation will be described below. When the transmission data is random data of [−1 or 1], the amplitude distribution of the demodulated data (P, Q) can be considered to be the normal distribution shown in FIG.

[0008]

[Equation 1] However, in the above equation, σ ₁ is the standard deviation of P, σ ₂ is the standard deviation of Q, μ ₁ is the average of P (expected value), μ ₂ is the average of Q (expected value), and these are constants. is there. Further, ρ is a correlation coefficient, and here P and Q are independent of each other, so ρ =
0. Also, −∞ <P, Q <∞, σ ₁ = σ ₂ > 0, μ
There is a relation of ₁ = μ ₂ > 0. Further, mu ₁ and mu ₂ of the previous code first in quadrant mu ₁ and mu ₂ are both negative 3, in the second quadrant mu ₁ is ₂ positive mu negative, in the third quadrant mu ₁ and mu ₂ Both are positive, and in the fourth quadrant, μ ₁ is negative and μ ₂ is positive.

The above equation may be used for explanation, but here, for ease of understanding, explanation will be given below with reference to the drawings. The demodulated data (P, Q) distribution is shown in FIG. 5 when the energy-to-noise power density ratio (Eb / No) per bit is high, that is, when the noise (noise power) is small.
A distribution as shown in (A) is shown. It should be noted that in FIG. 5, the positive and negative parts are symmetrical, so only the positive part is shown.

On the other hand, when Eb / No is low, that is,
When there is a lot of noise, the demodulated data (P, Q)
The distribution is the variance σ, as shown in FIG.² Is large
Becomes However, the variance σ²Becomes larger, AVE {P²+ Q²If we try to maintain the condition that} = constant, it will be as shown in Fig. 5 (C).
Sea urchin average μ₁And μ₂Moves in the direction of becoming smaller. One
The lower the Eb / No state, the more the demodulation coordinate distribution becomes.
You will physically approach the origin.

[0011]

However, in the conventional digital automatic gain control circuit, the control is performed so that the mean square of the amplitude level becomes a constant level. , And when the Eb / No is low, as the Eb / No becomes worse, not only the amplitude and phase components of the demodulated data become larger due to noise components, but also the demodulated data coordinate distribution is It approaches the origin (the average value approaches the origin).

In this case, although the sign is not inverted, since the average amplitude level becomes small, the error of the carrier phase and the clock phase is obtained from the addition / subtraction calculation of the amplitude value of the demodulated data (P, Q). In such a case, there is a problem that the correct error value is not shown and the characteristics of carrier reproduction and clock reproduction are deteriorated.

Further, in the case of performing error correction processing such as Viterbi decoding on the demodulated data, when performing soft decision processing, the demodulated data amplitude level input to the error correction decoder and the input range of the error correction decoder are When they match (when the input range of the error correction decoder is ± 2α and the average value of the input data is μ, α = μ as shown by the solid line in FIG.
, The coding gain becomes maximum, but as shown by the broken line in FIG. 6, when the input range of the error correction decoder and the input demodulated data amplitude level do not match, the coding gain becomes small. Therefore, the expected coding gain cannot be obtained. Therefore, when performing soft-decision error correction, low E
The bit error rate (BER) characteristic at b / No has a problem that the expected coding gain cannot be obtained.

Even in a low Eb / No state in which noise is superimposed on the received PSK modulated wave, a control voltage from which the influence of noise has been removed as much as possible is generated from demodulated data.
There is also known an AGC circuit in which the received PSK modulated wave is controlled to a constant level by being controlled by an AGC amplifier for amplifying the received PSK modulated wave, without being affected by noise (Japanese Patent Laid-Open No. 4-335174). However, there is a problem that a number of arithmetic operations are required based on the demodulated signal power.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital automatic gain control circuit which does not cause deterioration of characteristics of clock reproduction and carrier reproduction even at low Eb / No with a small number of calculations.

Another object of the present invention is to provide a digital automatic gain control circuit which can always obtain a coding gain in accordance with a theoretical value even in error correction such as Viterbi decoding.

[0017]

To achieve the above object, the present invention demodulates a modulated wave obtained by phase-modulating a carrier wave with a baseband digital signal to obtain demodulated data of the original digital signal. In the digital automatic gain control circuit used in the obtained digital demodulator, from the expected value of the average of the sum of the sizes of the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator, Gain control input data calculation means for calculating the deviation as gain control input data, and the square of the expected value from the sum of the squares of the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator. The initial gain control input data calculation circuit that performs the operation of subtracting the doubled value and outputs the obtained value as the initial gain control input data, and the carrier wave subtraction The initial gain control input data in the locking process, and the gain control input data in the state where the carrier wave is pulled in; the control voltage calculation circuit for calculating the control voltage based on the output data of the selection device; And an amplitude control means for controlling the amplitude of the input signal of the digital demodulator with a gain corresponding to the voltage.

In the present invention, the gain control input data calculating means is an absolute value calculating circuit for calculating the absolute value of each of the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator, and an absolute value calculating circuit. The gain control input data calculation circuit calculates a value obtained by subtracting the expected value from the sum of the output signals of the value calculation circuit and outputs it as gain control input data, and the amplitude control means is a digital signal obtained from the received modulated wave. It is desirable that the imaginary signal is multiplied by the control voltage from the control voltage calculation circuit and that the multiplication result is supplied to the digital demodulator, because the amplitude level can be controlled by a simple arithmetic process.

[0019]

According to the present invention, when the carrier is pulled in (carrier synchronized state), the demodulation data of the in-phase component and the demodulation data of the quadrature component output from the digital demodulator are demodulated by the gain control input data calculating means. The deviation of the average of the sum of the data sizes from the expected value is calculated as gain control input data, which is supplied to the control voltage calculation circuit via the selection means and corresponds to the control voltage calculated by the control voltage calculation circuit. Since the gain controls the amplitude of the input signal of the digital demodulator, the average value of the amplitudes of the demodulated data can be maintained at the expected value.

[0020]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. As shown in the figure, the digital AGC circuit 20 of the present embodiment is a low noise amplifier / frequency converter 1 that amplifies and frequency-converts an IF signal from an intermediate frequency signal (IF signal) input terminal 11.
2, the A / D converter 13, the digital demodulator 14, the demodulated data output terminals 15a and 15b, and the switch switching control signal generating unit 16 are provided in the receiver. This receiver can be applied to reception of each modulated wave modulated by various phase modulation methods, but here, the reception of the modulated wave modulated by the QPSK method will be mainly described as an example.

As is well known, the QPSK method is 2
Each of the two binary digital signals of the sequence has two phases that are different from each other by 90 degrees and two-phase phase-modulates to generate two modulated waves that are in an orthogonal relationship. It is a modulation method of a digital signal transmitted as a phase-modulated wave.

The digital AGC circuit 20 comprises an absolute value calculation circuit 21, an initial gain control input data calculation circuit 22, a gain control input data calculation circuit 23, a switch circuit 24, a control voltage calculation circuit 25 and a multiplier 26. .
The switch circuit 24 has switching terminals 24a and 24b,
Based on the switch switching control signal from the switch switching control signal creation unit 16, one of the input signals of the switching terminals 24a and 24b is supplied to the control voltage calculation circuit 2 via the common terminal 24c.
Supply to 5.

The control voltage calculation circuit 25 includes the switch circuit 2
A value obtained by subtracting the cumulative value of the multiplication result of the output data of 4 and the constant from 1 is calculated, and this value is output to the multiplier 26 as a control voltage corresponding to the gain G. This digital AGC
The circuit 20 corrects the level by the multiplication operation of the multiplier 26 so that the received digital signal supplied to the digital demodulator 14 has a constant amplitude. The value of the level correction by the multiplier 26 is created based on the demodulated data (soft data P and Q).

Next, the operation of this embodiment will be described.
The modulated wave of the QPSK system is received by an antenna (not shown), amplified in a high frequency section and converted into an IF signal, and then supplied to a low noise amplifier / frequency converter 12 via an input terminal 11, where low frequency It is amplified by noise and frequency-converted into a baseband signal. This baseband signal is supplied to the A / D converter 13, converted into a digital real / imaginary signal, and then multiplied by a control voltage from a control voltage calculation circuit 25, which will be described later, in a multiplier 26, and then the digital demodulator 14 Is supplied to.

The digital demodulator 14 performs demodulation data P of the in-phase component and demodulation data Q of the quadrature component by known coherent detection using a reproducing carrier wave having a phase difference of 90 degrees with respect to the input digital real / imaginary signal. Is demodulated and output to the output terminals 15a and 15b, and is also supplied to the switch switching control signal generation unit 16.

Further, in this embodiment, the demodulated data P
And Q are input to the absolute value calculation circuit 21 and the initial gain control input data calculation circuit 22, respectively. The absolute value calculation circuit 21 receives the demodulated data P and Q as input signals, respectively, and calculates absolute values | P | and | Q | of the input signals.

Here, in order to keep the amplitude levels of the output demodulated data P and Q of the digital demodulator 14 constant,

[0028]

[Equation 2] The control may be performed so that the average of the values of is zero. Therefore, the gain control input data calculation circuit 23 calculates the gain control data Δ by the following equation, and uses this data as the switch circuit 2
4 switching terminals 24b.

[0029]

(Equation 3) When the carrier wave is pulled in, that is, when the demodulated data is displayed in XY coordinates, and the signal points of the demodulated data are concentrated at four points as shown in FIG. By controlling so that the average value of is kept at zero, the average value of demodulated data is almost constant (expected value) “μ”
Therefore, the conventional problems described above can be solved.

However, when the carrier wave is in the process of pulling in, that is, when the demodulated data is displayed in XY coordinates,
As shown in FIG. 2B, when demodulation data does not exist in a discrete manner, if the gain control input data Δ calculated by the gain control input data calculation circuit 23 is to be kept constant, the digital AGC circuit 20 Level correction is not performed correctly, fluctuations in amplitude level (amplitude fluctuations) occur, and clock recovery and carrier recovery are affected, leading to poor pull-in characteristics.

Therefore, in this embodiment, similarly to the conventional method,
The initial gain control input data calculation circuit 22 performs a calculation Δ = P ² + Q ² −2μ ² (3) on the basis of the output demodulation data P and Q of the digital demodulator 14 to obtain a value Δ, It is input to the switching terminal 24a of the switch circuit 24 as gain control input data in the process (in the state of carrier asynchronous).

The switch circuit 24 is responsive to the switch switching control signal from the switch switching control signal creating section 16 to input the initial gain control input data calculation circuit 22 which is input to the switching terminal 24a during the carrier wave pulling process (in the carrier wave asynchronous state). Output initial gain control input data is supplied to the control voltage calculation circuit 25 from the common terminal 24c, and the gain control input to the switching terminal 24b when the carrier wave is pulled in (during carrier wave synchronization state). The output gain control input data Δ of the input data calculation circuit 23 is selected and supplied to the control voltage calculation circuit 25 from the common terminal 24c.

Here, the switch changeover control signal producing section 16
Is the state where the carrier wave is pulled in (when the carrier wave is in sync),
Whether the carrier wave pulling process (in the carrier wave asynchronous state) is detected by the following method, and a switch switching control signal having a logical value according to the detected state is generated. That is, in the state where the carrier wave is pulled in (during carrier wave synchronization state), the demodulated data shows the signal point arrangement as shown in FIG. 2A (in the case of QPSK). On the other hand, in the carrier wave pull-in process (in the carrier wave asynchronous state), the demodulated data has a distribution as shown in FIG.

Therefore, the switch switching control signal generating section 16
Compares the phase error average AVE {P-Q} with a set threshold value to determine the synchronous state or the asynchronous state (in the case of BPSK, AVE {Q}.
Is compared with a threshold value), and a switch switching control signal having a logical value “1” or “0” is created according to the determination result and output to the switch circuit 24. Various other algorithms for determining the synchronous state and the asynchronous state have been proposed, and any of the processes can be applied to the switch switching control signal generating unit 16.

The control voltage calculation circuit 25 receives the gain control input data Δ selected by the switch circuit 24 in this way and represented by the formula (2) or (3) as an input signal, and based on the following formula: As a result, a gain (specifically, a value by which the multiplier 26 multiplies the digital real / imaginary signal) G can be obtained as a control voltage.

[0036]

[Equation 4] However, in the above equation, β is a constant.

The calculation of the gain G is obtained by only performing the operations of the equations (2), (3) and (4) on the basis of the demodulated data (soft data) P and Q. Since only a very simple division using “2” as a divisor is required for the division, the number of operations is smaller than that of the conventional circuit described in the above-mentioned publication, and the control voltage (gain) G can be easily calculated.

This control voltage (gain) G is supplied to the multiplier 26, is multiplied by the digital real / imaginary signal, and is then supplied to the digital demodulator 14 repeatedly. ) Is executed such that Δ is maintained at zero, and when the carrier wave is pulled in, control is performed so that the average value of Δ shown in expression (2) is maintained at zero. Be seen.

As a result, in the process of pulling in the carrier wave, the average value of the demodulated data (soft data) P and Q is low Eb / N.
The value at the time of o is smaller than that at the time of high Eb / No as described above, but the gain control input data of the equation (2) obtained by the gain control input data calculation circuit 23 is used in the equation (4) to obtain the gain. Since there is no fluctuation (amplitude fluctuation) in the amplitude level of the demodulated data (soft data) P and Q as in the case of control,
The pull-in characteristic is better than that, and the pull-in characteristic does not deteriorate as compared with the conventional circuit (shows the same pull-in characteristic).

On the other hand, in the carrier pull-in state, control is performed so that the average value of Δ shown in the equation (2) is maintained at zero, and as a result, the amplitude levels of the demodulated data (soft data) P and Q are made constant. Can be kept. Therefore, even when the Eb / No is low, the characteristics of the clock reproduction and the carrier reproduction are not deteriorated due to the decrease of the average amplitude level, and the coding gain based on the soft decision is theoretically used in error correction such as Viterbi decoding. You can get it for the price.

When the digital AGC circuit 20 is composed of, for example, a digital signal processor (DSP), if the division operation is possible, more complicated operation can be performed than that described in the embodiment, so that the accuracy is higher. Gain control can be performed.

The present invention is not limited to the above embodiment, but can be applied to other phase modulation methods such as a BPSK method other than the QPSK method, a π / 4 shift QPSK method, an offset QPSK method, and the like. Where π
The / 4 shift QPSK system transmits QPSK that transmits one of the same four signal points on the signal plane as shown in FIG.
Unlike the method, at one time, one of the four signal points on the signal plane of two orthogonal channel signals is transmitted, and at the next time, the above four signal points are shifted by π / 4 on the signal plane. This is a method of transmitting one of four signal points.

In the offset QPSK method, the change points of two series of binary digital signals of the in-phase channel and the quadrature channel occur at the same time, whereas the change points of two series of data are transmission periods of data of each other. This is a modulation method that occurs at the center of.

[0044]

As described above, according to the present invention,
Unlike the conventional circuit that keeps the power level of the demodulated data constant when the carrier is pulled in (carrier synchronized state),
Since the average value of the amplitudes of the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator is controlled so as to be maintained at an almost expected value, the average amplitude level of the demodulated data remains low even at low Eb / No. It is possible to prevent the characteristics of clock reproduction and carrier reproduction from being deteriorated due to the reduction of the size.

Further, according to the present invention, when the carrier wave is pulled in (carrier wave synchronization state), the average value of the amplitude level of the demodulated data is controlled to be constant, so that an error such as Viterbi decoding occurs. When soft data is used for correction, the consistency of the center (average) level can be maintained, and thus the coding gain by soft decision can be obtained according to the theoretical value.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a signal point arrangement diagram for explaining the operation of FIG.

FIG. 3 is a signal point constellation diagram of the QPSK system.

FIG. 4 is a diagram showing an amplitude distribution of demodulated data of the QPSK method.

FIG. 5 is a diagram showing an example of distribution of demodulated data.

FIG. 6 is a diagram illustrating consistency between a soft decision input range and an input signal level.

[Explanation of symbols]

 11 IF Signal Input Terminal 12 Low Noise Amplifier / Frequency Converter 13 A / D Converter 14 Digital Demodulator 15a, 15b Demodulated Data (Soft Data) Output Terminal 16 Switch Switching Control Signal Creating Section 20 Digital AGC Circuit 21 Absolute Value Calculation Circuit 22 initial gain control input data calculation circuit 23 gain control input data calculation circuit 24 switch circuit 25 control voltage calculation circuit 26 multiplier

Claims (4)

[Claims] 1. A digital automatic gain control circuit used in a digital demodulator for demodulating a modulated wave obtained by phase-modulating a carrier wave with a baseband digital signal to obtain demodulated data of an original digital signal. Gain control input data calculation that calculates the deviation from the average expected value of the sum of the size of each demodulation data from the demodulation data of the in-phase component and the demodulation data of the quadrature component output from the digital demodulator And a value obtained by subtracting a value that is twice the square of the expected value from the sum of the squares of the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator. Initial gain control input data calculation circuit for outputting as the initial gain control input data, and the initial gain control input data in the carrier pulling process. Selecting means for selecting the gain control input data when the carrier wave is pulled in, a control voltage calculating circuit for calculating a control voltage based on the output data of the selecting means, and a gain corresponding to the control voltage. And an amplitude control means for controlling the amplitude of the input signal of the digital demodulator. 2. The gain control input data calculating means calculates an absolute value of each of the demodulation data of the in-phase component and the demodulation data of the quadrature component output from the digital demodulator, and the absolute value calculation circuit. A gain control input data calculation circuit for calculating a value obtained by subtracting the expected value from the sum of the output signals of the calculation circuit and outputting it as the gain control input data, wherein the amplitude control means is a digital signal obtained from a received modulated wave. 2. The digital automatic gain control circuit according to claim 1, further comprising a multiplier for multiplying a real / imaginary signal by a control voltage from the control voltage calculation circuit and supplying the multiplication result to the digital demodulator. 3. The control voltage calculation circuit calculates a value obtained by subtracting the cumulative value of the multiplication result of the output data of the selection means and a constant from 1, and outputs this value as a control voltage corresponding to the gain. The digital automatic gain control circuit according to claim 1 or 2, characterized in that: 4. The selecting means detects, based on the demodulated data of the in-phase component and the demodulated data of the quadrature component output from the digital demodulator, whether or not the carrier is in a pull-in state and responds to the detection result. A switch switching control signal generating section for outputting a switch switching control signal, and output data of the gain control input data calculating circuit and the initial gain control input data calculating circuit according to the switch switching control signal from the switch switching control signal generating section. 2. A digital automatic gain control circuit according to claim 1, further comprising a switch circuit for selecting one of them.