JPH06216955A - Agc circuit for burst signal - Google Patents

Abstract

PURPOSE:To have a fast response characteristic by an AGC loop at the time of requiring the fast synchronism in the initial state and to let the AGC loop band minimize and eliminate an influence of the loop noise after the fast response. CONSTITUTION:The output signal of a sub-synchronous demodulating circuit 21 which shifts the frequency of a burst modulated wave signal to that of a base band signal is converted to digital signals by A/D conversion circuits 22 and 23, and the output signals of these circuits 22 and 23 and the output signal of an integrating circuit are inputted to a multiplying circuit 24. The output signal of the circuit 24 is imparted to a subtracting circuit 28 through square circuits 25 and 26 and an adding circuit 27. The subtracting circuit 28 obtains the difference between the input signal and a reference signal. A polarity discriminating circuit 11 discriminates the positive and negative polarity of the output signal of the subtracting circuit 28. A selecting circuit 12 selects a loop constant K1 by the circuit 11 when the polarity of the output signal of the substracting circuit 28 is positive, but the circuit 12 selects a loop constant K2 (K1>>K2) when it is negative.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal AGC circuit of a burst signal demodulator / demodulator for voice activation, slotted Aloha, TDMA and the like.

[0002]

2. Description of the Related Art In the case of voice transmission in a satellite communication system, a voice activation system is a satellite power system in which a signal is transmitted only when voice is present due to the intermittent occurrence characteristic of a speaker, and signal transmission is stopped when there is no voice. It is useful and often used. Such a signal-modulated wave becomes an intermittent transmission, that is, a burst signal. Therefore, a demodulator corresponding to burst is required on the receiving side.

On the receiving side, when the opposite station is changed, the reception level fluctuates due to the fluctuation of the propagation loss (base of each station) of the communication transmission line. Generally, when the reception level fluctuates, the loop gain of the carrier recovery circuit or the clock recovery circuit of the demodulator fluctuates and stable demodulation operation cannot be performed, and the AGC operation is necessary to keep the amplitude constant.

FIG. 2 shows the configuration of a conventional AGC circuit. The quasi-synchronous demodulation circuit 21 quasi-synchronously demodulates the burst modulated wave signal (1F input signal) transmitted intermittently by a quadrature carrier signal substantially equal to its carrier frequency to convert it into two series of analog signals. The A / D conversion circuits 22 and 23 are
The output signal from the quasi-synchronous demodulation circuit 21 is converted into a multi-bit digital data string. A / D conversion circuits 22 and 23
The digital data string from is input to the multiplication circuit 24 and then to the digital processing type demodulation circuit 31 and the square circuits 25 and 26. The power of each data string is added by the adder circuit 27 to obtain the power of the received signal output from the multiplier circuit 24. The subtractor 28, which has received the output received power of the adder circuit 27, finds the difference between the reference value of the power to be set by the AGC loop. This subtractor 28
The difference obtained by is the multiplication circuit 2 which determines the gain of the loop.
After being multiplied by the fixed constant k at 9, the data is input to the integrating circuit 30. The integrating circuit 30 integrates the output of the multiplying circuit 29, drives the multiplying circuit 24, and forms an AGC loop so that the output of the subtracting circuit 28 becomes zero.

In such an AGC loop, the response speed of the loop is determined by the loop gain k. The larger k is, the faster the response speed of the loop is. The smaller k is, the slower the response speed is.

[0006]

In the conventional AGC circuit for burst signals, it is generally necessary to increase the response speed of the loop in order to cope with the burst signal. However, increasing the loop response increases the loop bandwidth. Since it is equivalent to doing so, the amplitude fluctuation component of the signal passing through the loop and the noise component superimposed on the received signal also pass through the loop and are added to the received signal by the multiplier, which causes deterioration of signal quality. . For this reason, there is a limit to how fast burst signals can be handled.

The object of the present invention is to provide an AGC for burst signals in which the AGC loop has a high-speed response characteristic when high-speed synchronization is required in the initial state, and the AGC loop band is minimized after the high-speed response and the influence of loop noise is eliminated. To provide a circuit.

[0008]

According to the present invention, a quasi-synchronous demodulation circuit, which receives a burst modulation wave signal transmitted intermittently and shifts the frequency of the burst modulation wave signal to a baseband signal, A semi-synchronous demodulation circuit A / D conversion circuit for converting an output signal into a digital signal, and a multiplying operation using the modulated wave signal converted into a digital signal by the A / D conversion circuit and the output signal of the integration circuit as inputs 1 multiplication circuit, a square circuit that squares the output signal of the first multiplication circuit, and a digital subtraction circuit that obtains the difference between the output signal of the square circuit and a predetermined reference signal, A digital polarity determination circuit for determining whether the polarity of the output signal of the subtraction circuit is positive or negative, and a loop constant K1 is selected by the polarity determination circuit when the polarity of the output signal of the subtraction circuit is positive, and the subtraction circuit is selected. of A selection circuit that selects a loop constant K2 (K1 >> K2) when the polarity of the force signal is negative; and a second multiplication circuit that multiplies the output signal of the selection circuit and the output signal of the subtraction circuit. A burst signal for supplying the output signal of the first multiplication circuit to the demodulation circuit, and the integration circuit for integrating the output signal of the second multiplication circuit to drive the first multiplier. An AGC circuit is obtained.

Further, according to the present invention, in the burst signal AGC circuit, there is obtained a burst signal AGC circuit characterized in that the integration circuit resets an integrated value once at the start of a call.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the embodiment of FIG. 1, the same components as those of the embodiment of FIG. 3 are designated by the same reference numerals. In the embodiment of FIG. 1, a polarity determination circuit 11 and a selection circuit 12 are newly added to the embodiment of FIG.

The polarity determination circuit 11 receives the output signal of the subtraction circuit 28 which detects the difference between the reference value and the received power, and determines the polarity of the polarity. The determined polarity signal is given to the selection circuit 12. The selection circuit 12 selects the loop constant K1 when the polarity of the polarity signal is positive, and selects the loop constant K2 when the polarity of the polarity signal is negative. Here, K2 << K1. The selected loop constants K1 and K2 are input to the multiplication circuit 29 that determines the gain of the AGC loop.

Next, embodiments of the present invention will be specifically described in detail.

First, when the present embodiment receives a signal for the first time, the received power is small because the noise component existing in the transmission path at most is received before the signal arrives. Therefore, the value appearing in the addition circuit 27 is smaller than the reference value, and the output of the subtraction circuit 28 becomes a negative value. Therefore, the polarity determination circuit 11 outputs a negative signal, and K2 appears in the output of the selection circuit 12. The output of the subtraction circuit 28 becomes K2, and K2 << K1 is satisfied, and AGC is set as a constant for keeping the loop band small.
The loop is waiting while keeping the low-speed response characteristic. However, since the signal is not received, the multiplication circuit 24 usually has a value having the maximum gain. or,
In voice communication or the like, when a call is first started, a call channel is designated by a signaling signal and then actual communication is started. In this case, the integrating circuit 30 of FIG.
It is possible to set the value of the integrating circuit 30 to a value that maximizes the gain of the multiplying circuit 24 using a reset signal connected to.

This state is shown in FIG. FIG. 2A shows the case where the demodulator first communicates with the A station and then with the B station, and the reset signal is input before the call starts. The reset signal is input before the start even when the communication with the station A is completed and the next communication with the station B is performed. FIG. 2B shows the situation of the signal of the station A, and shows the situation where the burst signal is transmitted based on the generation of the voice of the caller.

When a signal is received, a large voltage is generated in the adder circuit 27 indicating the received power, the output of the subtractor circuit 28 becomes a positive value, and the constant set in the multiplier circuit 29 is the polarity judgment circuit 11 and the selection circuit 12. Sets the value of K1. This K1 is K1 >> K2, and is set to a value that widens the band of the loop. Therefore, the bandwidth of the AGC loop is wide,
Responds to input signals at high speed. When the loop responds at high speed, the signal power input to the demodulation circuit 31 by the multiplication circuit 24 rapidly matches the reference value, and the output signal of the subtractor 28 becomes zero. When the output signal of the subtractor 28 becomes 0, the output of the polarity determination circuit 11 becomes negative and the selection circuit 1
2 is controlled to select the loop constant K2. At this time, K2 has a sufficiently small value as compared with K1, so that the noise in the AGC loop also has a sufficiently small value and the signal deterioration is suppressed to the minimum. Therefore, when high-speed synchronization is required, the band of the AGC loop becomes large, and once pulled in, the AGC loop becomes a small band and signal deterioration is minimized.

Next, consider the case where this reception burst disappears.

When there is no received signal, the output of the subtraction circuit 28 is maintained at a negative value, so that K2 remains set in the multiplier 29. Since K2 is a sufficiently small value, only a very small value is supplied to the integrator 30 following the multiplier 29, so that the value of the integrator 30 is kept substantially constant for a long time. Therefore, the gain of the multiplier 24 is maintained at about the same value as when there is a burst signal.

Therefore, when the next signal is received, the gain of the multiplication circuit 24 is maintained in an almost ideal state, so that the time required for the next pull-in becomes extremely short. If the input signal is smaller than the previous burst, it takes a long time to respond, but in systems such as voice activation, the transmitting station is the same station, so the level difference is small and there is no effect on subsequent demodulators. is there. Looking at other systems such as TDMA, the level difference between bursts is about 3 dB at most, and there is almost no influence on the demodulator.

[0020]

According to the present invention, when high-speed synchronization is required in the initial state, the AGC loop has a high-speed response characteristic, and after the high-speed response, the AGC loop band is minimized and the influence of loop noise is eliminated. Further, in the present invention,
After the burst signal is received, when the burst signal disappears, the AGC loop is set to the minimum band, and the gain of the gain control multiplication circuit is set corresponding to the level of the previous burst. Even from time to time, a value close to the target level can be supplied to the demodulator from the beginning.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining the timing of resetting the integrating circuit 30 in the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional burst signal AGC circuit.

[Explanation of symbols]

 11 polarity determination circuit 12 selection circuit 21 quasi-synchronous demodulation circuit 22, 23 A / D conversion circuit 24 multiplication circuit 25, 26 square circuit 27 addition circuit 28 subtraction circuit 29 multiplication circuit 30 integration circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Colin Smith 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation

Claims (2)

[Claims] 1. A quasi-synchronous demodulation circuit for inputting a burst modulated wave signal transmitted intermittently, and shifting the frequency of the burst modulated wave signal to a baseband signal, and a quasi-synchronous demodulator output signal to a digital signal. An A / D conversion circuit for conversion, a first multiplication circuit for performing a multiplication operation using the modulated wave signal converted into a digital signal by the A / D conversion circuit and the output signal of the integration circuit as input, and the first multiplication circuit. A square circuit that squares the output signal of the multiplication circuit, a digital subtraction circuit that obtains the difference between the output signal of the square circuit and a predetermined reference signal, and the polarity of the output signal of the subtraction circuit A polarity determining circuit of digital type for determining that the loop constant K1 is selected when the polarity of the output signal of the subtracting circuit is positive by the polarity determining circuit, and the polarity of the output signal of the subtracting circuit is negative In A selection circuit that selects a loop constant K2 (K1 >> K2), a second multiplication circuit that multiplies the output signal of the selection circuit and the output signal of the subtraction circuit, and the second multiplication circuit.
Burst signal A for integrating the output signal of the multiplier circuit and driving the first multiplier, and supplying the output signal of the first multiplier circuit to the demodulation circuit.
GC circuit. 2. The burst signal AGC circuit according to claim 1, wherein the integration circuit resets an integrated value once at the start of a call.