JPH08181251A - Ceramic multilayer substrate - Google Patents
Ceramic multilayer substrateInfo
- Publication number
- JPH08181251A JPH08181251A JP6324496A JP32449694A JPH08181251A JP H08181251 A JPH08181251 A JP H08181251A JP 6324496 A JP6324496 A JP 6324496A JP 32449694 A JP32449694 A JP 32449694A JP H08181251 A JPH08181251 A JP H08181251A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- ceramic multilayer
- multilayer substrate
- semiconductor chip
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板表面に半導体チッ
プをフリップチップ方式で実装するようにしたセラミッ
ク多層基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer substrate in which a semiconductor chip is mounted on the surface of the substrate by a flip chip method.
【０００２】[0002]
【従来の技術】近年の高密度実装・小型化の要求に応え
るため、セラミック多層基板に半導体チップをフリップ
チップ方式で実装したＩＣ製品の需要が益々増大してい
る。一般に、フリップチップは、ワイヤボンディング用
として製造された半導体チップをそのままフリップチッ
プ用のチップとして流用することが多い。従って、チッ
プ側の電極部（バンプ）は、チップの外周に一列に並ん
で形成されている。一方、セラミック多層基板も、小型
化のために多層化する傾向にあり、多層基板ではチップ
直下の基板内層に何層もの導体や誘電体を形成してい
る。このため、内層の導体や誘電体とセラミック基材と
の間で焼成収縮に微妙なミスマッチがあり、これが原因
で焼成後の基板に反りが生じることが多い。2. Description of the Related Art In order to meet recent demands for high-density mounting and miniaturization, demand for IC products in which semiconductor chips are mounted on a ceramic multilayer substrate by a flip-chip method is increasing more and more. In general, as the flip chip, a semiconductor chip manufactured for wire bonding is often used as it is as a chip for flip chip. Therefore, the electrode parts (bumps) on the chip side are formed in a line on the outer periphery of the chip. On the other hand, ceramic multi-layer substrates also tend to be multi-layered for miniaturization, and in multi-layer substrates, many layers of conductors and dielectrics are formed in the inner layers of the substrate immediately below the chip. For this reason, there is a slight mismatch in firing shrinkage between the conductor or dielectric material of the inner layer and the ceramic base material, which often causes warpage in the substrate after firing.
【０００３】[0003]
【発明が解決しようとする課題】上述したように焼成収
縮のミスマッチにより生じるセラミック多層基板の反り
が凸反りである場合には、図６に示すように、半導体チ
ップ１１がセラミック多層基板１７から浮き上がってし
まい、セラミック多層基板１７の表面のパッド１３と、
半導体チップ１１の電極部１４に形成されたバンプ１５
との接続が不完全となる。これを防ぐために、セラミッ
ク多層基板１７の反りを１５μｍ以下（１チップ当た
り）に抑えることが要求されることが多い。When the warp of the ceramic multilayer substrate caused by the mismatch of firing shrinkage is convex as described above, the semiconductor chip 11 is lifted from the ceramic multilayer substrate 17 as shown in FIG. The pad 13 on the surface of the ceramic multilayer substrate 17,
The bump 15 formed on the electrode portion 14 of the semiconductor chip 11
The connection with is incomplete. In order to prevent this, it is often required to suppress the warp of the ceramic multilayer substrate 17 to 15 μm or less (per chip).
【０００４】このような基板側の反りの対策として、基
板焼成後に基板表面を研磨して平坦化し、その後に、基
板表面にフリップチップ接続用のパッドを薄膜形成又は
印刷焼成することが考えられる。しかしながら、この方
法では、基板表面の研磨やパッドの薄膜形成又は印刷焼
成という手間のかかる工程を追加しなければならないた
め、製造コストが大幅に高くなる欠点がある。しかも、
基板焼成後は、焼成前のグリーンシートに比して２割程
度も焼成収縮すると共に、基板表面における印刷塗料の
にじみが大きく、ファインパターン化にも限界がある。As a countermeasure against such a warp on the substrate side, it is conceivable that the substrate surface is polished and flattened after the substrate is fired, and then a pad for flip chip connection is formed into a thin film or printed and fired on the substrate surface. However, this method has a drawback that the manufacturing cost is significantly increased because a laborious process of polishing the substrate surface, forming a thin film of the pad, or printing and baking must be added. Moreover,
After firing the substrate, the firing shrinkage is about 20% of that of the green sheet before firing, and the bleeding of the printing paint on the substrate surface is large, and there is a limit to fine patterning.
【０００５】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、基板表面を研磨しな
くても、基板の凸反りによる半導体チップの浮き上がり
を防止することができて、半導体チップの接続信頼性を
向上できると共に、ファインパターン化・低コスト化の
要求も満たすことができるセラミック多層基板を提供す
ることにある。The present invention has been made in consideration of such circumstances, and therefore an object thereof is to prevent the semiconductor chip from being lifted up due to the warp of the substrate without polishing the surface of the substrate. It is an object of the present invention to provide a ceramic multilayer substrate which can improve the connection reliability of a semiconductor chip and can also meet the requirements for fine patterning and cost reduction.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項１のセラミック多層基板は、基板表
面に半導体チップをフリップチップ方式で実装する多数
のパッドが列設され、前記基板表面のうちの前記パッド
の列の内側領域に、前記半導体チップの下面に対向する
凹部を形成した構成としたものである。In order to achieve the above object, a ceramic multilayer substrate according to claim 1 of the present invention has a large number of pads for mounting a semiconductor chip mounted in a flip chip manner on the surface of the substrate. A concave portion facing the lower surface of the semiconductor chip is formed in an area inside the row of pads on the surface of the substrate.
【０００７】この場合、請求項２のセラミック多層基板
のように、グリーンシートを積層・焼成するに際して、
前記パッドの列の内側領域に穴部が形成されたグリーン
シートを最上層に積層して焼成することで、基板表面に
前記凹部を形成するようにしても良い。更に、請求項３
のように、低温焼成用のグリーンシートを積層し、１０
００℃以下で焼成することが好ましい。In this case, when the green sheets are laminated and fired as in the ceramic multilayer substrate according to claim 2,
The recess may be formed on the surface of the substrate by stacking a green sheet having holes formed in the inner region of the row of pads on the uppermost layer and baking the green sheet. Further, claim 3
And stack the green sheets for low temperature firing,
It is preferable to perform firing at 00 ° C or lower.
【０００８】[0008]
【作用】本発明によれば、基板表面のうちのパッドの列
の内側領域に形成された凹部が半導体チップ（フリップ
チップ）の下面に対向し、凹部底面と半導体チップとの
間にある程度の隙間が開いた状態となる。このため、た
とえ、セラミック多層基板が凸反りして、凹部底面が凸
反りしたとしても、凹部底面が半導体チップの下面に当
接することが避けられ、基板の凸反りによる半導体チッ
プの浮き上がりが防止される。更に、穴部が形成された
グリーンシートを最上層に積層して焼成すれば、セラミ
ック多層基板の製造に用いられるグリーンシート積層法
で基板表面に凹部を形成することができ、凹部の形成も
容易である。According to the present invention, the recess formed in the inner region of the row of pads on the surface of the substrate faces the lower surface of the semiconductor chip (flip chip), and a certain amount of clearance is provided between the bottom surface of the recess and the semiconductor chip. Is opened. For this reason, even if the ceramic multilayer substrate is convexly warped and the bottom surface of the concave portion is convexly warped, the bottom surface of the concave portion is prevented from coming into contact with the lower surface of the semiconductor chip, and the semiconductor chip is prevented from rising due to the convex warpage of the substrate. It Furthermore, if a green sheet having holes is laminated on the uppermost layer and fired, a concave portion can be formed on the substrate surface by the green sheet laminating method used for manufacturing a ceramic multilayer substrate, and the concave portion can be easily formed. Is.
【０００９】更に、低温焼成用のグリーンシートを積層
し、１０００℃以下で焼成してセラミック多層基板を作
れば、予めグリーンシート上に微細なパターンを印刷に
より容易に形成できると共に、基板の熱膨張係数がアル
ミナ多層基板よりもかなり小さく、半導体チップ（Ｓ
ｉ）の熱膨張係数に近いので、半導体チップをフリップ
チップ方式で基板表面に直接接合しても、その接合部に
発生する熱応力は小さく、熱サイクル疲労による接続不
良の発生が抑えられる。勿論、低温焼成による製造コス
トの削減も期待できる。Further, by stacking green sheets for low temperature firing and firing at 1000 ° C. or less to make a ceramic multilayer substrate, a fine pattern can be easily formed in advance on the green sheets by printing, and the thermal expansion of the substrate can be performed. The coefficient is much smaller than that of the alumina multilayer substrate, and the semiconductor chip (S
Since the coefficient of thermal expansion is close to that of i), even if the semiconductor chip is directly bonded to the substrate surface by the flip chip method, the thermal stress generated at the bonded portion is small, and the occurrence of connection failure due to thermal cycle fatigue can be suppressed. Of course, reduction in manufacturing cost due to low temperature firing can be expected.
【００１０】[0010]
【実施例】以下、本発明の一実施例を図１乃至図４に基
づいて説明する。図１及び図２に示すように、半導体チ
ップ１１の下面外周の４辺部には、それぞれ多数の電極
部１４がほぼ等ピッチで一列に形成され、各電極部１４
にバンプ１５が形成されている。一方、セラミック多層
基板１２の表面には、上記半導体チップ１１の電極部１
４の配列と同じパターンで多数のパッド１３が形成さ
れ、この基板表面のうちのパッド１３の列の内側領域
に、半導体チップ１１の下面に対向する凹部１６が形成
されている。このセラミック多層基板１２の各パッド１
３に対して、フリップチップ方式で半導体チップ１１の
各電極部１４がバンプ１５により接合されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. As shown in FIGS. 1 and 2, a large number of electrode portions 14 are formed in a row at substantially equal pitches on the four sides of the outer periphery of the lower surface of the semiconductor chip 11, and each electrode portion 14 is formed.
Bumps 15 are formed on the. On the other hand, on the surface of the ceramic multilayer substrate 12, the electrode portion 1 of the semiconductor chip 11 is formed.
A large number of pads 13 are formed in the same pattern as the arrangement of No. 4, and a concave portion 16 facing the lower surface of the semiconductor chip 11 is formed in an inner region of the row of pads 13 on the substrate surface. Each pad 1 of this ceramic multilayer substrate 12
3, the electrode portions 14 of the semiconductor chip 11 are joined by the bumps 15 by the flip chip method.
【００１１】次に、基板表面に凹部１６を有するセラミ
ック多層基板１２の製造方法を説明する。まず、ＣａＯ
−Ａｌ2 Ｏ3 −ＳｉＯ2 −Ｂ2 Ｏ3 系のガラス粉末６０
ｗｔ％とアルミナ粉末４０ｗｔ％とを混合した粉体に、
可塑剤（例えばＤＯＰ）、バインダー（例えばアクリル
樹脂）、溶剤（トルエン、キシレン、アルコール類）を
加え、十分に混練して粘度２０００〜４００００ｃｐｓ
のスラリーを作成し、ドクターブレード法によって例え
ば０．３ｍｍと０．０５ｍｍ厚の低温焼成用のグリーン
シート２１，２２（図４参照）を形成する。ここで、
０．０５ｍｍ厚のグリーンシート２２は、最上層に積層
するグリーンシートであり、これに、層間接続用の０．
０５〜１．００ｍｍφ程度のビアホール２３と凹部１６
形成用の角穴部２４とを打抜き型やパンチングマシーン
で打ち抜き形成する。また、０．３ｍｍ厚のグリーンシ
ート２１には、ビアホール２３のみを打ち抜き形成す
る。Next, a method of manufacturing the ceramic multi-layer substrate 12 having the concave portion 16 on the substrate surface will be described. First, CaO
-Al 2 O 3 glass powder 60 -SiO 2 -B 2 O 3 system
powder mixed with 40 wt% of alumina powder,
A plasticizer (for example, DOP), a binder (for example, acrylic resin), a solvent (toluene, xylene, alcohols) are added, and the mixture is sufficiently kneaded to have a viscosity of 2000 to 40,000 cps.
Is prepared, and green sheets 21 and 22 (see FIG. 4) for low-temperature firing having a thickness of 0.3 mm and 0.05 mm, for example, are formed by a doctor blade method. here,
The 0.05 mm-thick green sheet 22 is a green sheet to be laminated on the uppermost layer.
Via hole 23 and recess 16 of about 05 to 1.00 mmφ
The square holes 24 for forming are punched and formed by a punching die or a punching machine. Further, only the via hole 23 is punched and formed on the green sheet 21 having a thickness of 0.3 mm.
【００１２】この後、層間の導体パターン２５を電気的
に接続できるように、各グリーンシート２１，２２のビ
アホール２３にＡｇ系導体材料を充填した後、各グリー
ンシート２１，２２上に、導体パターン２５をＡｇ、Ａ
ｇ−Ｐｄ、Ａｇ−Ｐｔ、Ａｇ−Ｐｄ−Ｐｔ等の導体材料
ペーストを使用してスクリーン印刷すると共に、最上層
に積層される０．０５ｍｍ厚のグリーンシート２２上に
は、フリップチップ接続用の多数のパッド１３も上記導
体材料ペーストを使用してスクリーン印刷する。このよ
うにして導体パターン２５が印刷された複数枚（例えば
４枚）のグリーンシート２１，２２を、位置決め孔によ
り正確に位置決めして積層し、最上層には、フリップチ
ップ接続用の多数のパッド１３が印刷された０．０５ｍ
ｍ厚のグリーンシート２２を積層し、この積層体を例え
ば８０〜１５０℃、５０〜２５０ｋｇ／ｃｍ2 の条件で
熱圧着して一体化する。次いで、この積層体を電気式連
続ベルト炉を使用して、空気中で９００℃、２０分の保
持条件で焼成し、図４に示すようなセラミック多層基板
１２を作成する。このセラミック多層基板１２は、最上
層のグリーンシート２２に形成された角穴部２４が焼成
後に凹部１６となる。Thereafter, the via holes 23 of the green sheets 21 and 22 are filled with an Ag-based conductor material so that the conductor patterns 25 between the layers can be electrically connected, and then the conductor patterns are formed on the green sheets 21 and 22. 25 for Ag, A
A conductive material paste such as g-Pd, Ag-Pt, or Ag-Pd-Pt is used for screen printing, and a 0.05 mm-thick green sheet 22 laminated on the uppermost layer is used for flip-chip connection. A large number of pads 13 are also screen-printed using the conductor material paste. A plurality of (for example, four) green sheets 21 and 22 on which the conductor patterns 25 are printed in this way are accurately positioned and stacked by the positioning holes, and a number of pads for flip-chip connection are provided on the uppermost layer. 0.05m with 13 printed
The green sheets 22 having a thickness of m are stacked, and the stacked body is thermocompression bonded under the conditions of, for example, 80 to 150 ° C. and 50 to 250 kg / cm 2 to be integrated. Next, this laminated body is fired in air at 900 ° C. for 20 minutes using an electric continuous belt furnace to produce a ceramic multilayer substrate 12 as shown in FIG. In this ceramic multilayer substrate 12, the square hole 24 formed in the uppermost green sheet 22 becomes the recess 16 after firing.
【００１３】このようにして作られたセラミック多層基
板１２は、図１（ａ）に示すように、基板表面の凹部１
６が半導体チップ１１（フリップチップ）の下面に対向
し、凹部１６の底面と半導体チップ１１との間にある程
度の隙間が開いた状態となる。このため、図１（ｂ）に
示すように、たとえ、セラミック多層基板１１が凸反り
して、凹部１６の底面が凸反りしたとしても、凹部１６
の底面が半導体チップ１１の下面に当接することが避け
られ、セラミック多層基板１２の凸反りによる半導体チ
ップ１１の浮き上がりが防止され、セラミック多層基板
１２の各パッド１３と半導体チップ１１の各電極部１４
とが確実に接続される。As shown in FIG. 1A, the ceramic multi-layer substrate 12 manufactured in this manner has the concave portion 1 on the substrate surface.
6 is opposed to the lower surface of the semiconductor chip 11 (flip chip), and a certain gap is opened between the bottom surface of the recess 16 and the semiconductor chip 11. Therefore, as shown in FIG. 1B, even if the ceramic multilayer substrate 11 is convexly warped and the bottom surface of the concave portion 16 is also convexly warped, the concave portion 16 is curved.
The bottom surface of the semiconductor chip 11 is prevented from coming into contact with the lower surface of the semiconductor chip 11, the semiconductor chip 11 is prevented from being lifted up due to the convex warp of the ceramic multilayer substrate 12, and each pad 13 of the ceramic multilayer substrate 12 and each electrode portion 14 of the semiconductor chip 11 is prevented.
And are securely connected.
【００１４】本発明者等が行った試験結果によれば、本
実施例のセラミック多層基板１２では、パッド１３の列
の反りは最大１２μｍであり、凹部１６の底面の対角線
の反りは最大２６μｍであり、凹部１６の深さ（５０μ
ｍ）よりも低かった。従って、セラミック多層基板１２
が凸反りしたとしても、凹部１６の底面がパッド１３よ
り高くなることはなく、半導体チップ１１がセラミック
多層基板１２から浮き上がってしまうことがない。従っ
て、本実施例のセラミック多層基板１２を用いると、実
装歩留りが１００％となり、接続不良品は発生しなかっ
た。According to the test results conducted by the present inventors, in the ceramic multilayer substrate 12 of this embodiment, the warp of the rows of the pads 13 is 12 μm at the maximum, and the warp of the diagonal line of the bottom surface of the recess 16 is 26 μm at the maximum. Yes, the depth of the recess 16 (50μ
It was lower than m). Therefore, the ceramic multilayer substrate 12
Even if the convex warps, the bottom surface of the concave portion 16 does not become higher than the pad 13, and the semiconductor chip 11 does not rise above the ceramic multilayer substrate 12. Therefore, when the ceramic multilayer substrate 12 of this example was used, the mounting yield was 100%, and no defective connection product was generated.
【００１５】これに対し、図５（比較例）に示すよう
に、凹部形成用の０．０５ｍｍ厚のグリーンシート２２
を用いないで、０．３ｍｍ厚のグリーンシート２１のみ
を積層して焼成したセラミック多層基板１７を用いた場
合、本発明者が行った試験結果によれば、パッド１３の
列の反りは最大１１μｍであり、チップ接合面の対角線
の反りは最大２４μｍであった。このようなセラミック
多層基板１７にフリップチップ方式で半導体チップ１１
を実装した場合には、セラミック多層基板１７が凸反り
していると、図６に示すように、半導体チップ１１がセ
ラミック多層基板１７から浮き上がってしまう。本発明
者が行った試験結果によれば、図５のセラミック多層基
板１７を用いると、実装歩留りが８９％となり、接続不
良品が１１％も発生した。On the other hand, as shown in FIG. 5 (comparative example), a 0.05 mm thick green sheet 22 for forming recesses is formed.
When using the ceramic multilayer substrate 17 in which only the green sheet 21 having a thickness of 0.3 mm is laminated without firing, according to the test result conducted by the present inventor, the warp of the row of the pads 13 is 11 μm at maximum. And the maximum warp of the diagonal line of the chip bonding surface was 24 μm. The semiconductor chip 11 is formed on the ceramic multilayer substrate 17 by the flip chip method.
If the ceramic multilayer substrate 17 is convexly warped in the case of mounting, the semiconductor chip 11 is lifted from the ceramic multilayer substrate 17 as shown in FIG. According to the test results conducted by the present inventor, when the ceramic multilayer substrate 17 of FIG. 5 was used, the mounting yield was 89% and the connection failure was 11%.
【００１６】ところで、図３に示すように、セラミック
多層基板１２，１７の反りが円周で近似できるとすれ
ば、チップ接合面の高低差ｈは次式で算出できる。 ｈ＝ａ×ｓｉｎθ ……（１） この場合、θは小さく、ａ＝ｒ×θ、ｓｉｎθ＝θ、θ
＝Ｌ／ｒと近似できるので、（１）式は次のようにな
る。 ｈ＝ｒ×θ2 ＝Ｌ2 ／ｒ ……（２） この（２）式において、反りの曲率半径ｒが一定と仮定
すると、チップ接合面の高低差ｈは長さＬの２乗に比例
するので、本実施例と図５（比較例）とを比較した場
合、チップ接合面の高低差ｈの比が （チップ接合面の辺÷対角線）2 ＝１／２ となる。つまり、本実施例のセラミック多層基板１２
は、反りによるチップ接合面の高低差ｈが図５（比較
例）の場合の１／２となり、フリップチップ実装の信頼
性を向上できることが理論上からも証明される。By the way, as shown in FIG. 3, if the warp of the ceramic multilayer substrates 12 and 17 can be approximated by the circumference, the height difference h of the chip bonding surface can be calculated by the following equation. h = a × sin θ (1) In this case, θ is small, and a = r × θ, sin θ = θ, θ
Since it can be approximated as = L / r, the equation (1) is as follows. h = r × θ 2 = L 2 / r (2) In this equation (2), assuming that the curvature radius r of the warp is constant, the height difference h of the chip joint surface is proportional to the square of the length L. Therefore, when this example is compared with FIG. 5 (comparative example), the ratio of the height difference h of the chip joint surface is (the side of the chip joint surface / diagonal line) 2 = 1/2. That is, the ceramic multilayer substrate 12 of this embodiment
Shows that the height difference h of the chip joint surface due to the warpage becomes 1/2 of that in the case of FIG. 5 (comparative example), and it is theoretically proved that the reliability of flip chip mounting can be improved.
【００１７】尚、図４の例では、０．３ｍｍ厚のグリー
ンシート２１を３枚積層したが、これを２枚以下又は４
枚以上積層するようにしても良い。また、グリーンシー
ト２１，２２の厚みは０．３ｍｍ、０．０５ｍｍに限定
されず、この厚みを用途等に応じて適宜変更しても良い
ことは言うまでもない。また、本実施例は、セラミック
多層基板１２を低温焼成セラミック多層基板により構成
したので、セラミック多層基板１２の熱膨張係数が半導
体チップの熱膨張係数に近くなるという利点があるが、
低温焼成セラミックに代えて、アルミナ基板により構成
しても良く、この場合でも本発明の所期の目的は達成で
きる。In the example of FIG. 4, three green sheets 21 each having a thickness of 0.3 mm are laminated, but two or less or four green sheets 21 are laminated.
You may make it laminate | stack more than one sheet. Further, it goes without saying that the thickness of the green sheets 21 and 22 is not limited to 0.3 mm and 0.05 mm, and the thickness may be appropriately changed depending on the application. Further, in this embodiment, since the ceramic multilayer substrate 12 is constituted by the low temperature fired ceramic multilayer substrate, there is an advantage that the coefficient of thermal expansion of the ceramic multilayer substrate 12 is close to that of the semiconductor chip.
Instead of the low temperature fired ceramic, an alumina substrate may be used, and even in this case, the intended object of the present invention can be achieved.
【００１８】その他、本発明は、凹部１６の形状は四角
形状に限定されず、円形等、他の形状であっても良い
等、要旨を逸脱しない範囲内で種々変更して実施できる
ことは言うまでもない。In addition, it goes without saying that the present invention is not limited to the quadrangular shape of the concave portion 16 and may have other shapes such as a circular shape and the like, and various modifications can be made without departing from the scope of the invention. .
【００１９】[0019]
【発明の効果】以上の説明から明らかなように、本発明
のセラミック多層基板によれば、基板表面のパッドの列
の内側領域に形成された凹部が半導体チップ（フリップ
チップ）の下面に対向し、両者間に隙間が開いた状態と
なるため、この隙間により基板の凸反りを逃げることが
できて、基板の凸反りによる半導体チップの浮き上がり
を防止することができる。従って、従来のように基板表
面を研磨しなくても、基板の凸反りによる半導体チップ
の浮き上がりを防止することができて、フリップチップ
の接続信頼性を向上できると共に、パッド印刷も焼成前
に行うことができて、ファインパターン化・低コスト化
の要求も満たすことができる（請求項１）。As is apparent from the above description, according to the ceramic multilayer substrate of the present invention, the recesses formed in the inner region of the row of pads on the surface of the substrate face the lower surface of the semiconductor chip (flip chip). Since a gap is opened between the two, the convex warpage of the substrate can be escaped by this gap, and the semiconductor chip can be prevented from rising due to the convex warp of the substrate. Therefore, it is possible to prevent the semiconductor chip from being lifted up due to the convex warp of the substrate without polishing the substrate surface as in the conventional case, and it is possible to improve the connection reliability of the flip chip and also perform the pad printing before firing. Therefore, it is possible to satisfy the requirements for fine patterning and cost reduction (Claim 1).
【００２０】しかも、請求項２では、穴部が形成された
グリーンシートを最上層に積層して焼成することにより
基板表面に凹部を形成したので、セラミック多層基板の
製造に用いられるグリーンシート積層法で基板表面に凹
部を容易に形成することができ、凹部の形成も容易であ
る。Further, according to the second aspect of the present invention, the green sheet having holes is laminated on the uppermost layer and baked to form the concave portion on the substrate surface. Thus, the concave portion can be easily formed on the substrate surface, and the concave portion can be easily formed.
【００２１】また、請求項３では、低温焼成用のグリー
ンシートを用いたので、セラミック多層基板の熱膨張係
数を半導体チップの熱膨張係数に近づけることができ
て、接続の信頼性を向上させることができる。Further, in claim 3, since the green sheet for low temperature firing is used, the coefficient of thermal expansion of the ceramic multilayer substrate can be brought close to the coefficient of thermal expansion of the semiconductor chip, and the reliability of connection is improved. You can
【図１】（ａ）は本発明の一実施例を示すフリップチッ
プ実装部分の縦断面図、（ｂ）はセラミック多層基板が
凸反りした時のフリップチップ実装部分の状態を示す縦
断面図である。1A is a vertical cross-sectional view of a flip-chip mounting portion showing an embodiment of the present invention, and FIG. 1B is a vertical cross-sectional view showing a state of the flip-chip mounting portion when a ceramic multilayer substrate is warped. is there.
【図２】フリップチップ実装部分の平面図である。FIG. 2 is a plan view of a flip-chip mounting portion.
【図３】反りによるチップ接合面の高低差ｈの算出方法
を説明する図である。FIG. 3 is a diagram illustrating a method of calculating a height difference h of a chip bonding surface due to warpage.
【図４】本発明の一実施例におけるセラミック多層基板
の要部を示す縦断面図である。FIG. 4 is a vertical sectional view showing a main part of a ceramic multilayer substrate according to an embodiment of the present invention.
【図５】比較例のセラミック多層基板の要部を示す縦断
面図である。FIG. 5 is a vertical sectional view showing a main part of a ceramic multilayer substrate of a comparative example.
【図６】従来（比較例）のセラミック多層基板が凸反り
した時のフリップチップの接合状態を示す縦断面図であ
る。FIG. 6 is a vertical cross-sectional view showing a bonded state of a flip chip when a conventional (comparative example) ceramic multilayer substrate is convexly warped.
１１…半導体チップ（フリップチップ）、１２…セラミ
ック多層基板、１３…パッド、１４…電極部、１５…バ
ンプ、１６…凹部、２１，２２…グリーンシート、２３
…ビアホール、２４…角穴部、２５…導体パターン。11 ... Semiconductor chip (flip chip), 12 ... Ceramic multilayer substrate, 13 ... Pad, 14 ... Electrode part, 15 ... Bump, 16 ... Recess, 21, 22 ... Green sheet, 23
... via hole, 24 ... square hole, 25 ... conductor pattern.
Claims (3)
プ方式で実装する多数のパッドが列設されたセラミック
多層基板において、前記基板表面のうちの前記パッドの
列の内側領域に、前記半導体チップの下面に対向する凹
部を形成したことを特徴とするセラミック多層基板。1. A ceramic multi-layer substrate in which a large number of pads for flip-chip mounting a semiconductor chip on a surface of a substrate are arranged in a row, and a lower surface of the semiconductor chip is located in an area inside the row of the pads on the surface of the substrate. A ceramic multi-layer substrate, characterized in that a concave portion is formed opposite to.
ラミック多層基板であって、前記パッドの列の内側領域
に穴部が形成されたグリーンシートを最上層に積層して
焼成することで、基板表面に前記凹部を形成したことを
特徴とする請求項１に記載のセラミック多層基板。2. A ceramic multilayer substrate formed by stacking and firing green sheets, wherein the green sheet having holes formed in the inner regions of the pad rows is laminated on the uppermost layer and fired. The ceramic multilayer substrate according to claim 1, wherein the recess is formed on the surface.
１０００℃以下で焼成して成ること特徴とする請求項１
又は２に記載のセラミック多層基板。3. Laminating green sheets for low temperature firing,
2. The composition is formed by firing at 1000 ° C. or lower.
Or the ceramic multilayer substrate according to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6324496A JP2945291B2 (en) | 1994-12-27 | 1994-12-27 | Ceramic multilayer substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6324496A JP2945291B2 (en) | 1994-12-27 | 1994-12-27 | Ceramic multilayer substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08181251A true JPH08181251A (en) | 1996-07-12 |
| JP2945291B2 JP2945291B2 (en) | 1999-09-06 |
Family
ID=18166462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6324496A Expired - Lifetime JP2945291B2 (en) | 1994-12-27 | 1994-12-27 | Ceramic multilayer substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2945291B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10173089A (en) * | 1996-12-12 | 1998-06-26 | Nec Corp | Wireless chip mounting board, wireless chip mounting structure and manufacturing method of the wireless chip mounting board |
| JP2005108950A (en) * | 2003-09-29 | 2005-04-21 | Matsushita Electric Ind Co Ltd | Ceramic modular component and its manufacturing method |
| CN110858577A (en) * | 2018-08-22 | 2020-03-03 | 丰田自动车株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN111446213A (en) * | 2020-03-23 | 2020-07-24 | 维沃移动通信有限公司 | Circuit board and electronic equipment |
-
1994
- 1994-12-27 JP JP6324496A patent/JP2945291B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10173089A (en) * | 1996-12-12 | 1998-06-26 | Nec Corp | Wireless chip mounting board, wireless chip mounting structure and manufacturing method of the wireless chip mounting board |
| JP2005108950A (en) * | 2003-09-29 | 2005-04-21 | Matsushita Electric Ind Co Ltd | Ceramic modular component and its manufacturing method |
| EP1519641A3 (en) * | 2003-09-29 | 2005-08-24 | Matsushita Electric Industrial Co., Ltd. | Module and method of manufacturing module |
| US7231712B2 (en) | 2003-09-29 | 2007-06-19 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a module |
| CN100369532C (en) * | 2003-09-29 | 2008-02-13 | 松下电器产业株式会社 | Module and method of manufacturing module |
| CN110858577A (en) * | 2018-08-22 | 2020-03-03 | 丰田自动车株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN110858577B (en) * | 2018-08-22 | 2023-03-21 | 株式会社电装 | Semiconductor device with a plurality of semiconductor chips |
| CN111446213A (en) * | 2020-03-23 | 2020-07-24 | 维沃移动通信有限公司 | Circuit board and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2945291B2 (en) | 1999-09-06 |
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