JPH08180687A - Josephson latch circuit - Google Patents

Abstract

PURPOSE: To decrease a number of input signals to a circuitry, to reduce a number of I/O pins and to improve the efficiency of the circuit by writing magnetic flux into a data holding loop by directly inputting only a true signal. CONSTITUTION: When the calculated result in the operating region of a Josephson logic circuit is '1', an input 1 from a product arithmetic circuit is passed through a separator circuit 25, a current is made to flow through a magnetism holding loop composed of a Josephson junction 7 and an inductance, the Josephson junction 7 is made to be a superconducting state and a persistent current is made to flow through the loop. When the calculated result is '0', the product arithmetic circuit 24 is not switched over and the circuit is not operated. When the persistent current does not flow at the rising time of a gate current, since a Josephson junction 13 becomes a voltage state, the read signal is outputted to an auxiliary signal output line 23 by making a current flow through a Josephson junction 14. By sending the output of a true signal line 22 to an inductance 19, resetting is performed by means of a pulse. At this time, mal-function due to the pulse is prevented by the separator circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit using a Josephson junction, and more particularly, to a logic circuit that uses a true signal and a complementary signal in a circuit, and temporarily stores a result of a logical operation in a previous clock cycle. , A true signal and a complementary signal.

[0002]

2. Description of the Related Art In a Josephson junction element logic gate based on a latching operation, an AC power supply system in which a latching operation is reset by returning a power supply current to 0 every clock cycle is generally adopted. In order to form a logic circuit in this manner, while the power supply current is 0,
A latch circuit that essentially maintains the information of the previous clock cycle is required. Further, in a logic circuit using a Josephson junction, a timing signal is required to configure an inverter, and the configuration is more difficult than that of a semiconductor, which hinders high-speed operation. Therefore, a latch circuit that outputs a true signal and a complementary signal of input information at the same time is indispensable for improving the performance of a logic circuit using a Josephson element.

Conventionally, several latch circuits have been proposed and studied. Here, a conventional example shown in FIG. 5 will be described. The operation of this conventional latch circuit is described in detail in Japanese Patent Application Laid-Open No. 2-244495, and will be described only briefly here. FIG. 5 shows an equivalent circuit of a conventional example. In FIG. 5, 501 is a true signal input line and 502 is a true signal input line.
Is a complement signal input line, 503, 508, 519 are Josephson junctions, 504, 505, 506 are inductances,
07 is a sense circuit (two-junction SQUID) composed of a Josephson junction and an inductance, 509 is a gate current line,
510 and 511 are output resistors, 512 is a true signal output line, and 5
13 is a complementary signal output line, 514 is a latch enable signal line, 515 and 516 are product operation circuits, 517 is a true signal input line, 518 is a complementary signal input line, and Josephson junction 5
03 and the inductances 504, 505 and 506 form a data holding loop.

When the result of the calculation in a certain clock cycle is 1, a current flows through the true signal input line 501, and when the result is 0, a current flows through the complementary signal input line 502. The current flowing through the true signal input line 501 becomes a current flowing through the magnetic flux holding loop through the inductance 504 by magnetic coupling, and the Josephson junction 503 switches to the voltage state to store the magnetic flux quantum. A permanent current corresponding to the flux quantum flows through the holding loop. When the calculation result is 0, the current induced in the holding loop through the magnetic coupling between the complementary signal input line 502 and the inductance 505 is the same as the direction of the current induced by the input of the true signal, that is, the direction of the permanent current. The Josephson junction 503 is designed to be in a voltage state when superimposed on a permanent current, and not in a voltage state when not superimposed. Then, when a magnetic flux is written in the holding loop, the complementary signal input cancels out the quantum magnetic flux in the magnetic flux loop, and when no magnetic flux is written, the state remains as it is.
In this way, the information of the calculation result is recorded. To read the information, the inductance 50 in the holding loop is used.
6 is performed by a sense circuit that receives a magnetic flux induced through magnetic coupling between the sense circuit 6 and the sense circuit 507 as an input. The current value of the sense circuit that shifts to the voltage state differs depending on whether or not a magnetic flux is written in the magnetic flux holding loop. The relationship of the current values is represented by the magnitude relationship with the Josephson junction 508: (voltage state transition current when magnetic flux exists) <(voltage state transition current of Josephson junction 508) <(voltage state transition when no magnetic flux exists) Current)), the sense circuit 507 switches only when the magnetic flux is written in the holding loop, and when the magnetic flux is not written, the Josephson junction 508 switches before the sense circuit 507. Come to do. When the sense circuit 507 switches, the gate current supplied from the gate current line 509 flows through the resistor 511 to the true signal output line 512 (the resistor 510 also branches, but the branched current flows through the Josephson junction 519). When the Josephson junction 508 is switched, the gate current flows through the resistor 510, to the Josephson junction 519, and to the Josephson junction 519.
And flows to the complementary signal output line 513. That is, a true signal and a complementary signal are output according to the presence or absence of the holding magnetic flux in the holding loop (corresponding to data “1” and “0”). In this way, a Josephson latch circuit can be realized.

[0005]

However, the above-mentioned latch circuit has the following problems. Firstly, the writing of data always requires two signals, a true signal and a complementary signal. This means that a dual rail system must be employed when building a logic circuit. The dual-rail method is a method commonly used in circuits using Josephson junctions.However, it is necessary to prepare a gate to maintain the complementary signal even where a complementary signal is not required, and especially the Josephson logic When trying to realize a complex logic system by combining gates, there is a possibility that the total number of gates will increase without meaning. The same applies to the number of pins of the input / output portion of the chip. For example, in the case of a 64-bit multiplier, 128 pins are required for input and 64 pins are required for output. , 384 input / output pins are required. It is undesirable to implement such chips with Josephson chips that must be cooled with liquid helium.

Secondly, magnetic coupling is used for coupling the signal lines. Magnetic coupling is usually realized by stacking wiring layers, but magnetic coupling is harder to control than direct coupling. Therefore, the degree of coupling is low and the degree of dependence on the process is high, which makes the design more difficult. To realize the circuit described above, the inductances 504, 5
Numeral 05 is a true and complementary signal independent magnetic coupling input inductance, so both must have a large value to gain each mutual inductance value. 501,50
The current that must be passed through 2 must also be increased. In addition, the inductance 506 and the sense circuit 50
The same applies to the inductance value of the inductance portion of the circuit 7, which eventually increases the wiring area of the circuit and prevents the circuit from being downsized. Further, the relationship between the LI product of the sense circuit 507 and the write magnetic flux induced between the inductance 506 and the inductance of the sense circuit 507 is an important relationship that determines the operation margin of the latch circuit. As far as we can, it is very difficult to optimize this relationship. The reason is that the sense circuit 507
This is because even if the LI product is optimized by setting the appropriate inductance, the mutual inductance corresponding to the inductance value cannot be obtained, so that the magnetic flux written to the sense circuit 507 becomes small. This is
This means that the operation margin of the latch circuit is reduced. Such a latch circuit is not desirable as a latch circuit to constitute an LSI.

[0007]

The Josephson latch circuit of the present invention comprises a data holding loop composed of a single or a plurality of Josephson junctions and a superconducting inductance, an isolation circuit directly coupled to the data holding loop, and A signal input line directly connected to the separation circuit, a sense circuit directly connected to the data holding loop, and an output for reading the information held in the data holding loop by the sense circuit and generating a true signal output and a complementary signal output. And a reset pulse circuit in which a true signal output of the output circuit is branched and magnetically coupled to a part of the data holding loop.

[0008]

The magnetic flux is written into the data holding loop according to the present invention by a method of directly inputting only the true signal of the calculation result after passing through the separation circuit. The write flux is read by the SQUID directly coupled to the holding loop.
Since the direct coupling method is adopted, the circuit parameter of the SQUID can be adjusted to the optimum sensitivity. The write magnetic flux is reset by utilizing the fact that the magnetic flux exists only when a true signal is output, and a part of the true signal output is passed through a reset pulse circuit to cancel the permanent current of the holding loop. The pulses are so short that they do not affect the input in the next clock cycle. Malfunction due to the dynamic effect of pulse generation is prevented by using a separation circuit.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing an equivalent circuit of an embodiment of the Josephson latch circuit according to the present invention. Separation circuit 2
5, the resistor 4, the inductor 6, and the resistor 5 are sequentially connected in series from the signal input line 1, and the inductor 6 and the resistor 5 are connected.
Are grounded via a Josephson junction 3. Josephson junction 7, inductance 10, inductance 9, and inductance 8 are sequentially connected in a loop,
A separation circuit is connected between the Josephson junction 7 and the inductance 10, and the inductance 9 and the inductance 8
Is grounded. The Josephson junction 11, the Josephson junction 12, the inductance 9 and the inductance 8 are connected in a loop, and the Josephson junction 11
And between the Josephson junction 12 are output. This output is connected to the true signal output line 22 via the resistor 17. This output is connected to an auxiliary signal output line 23 via a Josephson junction 13, a resistor 15, and a resistor 16, and a gate current line 26 is connected between the Josephson junction 13 and the resistor 15. 15 and the resistor 16 are grounded via the Josephson junction 14. In the reset pulse circuit, the true signal output line 22 is grounded via a resistor 20 and a resistor 21, the resistor 20 and the resistor 21 are grounded via a Josephson junction 18 and an inductance 19, and the inductance 19 is Are combined.

When the phase difference of the order parameter of the Josephson junction 7 is θ, the characteristic with the current Ie input from the output resistance 5 of the separation circuit is as shown in FIG. In FIG. 2, 201 to 206 show operating points. This characteristic can be designed by determining the critical current value of the Josephson junction 7 and the values of the inductances 8, 9, and 10.

FIG. 3 is an example of a gate current waveform of the Josephson logic circuit, schematically showing the case of unipolar AC driving. Reference numeral 301 denotes an operation area, 302 denotes a data write area, 303 denotes a data holding area, 304 denotes a machine cycle, and 305 denotes a data read area. The result calculated in the operation area 301 shown in FIG. 3 is input from the signal input line 1 to the product operation circuit 24. When the calculation result is 1, when the latch enable signal is input, the signal is transmitted to the separation circuit 25 via the product operation circuit 24. The critical current value of the Josephson junction 3 in the separation circuit 25 is designed to be smaller than the input current value from the integrating circuit, and the input current eventually becomes the Josephson junction 7 and the inductance 8,
A magnetic flux holding loop composed of 9 and 10 flows. The role of the separation circuit will be described later. The current flowing in the flux holding loop causes the Josephson junction 7 to transition to a voltage state, recording one flux quantum in the flux holding loop. That is, FIG.
At, the operating point moves through 201 to 202. When the gate current waveform falls, the operating point shifts to 203, and data is held in the data holding area 303. At this time, the Josephson junction returns to the superconducting state, and a permanent circulating current flows through the magnetic flux holding loop. When the calculation result is 0, the product operation circuit 24 does not switch, and no current flows through the separation circuit. That is, the state of the magnetic flux holding loop does not change.

Reading is performed when the gate current rises. When a circulating current is flowing through the data holding loop, the critical current values of the inductances 8 and 9 and the Josephson junctions 11 and 12 constituting the read SQUID are smaller than the critical current value of the Josephson junction 13. When the circulating current is not flowing through the holding loop, the SQUID is designed to have a critical current value larger than that of the Josephson junction 13. When the circulating current is flowing, first, as the gate current increases, the SQUID
Is switched, the current flows through the resistor 17, and the true signal output line 2
The output appears at 2. At the same time, the current shunts to the resistor 15, but the current flows to the ground through the Josephson junction 14. When the circulating current is not flowing, when the gate current increases, the Josephson junction 13 switches to the voltage state first, and the current flows to the resistor 15 and first flows to the Josephson junction 14 as it is. ,
14 is set to the same critical current value, so that Josephson 1
4 also switches immediately, and eventually the current passes through the resistor 16 and appears on the auxiliary signal output line 23. No current flows through the true signal output line.

Reading and writing operations of the latch circuit are performed by the method as described above. However, the recorded flux holding loop must be reset every clock. In the conventional example, the complementary signal input is designed to contribute to the magnetic flux reset of the magnetic flux holding loop, but in the present invention, the work is performed using the reset circuit. In the present invention, the input is 1, that is, the true signal is 1
The magnetic flux is written only when. Therefore, resetting
It should be performed only when the next output is output to the true signal line. In the present invention, resetting is performed using a part of the output line from the true signal output line 22. The reset must not disturb the signal writing operation of the data holding loop in the next operation area. Therefore, a reset operation is performed using a pulse signal. That is, a part of the true signal output line is sent to the inductance 19 magnetically coupled to the holding loop inductance 10 through the resistor 20 and the Josephson junction 18. The critical current value of the Josephson junction 18 is designed to be smaller than the current flowing for resetting. Then, the Josephson junction 18 switches immediately after the reset current flows, the pulse current flows through the inductance 19, and the rest flows into the resistor 21. In this way, the reset operation can be completed without affecting the signal input to the data holding loop in terms of timing.

Since the reset operation is performed by a pulse current, a larger amount of a current pulse must be applied as compared with a steady reset current performed in a conventional example. Therefore, the dynamic effect of flowing a large current in a very short time cannot be ignored, leading to a reduction in the operating margin. In the case of configuring an LSI, the most probable malfunction is caused by this dynamic effect even when the calculation result of the logic gate configuring the LSI, which is located in the preceding stage of the signal input line 1, is 0, that is, when the input is Even when there is no switch, switching is performed only by the gate current, and current flows through the signal input line 1. Therefore, the separation circuit 25 is provided. The embodiment shows one example. The resistors 4 and 5 and the inductance 6 are used as circuit parameters for suppressing a steep current change with time, and the preceding gate is caused by leakage current from the holding loop induced by the reset pulse of the Josephson junction 3 and other malfunctions. When switching is performed only by the gate current, the input current is set to be absorbed so that the operation by the dynamic effect at the time of magnetic flux reset is separated from the previous circuit.

Although the latch circuit of the present invention operates as described above, the reason why the input signal line and the portion of the read circuit using the SQUID are not of the magnetic coupling type as in the conventional example but are of the direct coupling type. An example is described below in connection with the basic design of the reading sensitivity. FIG. 4 is a very simplified drawing of the magnetic flux holding loop and the read SQUID. In FIG. 4, 401, 406, and 407 represent Josephson junctions, 402, 403, and 404 represent self-inductances, and 405 represents a mutual inductance between 402 and 404. The inductance 403 is equivalent to the reset circuit magnetic coupling inductance 10 in this embodiment. Here, each circuit parameter amount is represented by L1 for the inductance 402 and L40 for the inductance.
3 L3, inductor 404 Lr, the mutual inductance 405 M, the Josephson junction 406 and 407 is assumed to be I _0. In the logic circuit using the Josephson junction, magnetic coupling is obtained by stacking different wiring layers. Therefore, the following relationships can be established between these parameters.

M = α × Lr (1) Lr = β × L1 (2) α and β are constants, and have different values between the magnetic coupling type and the direct coupling type, as described later. Further, in order to obtain the optimum sensitivity of the reading SQUID, assuming that the circulating current when the magnetic flux is written in the holding loop is Icir with respect to the LI product and the writing magnetic flux, a typical setting for obtaining high sensitivity is as follows. _{, Lr × I 0 = Φ 0} /4 (3) Icir = Φ 0 / (L1 + L3) (4) M × Icir = Φ 0/2 (5) and the like. From Equations (1) to (5), L3 = (2 × α × β−1) × Φ ₀ / (4 × β × I ₀ ) (6) Substitute a typical value into Equation (6), Find L3. In the case of magnetic coupling, α = 0.7, β = 0.5, I ₀ = 0.1 (m
In A), L3 = -3.105 (pH) <0. on the other hand,
Taking a direct bond, α = 1, β = 1, I ₀ = 0.1 (m
In A), L3 = 5.175 (pH). In the case of magnetic coupling, it can be clearly seen that it is impossible to design to satisfy the relationships of equations (3) to (5). Further, when the loop is actually laid out, an extra inductance of about 1 (pH) usually occurs. For this reason, it is inevitable to form a circuit of the flux coupling type with a parameter set that remarkably lowers the sensitivity. If a circuit is configured using one of the linear combinations, it can be brought to an operating point where high-sensitivity operation is possible. In this case, the largest inductance is L3, but the reset pulse portion which is the only magnetically coupled in the present invention, that is, the portions of the inductances 19 and 10, require the largest area. That also contributes to the miniaturization of the circuit area.

As described above, a Josephson latch circuit can be realized by using this circuit. This circuit is a latch circuit for a unipolar AC drive system that can operate only with a true signal at the input. As the output, a true signal and a complementary signal are generated.

[0019]

The latch circuit of the present invention does not require any timing sequence for its operation which can be used in a unipolar AC drive scheme. Since only one true signal is needed to operate the present latch circuit, it is possible to contribute to the reduction of I / O pins. In addition, the loop for data retention uses a single Josephson junction and employs a method of directly coupling to the loop to read input and loop information, thus improving read sensitivity and increasing circuit occupation area. It greatly contributes to downsizing.

[Brief description of drawings]

FIG. 1 is a diagram showing an equivalent circuit of one embodiment of the present invention.

FIG. 2 is a diagram showing a current-phase characteristic of a phase difference of an order parameter of a Josephson junction in a holding loop and an input current to the holding loop.

FIG. 3 is a diagram illustrating an example of a gate current waveform of a Josephson logic circuit.

FIG. 4 is a simplified drawing of a magnetic flux holding loop and a read SQUID portion.

FIG. 5 is a diagram showing an equivalent circuit of a conventional example.

[Description of Reference Signs] 1 signal input line 2,514 latch enable signal line 3,7,11,12,13,14,18,401,40
6,407,503,508 Josephson junction 4,5,15,16,17,20,21,510,51
1 Resistance 6,8,9,10,19,402,403,404,5
04,505,506 Inductance 22,512 True signal output line 23,513 Complementary signal output line 24,515,516 Product arithmetic circuit 25 Separation circuit 26,509 Gate current line 201,202,203,204,205,206 Operating point 301 Operation area 302 Data writing area 303 Data holding area 304 Machine cycle 305 Data reading area 405 Mutual inductance 501,517 True signal input line 502,518 Complementary signal input line 507 Sense circuit (SQUID)

Claims (3)

[Claims] 1. A data retention loop comprising a single or a plurality of Josephson junctions and a superconducting inductance, a separation circuit directly coupled to the data retention loop, a signal input line directly coupled to the separation circuit, and the data. A sense circuit directly coupled to the holding loop, an output circuit that reads the information held in the data holding loop by the sense circuit and generates a true signal output and a complementary signal output, and a true signal output of this output circuit is branched. A Josephson latch circuit, comprising: a reset pulse circuit magnetically coupled to a part of the data holding loop. 2. A first resistance, a first inductance, and a second resistance are sequentially connected in series from a signal input line, and the first inductance and the second resistance are connected via a first Josephson junction. Grounded isolation circuit, second Josephson junction, second inductance and third
And the fourth inductance are sequentially connected in a loop, the space between the second Josephson junction and the second inductance is connected to the separation circuit, and the space between the third inductance and the fourth inductance is grounded. A third data processing loop, a third Josephson junction, a fourth Josephson junction, the third inductance and the fourth inductance connected in a loop, and a third Josephson junction and a fourth Josephson junction. And a sense circuit whose output is between the fifth Josephson junction and the third
Is connected to the complementary signal output line through the resistor and the fourth resistor in order, and the gate current line is connected between the fifth Josephson junction and the third resistor, and the third resistor and the fourth resistor are connected. 6th interval
An output circuit in which the output of the sense circuit is connected to a true signal output line via a fifth resistor; and the true signal output line is connected to a sixth resistor and a seventh resistor. A sixth resistor and a seventh resistor are grounded via a seventh Josephson junction and a fifth inductance, and the fifth inductance is magnetically connected to the second inductance. And a coupled reset pulse circuit. 3. The Josephson latch circuit according to claim 2, wherein a critical current value of the first Josephson junction is set to be smaller than a current value from a signal input line, and a circulating current is supplied to the data holding loop. 3
And the third and fourth Josephson devices when the critical current value of the fourth Josephson junction is smaller than the critical current values of the fifth and sixth Josephson junctions and when no circulating current flows. A Josephson latch circuit, wherein the critical current value of the junction is set to be larger than the critical current values of the fifth and sixth Josephson junctions.