JPH08180080A - Logic simulator - Google Patents

Abstract

PURPOSE: To provide efficient simulation by plural simulators by using the logic simulators on the market as they are. CONSTITUTION: A logic simulator 3 executes the test instruction part of a test program 2 and executes the simulation of a simulation object logic 5. An instruction interpreter 4 executes the pre-processing instruction and post-processing instruction parts of the test program 2. An interface logic block 51 is embedded in the simulation object logic 5, and information 6 required for a change between the logic simulator 3 and the instruction interpreter 4 is mutually transmitted. Thus, it is not necessary to especially alter the logic simulator so as to connect it with the instruction interpreter but the logic simulators on the market can be used as they are.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation device for an information processing device, and more particularly to a device for executing a logic simulation of an information processing device (logic device under test) using logic simulators having different functions.

[0002]

2. Description of the Related Art Conventionally, a gate level logic simulator (HA) has been used as a means for efficiently verifying a logic device under test.
There is a TDHAL system combining L) and an instruction level simulator (TD). In the simulation target program (test program), the test instruction portion is generally only a few percent, and the instruction level simulator (TD) is several hundred times faster than the gate level logic simulator (HAL). Therefore, in the TDHAL system, Only the test instruction part of the simulation target program is executed by the logic simulator (HAL), and the other parts are executed by the instruction level simulator (TD).

FIG. 6 shows a conventional configuration example of this type of TDHAL system, which is a HAL control unit 601 and an instruction level simulator (TD) 602 on a host computer 600.
And a logic simulator (HAL) 610 connected to the channel of the host computer 600. The transfer information between the two, that is, the software such as the simulation target program 620, the contents of visible registers and memories in the logic device under test,
It is passed by inter-task communication on the host computer 600. The HAL control unit 601 edits this transfer information into a memory representation in the logic simulator (HAL) 610 and transfers it to the logic simulator (HAL) 610.
A start instruction is issued to the logic simulator (HAL) 610. The logic simulator (HAL) executes the test instruction on the simulation target logic 611 (executes the logic simulation), and when it detects the end of the test instruction portion, H
The AL controller 601 is interrupted and the HAL controller 60 is interrupted.
1 receives the instruction level simulator (TD) 60
Transfer to 2 and pass the information. As a result, conventional TDHA
In the L system, an instruction level simulator (TD) and a logic simulator (HAL) can be connected.

On the other hand, also in the logic simulation apparatus disclosed in, for example, Japanese Patent Laid-Open No. 02-268341, the test program is executed by alternately executing the logic simulator and the virtual computer, as in the TDHAL system. FIG. 7 is a diagram for explaining this. The communication module 712 is provided in the device simulation program 700, the communication module 712 is called from the logic simulator 710, the transfer information 730 is set in the communication module 712, and The computer 720 is called and processed.

[0005]

SUMMARY OF THE INVENTION In the above conventional technique,
The HAL control unit or the communication module, from the simulation target logic, transfer information, that is, software,
A simulator such as a gate level / instruction level by extracting and editing signal values of visible memory and registers and passing them to another type of simulator and substituting the transfer information received from another type of simulator into the simulation target logic. Connection is possible. However, in a general (general-purpose) simulator, it is not possible to directly extract the signal value in the simulation target logic or substitute the signal value from the control program outside the simulator. In order to connect and use a plurality of simulators having different functions by the above conventional technique, it is necessary to create the simulator itself by the control program so that the signal operation in the simulation target logic can be performed.
It has a drawback that it cannot be applied as it is to general simulators.

It is an object of the present invention to provide a logic simulator device which realizes a logic simulation, which is carried out in a conventional DHAL system, by using a general logic simulator as it is.

[0007]

The present invention comprises a first logic verification means and a second logic verification means having a function different from that of the first logic verification means, and the first and second logic verification means are provided. In the logic simulation apparatus for alternately activating the logic verification means of (1) to pseudo-verify the logic device under test, between the first logic verification means and the second logic verification means in the simulation target logic of the logic device under test. This is to add an interface logic block for mutually transmitting information necessary for transfer (transfer information).

[0008]

The interface logic block added to the simulation target logic performs extraction and substitution of signal values as the operation of the simulation target logic. Therefore, the function of the interface logic block does not depend on the logic verification means (logic simulator) to be used, and the logic verification means is used without making the signals in the simulation target logic operable from the external control program. it can.

[0009]

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a logic simulation apparatus according to the present invention. In the figure, a logic simulator (first logic verification means) 3 is, for example, a gate level logic simulator (HAL), an instruction interpreter (second logic verification means) 4 is an instruction level simulator (TD), and these are alternately used. Then, the test program 2 is executed. The test program (test instruction sequence) 2 is generally composed of pre-processing instructions, test instructions and post-processing instructions. The pre-processing instructions and post-processing instructions are executed by the instruction interpreter 5, and test instructions (four arithmetic operation instructions, etc.) are executed. Only the part is executed by the logic simulator 4. The simulation command 1 instructs the operation to the logic simulator 3, and the logic simulator 3 executes the simulation of the simulation target logic (logic device under test) 5 according to the simulation command 1. In the simulation target logic 5, an interface logic block 51 is provided between the logic simulator 3 and the instruction interpreter 4 to bridge the information necessary for instruction execution, that is, the transfer information 6. In this embodiment, the interface logic block 51 extracts the desired signal value of the memory / register 52 in the simulation target logic 5, edits the transfer information 6 and passes it to the instruction interpreter 4, and also transfers from the instruction interpreter 4. 6 is received and a value is set in the memory / register 52.

The logic simulation device is built on a computer system. An area for the transfer information 6 is secured in the main storage device of this computer system, and the contents (instruction string, data) of the test program 2 are set in advance as a part of the transfer information 6 before the simulation is started. The logic simulator 3 executes the instruction as if the test program 2 were in the memory of the logic 5 to be simulated. The simulation command 1 is also prepared in advance in a predetermined area of the main storage device.

FIG. 2 is a description example of the simulation command 1, which shows the operation flow of the logic simulator 3. FIG. 3 shows the interface logic block 5
2 is an operation flow of No. 1. An outline of the operation of the embodiment shown in FIG. 1 will be described below with reference to FIGS.

At the start of the simulation, the logic simulator 3 first resets the simulation target logic 5 according to the simulation command 1 (step 210) and then executes the simulation of the interface logic block 51 (step 220).

When the logic 5 to be simulated is reset, the interface logic block 51 executes steps 301 to 303 in FIG. First, the instruction interpreter 4 is called (step 301). The instruction interpreter 4 takes in the transfer information 6 and executes the preprocessing instruction part in the test program 2. After the execution, the transfer information 6 is updated and the interface logic block 51 is returned. The interface logic block 51 reads the transfer information 6 (step 302) and sets a signal value in the memory / register 52 in the simulation target logic 5 (step 303).

Next, the logic simulator 3 executes the test instruction part in the test program 2 (step 23).
0). After executing the test instruction, the logic simulator 3 executes the simulation of the interface logic block 51 again according to the simulation command 1 (step 240).

At this time, the interface logic block 51
Then, steps 311 to 313 of FIG. 3 are executed. First, the contents of the memory / register 52 in the simulation target logic 5 are extracted (step 311) and edited and output as the transfer information 6 (step 312). Next, the instruction interpreter 4 is called (step 313). The instruction interpreter 4 takes in the transfer information 6 and executes the post-processing instruction portion in the test program 2.

The above is the outline of the operation of the embodiment shown in FIG.
The flow of the logic simulation control of a specific test program will be described in more detail below.

Here, for simplification of description, it is assumed that the test program 2 is a very simple example in which the data 1 and the data 2 are added and the addition result is compared with the expected value of the data 3. The instruction sequence of this test program is as shown in FIG. In FIG. 4, steps 401 and 40
2 is a preprocessing command part, step 404 is a test command part (here, an addition command), and steps 406, 407, 40.
8 is a post-processing instruction part. Steps 403 and 405 are NOT OPERATION (NOP).
When the OP instruction is detected, the operations of the logic simulator 3 and the instruction interpreter 4 are switched.

FIG. 5 shows the transition of the transfer information in the execution process of the test program of FIG. Hereinafter, description will be given with reference to FIG.

At the start of the simulation, the logic simulator 3 resets the simulator target logic 5 (step 210) and executes the simulation of the interface logic block 51 (step 220). By the operation of this interface logic block 51, control is transferred to the instruction interpreter 4 (step 301). At this time, the transfer information 6 is as shown in the state (a) of FIG. This is the initial state. The life-and-death interpreter 4 executes the test program of FIG. 4 from the head to steps 401 and 402 by the instruction pointer of the transfer information, and subsequently when the NOP instruction is detected in the step 403, the interface logic block 51 is returned. As a result of execution of instructions by this instruction interpreter 4, the transfer information 6
It becomes like the state (b) of. The interface logic block 51 reads the transfer information 6 (step 30
2) Set the value in the memory / register 52 in the simulation target logic 5 (step 303). That is,
Data 1 is set in the register 1, data 2 is set in the register 2, and the instruction address of step 404 is set in the instruction pointer.

The logic simulator 3 executes the addition instruction of step 404 of the test program of FIG. 4 by the instruction pointer of the memory / register 52 (step 23).
0), subsequently, when the NOP instruction is detected in step 405, the simulator of the interface logic block 51 is executed again (step 240). The interface logic block 51 extracts the contents of register 1 and the instruction pointer in the memory / register 52 (step 311),
The transfer information 6 is edited (step 312), and the instruction interpreter 4 is activated (step 313). The transfer information 6 at this time is as shown in the state (C) of FIG.
The instruction interpreter 4 uses the instruction pointer of the transfer information to execute the test program of FIG.
7,408. That is, in step 406, the value of the register 1 (addition result) in the transfer information 6 and the expected value of the data 3 are compared.
In step 7, a normal end message is output, and if they do not match, step 408 outputs a bad message.

Although the test program of FIG. 4 is a very simple example, it goes without saying that the actual test program is generally more complicated than this. In the embodiment of FIG. 1, the gate level logic simulator 3 is shown as the first logic verification means and the instruction level (statement level) instruction interpreter 4 is shown as the second logic verification means. There is no need to limit.

[0023]

According to the present invention, a general logic verifying means is added by adding an interface logic block having a function of extracting and substituting a signal required for transfer of the logic verifying means (simulator) to the simulation target logic. Can be used as it is, and an efficient simulation can be performed by a plurality of logic verification means. Therefore, for example, it is possible to carry out a logic simulation, which is carried out by a conventional TDHAL system, by combining a commercially available gate level simulator and a functional level simulator. In this case, if the test instruction portion of the simulation target program is 5%, the logic simulation can be performed in about 5% of the processing time as compared with the case of using the gate level simulator alone.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a logic simulation apparatus of the present invention.

FIG. 2 is an example of an operation instruction command for a logic simulator.

FIG. 3 is an example of an operation flow of an interface logic block.

FIG. 4 is a specific example of a test program.

FIG. 5 is a diagram showing transition of transfer information when the test program of FIG. 4 is executed.

FIG. 6 is a diagram showing a configuration example of a conventional TDHAL system.

FIG. 7 is a diagram showing an example of a connection between a conventional device simulation program and a virtual computer.

[Explanation of symbols]

 1 Simulation Command 2 Test Program 3 Logic Simulator 4 Instruction Interpreter 5 Simulation Target Logic 51 Interface Logic Block 52 Memory / Register Group 6 Transfer Information

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Norihiko Onizuka 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Co., Ltd. (72) Inventor Yoshiaki Kinoshita 1 Horiyamashita, Hadano, Kanagawa Pref. Factory General Computer Division

Claims (2)

[Claims] 1. A first logic verifying means and a second logic verifying means having a function different from that of the first logic verifying means are provided, and the first and second logic verifying means operate alternately. Then, in the logic simulation device for pseudo-verifying the logic device under test, in the simulation target logic of the logic device under test,
An interface logic block is provided for mutually transmitting information necessary for transfer between the first logic verification means and the second logic verification means (hereinafter referred to as transfer information). Logic simulation device. 2. The logic simulation apparatus according to claim 1, wherein the first logic verification means is composed of a logic simulator for pseudo-verifying the logic device under test at a gate level,
The second logic verification means is composed of an instruction interpreter that performs pseudo verification at the instruction level, and the interface logic block extracts transition information from the simulation target logic of the logic device under test, edits it, and edits it to the instruction interpreter. A logic simulation apparatus, which outputs the information, reads the transfer information from the instruction interpreter, and sets it in the simulation target logic.