JPH0817999A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce deterioration of the operating efficiency of parallel operation elements, which is caused by an electrical phase difference between input or output signals in the parallel operation of an arbitrary number of the semiconductor elements. CONSTITUTION:A semiconductor device has a first metal member 2 mounted with a semiconductor chip 1 and a second metal member 3 or 4, which is connected with input or output electrodes of the chip 1 by bonding using metal wires or the like, recessed and projected parts 19, 19' and 20 and 20' are provided in and on arbitrary places on the second metal members, an electrical phase difference between electrical signals, which are inputted in a plurality of the input electrodes, or an electrical phase difference between electrical signals, which are outputted from a plurality of the output electrodes, is reduced and the operating efficiency of parallel operation elements is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an array operation type semiconductor device in which a plurality of semiconductor elements are arranged in parallel.

[0002]

2. Description of the Related Art In a semiconductor device in which a plurality of semiconductor elements are arranged in parallel and operated in parallel, the electrical phases of input and output signals of the semiconductor elements arranged in parallel are aligned in order to enhance the operation efficiency of the device. Has been a problem than before. For example, when operating two transistors in parallel and making an amplifier that obtains twice the electric power that one transistor can output, if the signals input to the two transistors have a phase difference of ψ, the signal will be sin Assuming a wave, the composite wave A of the two signals is A = sin θ + sin (θ−ψ)
Becomes On the other hand, the composite wave B in the ideal case with no phase difference
Since B = 2 sin θ, when the power ratio of the composite waves A and B is considered as the operation efficiency, it is [Equation 1].

[Equation 1]

Here, in order to simplify the equation of [Equation 1], the inside of the parentheses is calculated as [Equation 2] with the integration range of 0 → π.

[Equation 2] For example, if there is a phase difference of ψ = 30 °, only 87% of the output that can be originally output operates.

As a conventional technique for reducing the electrical phase difference of this parallel operation type semiconductor device, semiconductor devices such as JP-A-63-141328 and JP-A-63-224247 have been proposed. FIG. 7 shows the structure of the semiconductor device disclosed in Japanese Patent Laid-Open No. 63-141328.
e) (here, bipolar transistors) are arrayed and mounted in an arch shape, and MO is applied from the input lead (33) to the input electrodes (base) (42a) to (42e) of the semiconductor chip.
Metal wires (38a) to (38e) and (39a) to which are bonded via the S capacitor (32).
The wire length of (39e) is the same for each semiconductor chip (30
A) to (30e) are made equal to reduce the phase difference of the input signals. In addition, (34) is an output terminal,
(35) is an insulating layer, (36) is a ground electrode (metal layer),
(40a) to (40e) and (41a) to (41d) are metal wires.

FIGS. 8 (a) and 8 (b) are obtained by applying the semiconductor device of FIG. 7 to a mold type semiconductor device, in which semiconductor chips (30a) to (30e) are arched on a first metal member (2). Mounted in a rectangular shape, and input electrodes (42a) to (42e)
And the second metal member (3) to the metal wire (45a) to
(45e) is connected by bonding, and the ground electrodes (emitters) (43) of the semiconductor chips (30a) to (30e) are connected.
a) to (43e) is another second metal member (47)
Are bonded with metal wires (46a) to (46e). The semiconductor resin, the metal wire, and the first and second metal members are fixed by the mold resin (9) filled in the mold area (8). Note that (13) is an input terminal and (14) is an output terminal. In addition, FIG.
It is an electrode explanatory view of chips (30a)-(30e).

FIG. 9 shows the structure of the semiconductor device disclosed in JP-A-63-224247, in which semiconductor chips (30a) to (30) are mounted on a mount area (31) formed on a peripheral device (37).
d) is mounted and the input electrodes (42a) to (42d) are mounted.
And the input lead (33), the MOS capacitors (32 ') (32 ") are mounted, and the bonding wires (44) (38a) to
(38b) (39a) to (39d) are bonded in a tournament shape so that the bonding wire lengths from the input lead (33) to the input electrodes (42a) to (42d) of the semiconductor chip are equal, and the input signal is The phase difference of is reduced. Note that (34) in FIG. 9 is an output terminal and (3
5) is an insulating layer, (36) is a ground electrode, and (37) is a peripheral device.

FIG. 10 is an application of the semiconductor device of FIG. 9 to a mold type semiconductor device in which a part of the tournament wiring is replaced with a second metal member (3). First
On the metal member (2) of the semiconductor chips (30a) to (3)
0d) is mounted and the input electrode (42
a) to (42d) and the second metal member (3) are connected by metal wires (45a) to (45d). From the input lead (13) to the input terminals (42a) to (42d), the second metal member (3) is connected to the metal wires (45a) to (42a).
By (45d), it is wired like a tournament,
The ground electrodes (43a) to (43d) are bonded to the other second metal member (47) with metal wires (46a) to (46d). The semiconductor resin, the metal wire, and the first and second metal members are fixed by the mold resin (9) filled in the mold area (8).

[0008]

As described above, in the conventional parallel operation type semiconductor device, the phase difference between the input signals is reduced by devising the mounting position of the semiconductor chip and the wire bonding structure. However, JP-A-63-141
In the semiconductor device 328, the width of the mounting area (M in FIG. 7 and FIG. 8) for mounting the semiconductor chip in an arch shape.
It is necessary to make the M'section) wider than in the case where the semiconductor chip is linearly mounted, which is inconvenient for downsizing of the device. This becomes remarkable as the number of semiconductor chips arranged in parallel increases.

Further, the semiconductor chip of Japanese Patent Laid-Open No. 63-141328 is mounted in an arch shape so as to correct the difference in the bonding wire length (the bonding wire becomes longer from the center to the outside) when linearly mounted. However, when it is necessary to wire not only the input side but also the output side by a bonding wire similar to the input like the FET, in the arch configuration in which the phases are matched on the input side, the output side is outside the center part. Since the bonding wire becomes longer, the phase cannot be corrected. Therefore, Japanese Patent Laid-Open No. 63-141328 cannot be applied to the case where a phase correction for simultaneous input and output is required, such as an FET.

Further, in Japanese Patent Laid-Open No. 63-224247, the width of the tournament area (N in FIG. 9 and N'in FIG. 10) is required in order to configure the wiring from the input lead to the semiconductor chip in a tournament shape. However, if the number of semiconductor chips arranged in parallel increases, it becomes necessary to secure a large tournament area, which causes inconvenience in downsizing of the device. Further, in the configuration of this Japanese Patent Laid-Open No. 63-224247, the signal phase from the external input terminal to the semiconductor chip is aligned by bonding the bonding wire to the tournament by using the moss capacitor as an intermediary. 2 parallels, 4 parallels, 87 parallels. ． ．
These are 2 ⁿ parallel elements and cannot be applied to parallel operation of an odd number of elements. For example, in the case of three parallel elements, the total phase length from the external input terminal to the element arranged in the middle to the semiconductor chip input terminal becomes shorter than the other two elements (elements arranged on both sides), The phases are not aligned.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor chip having a plurality of high frequency signal input or output terminals, a first metal member on which the semiconductor chip is mounted, and bonding of a metal wire or the like to the semiconductor chip. And a second metal member electrically connecting the semiconductor chip to the outer peripheral circuit is fixed by a molding resin, the plurality of high frequency signal input terminals of the semiconductor chip are connected to the outer peripheral circuit from the outer peripheral circuit. Any of the second metal members may be used so that the electric phases of the high-frequency signals that are input are aligned with each other, or that the high-frequency signals that are output from the plurality of high-frequency signal output terminals of the semiconductor chip to the external circuit are aligned with each other. The semiconductor device is characterized in that a concave-convex portion is provided at the location.

In addition, instead of the semiconductor chip having a plurality of high frequency signal input or output terminals in the above semiconductor device, a plurality of semiconductor chips having one high frequency signal input or output terminal are mounted. Further, in the semiconductor device of the present invention, the second metal member is
A single input terminal is branched to form a plurality of input terminal groups, each of which is connected to a plurality of semiconductor chips by bonding, and the single input is selected from the plurality of branched input terminal groups. It is characterized in that an uneven portion is provided on the input terminal group close to the terminals. Further, in the semiconductor device of the present invention, the second metal member is formed by integrating a plurality of output terminal groups into a single output terminal, and the plurality of semiconductor chips and the plurality of output terminals are connected by bonding. Has been done,
Among the plurality of output terminal groups, an uneven portion is provided on an input terminal group close to the single output terminal. Further, the semiconductor device of the present invention is characterized in that the uneven portion provided on the second metal member adjusts the phase difference between the plurality of terminal groups by changing the height thereof.

[0013]

According to the present invention, in contrast to the conventional parallel operation type semiconductor device, the semiconductor device of the present invention includes the first metal member for mounting the semiconductor chip, the input or output electrode of the semiconductor chip, and the metal wire. Second electrically connected
Since the second metal member is provided with the unevenness at any position, the difference in electrical phase due to the positional relationship between the second metal member and the plurality of input or output electrodes of the semiconductor chip is partly affected. It is possible to reduce the phase difference of the electric signal input to the semiconductor chip or output from the semiconductor chip by correcting the unevenness of the second metal member provided at an arbitrary position.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. [Embodiment 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 (a) is a sectional view taken along the line AA 'in FIG.
FIG. 2B is a sectional view showing electrodes of the semiconductor chip shown in FIG. The semiconductor chip (1) (here, FET) is mounted on the first metal member (2) by using AuSn brazing material or the like, and the semiconductor chip (1) is as shown in detail in FIG. 2 (b). Four input electrodes (10a) to (10d)
(Gate electrode) and four output electrodes (11a) to (11
d) (drain electrode) and eight ground electrodes (12a) to
(12h) (source electrode) is formed. The input electrodes (10a) to (10d) are bonded to the second metal member (3) by metal wires (5a) to (5d) such as gold wires. Also, the output electrodes (11a) to (11
d) is bonded to another second metal member (4) by metal wires (6a) to (6d). The ground electrodes (12a) to (12h) are connected to the first metal member (2) by bonding with metal wires (7a) to (7h).

The second metal member (3) has an uneven portion (1
9) (19 ') is formed. Further, the second metal member (4) is provided with uneven portions (20) and (20 '). The uneven portion is shown in FIG. 2A which is a sectional view taken along the line AA ′ of FIG. That is, the second metal member (3)
Is connected to the input terminal (13), the second metal member (4) is connected to the output terminal (14), and the first metal member (2) is connected to the ground terminals (15) and (15 '). There is. Then, the second metal member (3) is branched from the single input terminal (13) to form a plurality of input terminal groups, which are respectively connected to the plurality of semiconductor chips (1) by bonding. The concave-convex portion (19) (1) is formed in the input terminal group close to the single input terminal (13) among the plurality of input terminal groups
9 ') are provided. Also, the second metal member (4)
Is a single output terminal (1
4), a plurality of semiconductor chips (1) and a plurality of output terminals are connected by bonding, respectively, and an uneven portion (20) is formed in the input terminal group near the single output terminal (14) among the plurality of output terminal groups. ) (20 ') is provided.

The semiconductor chip (1), the first metal member (2), the second metal members (3) and (4), and the metal wires (5a) to (5d) and (6a) to (6d). ), (7
a) to (7h) are fixed by the mold resin (9) filled in the mold area (8). The semiconductor chip (1) has been described as having a plurality of high frequency signal input or output terminals, but the same applies to a case where a plurality of semiconductor chips having one high frequency signal input or output terminal are mounted instead. It is what constitutes.

The manufacture of this semiconductor device will be described with reference to FIGS. When manufacturing this semiconductor device,
First, a lead frame configuration of the metal member and the second metal member is manufactured. 3 and 4 show an example of the lead frame. The lead frame is formed by first pressing a plate material such as copper into a pattern as shown in FIG.
After that, the second press working is used to form a concavo-convex portion at an arbitrary position as shown in FIG. 4, and surface treatment such as silver plating is performed to complete the process. That is, as shown in FIG. 3, a plate material such as copper having a perforation hole (63) is subjected to a first press working to produce a lead frame (6
0) is formed. The lead frame (60) has a lead frame outer frame (61) and a lead frame inner frame (62), and the lead frame outer frame (61) includes the first metal member (2) and the lead frame. The second in the inner frame (62)
The metal members (3) and (4) are pressed into a pattern.

Next, as shown in FIG. 4, the lead frame is subjected to the second press working, and the second metal member (3)
Concavo-convex parts (19) (19 ') on the two central parts of the book
And the concave and convex portions (20) and (20 ') are formed on two of the four central portions of the second metal member (4). Then, this is subjected to surface treatment such as silver plating. As described with reference to FIGS. 1 and 2, a semiconductor chip is mounted on the lead frame thus formed and bonding wiring is performed with metal wires, and then the mold is put into a mold and a mold resin is injected into the mold to cure. Process and harden the molding resin. After that, after processing such as solder plating, the leads are cut, and the leads are molded to complete the process.

[Embodiment 2] FIGS. 5 and 6 show a second embodiment of the present invention. The configuration is the same as that of the first embodiment.
That is, the semiconductor chip (1) is mounted on the first metal member (2), and the semiconductor chip (1) has five input electrodes (gate electrodes), five output electrodes (drain electrodes), Ten ground electrodes (source electrodes) are formed, and the input electrodes are bonded to the second metal member (3) by metal wires (5a) to (5e).
Further, the output electrode is bonded to another second metal member (4) by metal wires (6a) to (6e). In addition, the ground electrodes are metal wires (7a) to (7
At j), it is bonded to the first metal member (2).

As described above, in the present embodiment, the semiconductor chip of 5 cells is used, and in order to match the phases with the two outermost elements (elements at both ends) as a reference, a larger phase correction is performed toward the center. Therefore, in forming the unevenness of the second metal member, the height of the convex portion of the central lead (19 ") is formed higher than that of the leads (19) and (19 ') on both sides thereof. Similarly, on the output side, the convex part of (20 ") is (2
0) and (20 ').

Regarding this, FIG. 6A shows a line A- in FIG.
A'section is shown, showing the irregularities (19 ') and (20')
However, FIG. 6 (b) shows a cross section taken along the line BB 'of FIG. 5, showing the uneven portions (19 ") and (20"). As is apparent from FIGS. 6A and 6B, the central lead (1
9 ") and (20") are formed higher than the leads on both sides thereof. Further, in the present embodiment, the second metal member is processed into a convex shape to perform the phase correction, but it goes without saying that the same effect can be obtained even if the second metal member is processed into a concave shape. . That is, the uneven portions provided on the second metal members (3) and (4) can adjust the phase difference between the plurality of terminal groups by changing the height thereof. Those formed in this way are the semiconductor chip (1), the first metal member (2), the second metal members (3) and (4), and the metal wires (5a) to (5).
e), (6a) to (6e), and (7a) to (7j) are fixed by the mold resin (9) filled in the mold area (8).

[0022]

As described above, according to the semiconductor device of the present invention, the frame portion (second metal member) connecting the semiconductor chip and the outer peripheral circuit is provided with irregularities so that the input or output terminals of the device are connected to each other. It is input to the semiconductor chip by keeping the distance to the input or output electrode of the semiconductor element constant. Alternatively, the effect of reducing the phase difference of the electric signal output from the semiconductor chip and improving the operation efficiency in the parallel operation type element is achieved. further,
It is possible to minimize the increase in the container area of the semiconductor device due to the increase in the number of chips (or cells), which is a drawback of the conventional technology. Moreover, it is possible to reduce the phase difference at the time of input and output simultaneously. It is also possible to mount an odd number (or odd number of cells) of semiconductor chips. That is the effect.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

2A is a sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is an explanatory view of a chip electrode.

FIG. 3 is a view of the lead frame according to the first embodiment of the present invention (after the first press working).

FIG. 4 is a view of the lead frame according to the first embodiment of the present invention (after the second press working).

FIG. 5 is a plan view of the second embodiment of the present invention.

6A is a sectional view taken along the line AA ′ in FIG. 5, and FIG.
BB 'sectional drawing.

FIG. 7 is a diagram illustrating a conventional technique.

FIG. 8 is a diagram illustrating a conventional technique (application example of a mold of FIG. 7).

FIG. 9 is a diagram illustrating a conventional technique.

FIG. 10 is a diagram illustrating a conventional technique (application example of a mold of FIG. 9).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor chip (FET) 2 1st metal member 3,4 2nd metal member 5a-5e, 6a-6e, 7a-7i Metal wire 8 Mold area 9 Mold resin 10a-10d Input electrode (gate) 11a-11d. Output electrode (drain) 12a to 12h Ground electrode (source) 13 Input terminal 14 Output terminal 15, 15 'Ground terminal 19, 19', 19 ", 20, 20 ', 20" Uneven portion 30a to 30e Semiconductor chip (bipolar transistor) ) 31 mount area (metal layer) 32, 32 ', 32 "moss capacitor 33 input terminal 34 output terminal 35 insulating layer 36 ground electrode (metal layer) 37 peripheral device 38a-38e, 39a-39e, 40a-40e, 4
1a to 41d Metal wire 42a to 42e Input electrode (base) 43a to 43e Ground electrode (emitter) 44, 45a to 45e, 46a to 46e Metal wire 47 Second metal member 60 Lead frame 61 Lead frame outer frame 62 In lead frame Frame 63 Feed hole

Claims (5)

[Claims] 1. A semiconductor chip having a plurality of high-frequency signal input or output terminals, a first metal member on which the semiconductor chip is mounted, and a semiconductor chip connected to the semiconductor chip by bonding such as a metal wire. In a semiconductor device in which a second metal member electrically connected to an outer peripheral circuit is fixed by a molding resin, an electrical phase of a high frequency signal input from the outer peripheral circuit to a plurality of high frequency signal input terminals of the semiconductor chip. So that the high-frequency signals output from the plurality of high-frequency signal output terminals of the semiconductor chip to the external circuit have the same electrical phase so that the second metal member is provided with an uneven portion at an arbitrary position. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein instead of the semiconductor chip having a plurality of high frequency signal input or output terminals, a plurality of semiconductor chips having one high frequency signal input or output terminal are mounted. A semiconductor device characterized by: 3. A second metal member, wherein a single input terminal is branched to form a plurality of input terminal groups, each of which is connected to a plurality of semiconductor chips by bonding, and the plurality of branched terminals are connected. 3. The semiconductor device according to claim 1, wherein an uneven portion is provided in an input terminal group close to the single input terminal in the input terminal group. 4. A second metal member, wherein a plurality of output terminal groups are integrated to form a single output terminal, and a plurality of semiconductor chips and a plurality of output terminals are connected by bonding, respectively. The semiconductor device according to claim 1, wherein an uneven portion is provided in an input terminal group near the single output terminal among the plurality of output terminal groups. 5. The uneven portion provided on the second metal member,
The semiconductor device according to claim 1, wherein the phase difference between the plurality of terminal groups is adjusted by changing the height.