JPH0817908A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To form a high breakdown voltage element in a dielectric isolation island, by connecting a polycrystalline silicon film with a GND electrode, on the substrate surface in the dielectric isolation region. CONSTITUTION:Many dielectric isolation islands 1 are formed on a retaining substrate 1 by using a polycrystalline silicon film 24 and an oxide film 12 retained by a borosilicate glass film 11. The polycrystalline silicon film 14 is doped with P-type impurities. PN junction diffusion isolation regions 16, 18 in the dielectric isolation island are connected with the same conductivity type polycrystalline silicon film 24 via an aperture 13 of the oxide film 12, and connected with a GND electrode 25 on the substrate surface in the dielectric isolation region. Hence the GND potential is supplied to the PN junction diffusion isolation regions 16, 18 through the polycrystalline silicon film 24 which is a part of a retaining part member retaining the dielectric isolation island 1, so that the conventional electrode wiring on the island and the connection with the wiring are made unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit including a high breakdown voltage semiconductor element in a dielectrically isolated island and a manufacturing method thereof.

[0002]

2. Description of the Related Art When manufacturing a semiconductor integrated circuit including a semiconductor element having a withstand voltage of several hundreds of volts or more, a dielectric material that does not use a PN junction to separate elements but an oxide film (dielectric material). A separate structure is used. There are several types of manufacturing methods, one of which is
A method is known in which after a groove is formed on the surface of a semiconductor substrate, the groove is filled with polycrystalline silicon and adhered to a supporting substrate, and the opposite surface is polished to use the polished surface as an element formation surface (for example, , JP-A-59-99735).

According to Japanese Patent Laid-Open No. 1-93143, unevenness (grooves) is formed on the main surfaces of the first semiconductor substrate and the second semiconductor substrate, and they are mutually bonded via a fluid adhesive material. After fitting the uneven surfaces of the two, the adhesive material is heated and hardened to bond the two semiconductor substrates, and the back surface of one of the semiconductor substrates is polished to form islands separated by the adhesive and the insulating layer. A method of doing so is disclosed. Here, as the adhesive material having fluidity, B
A glass material such as PSG is used.

[0004]

However, various LSs including transistors and the like whose breakdown voltage exceeds several hundreds of volts.
When manufacturing I, all the transistors mounted on this LSI do not necessarily require a withstand voltage of several hundreds of volts. In general, a large number of transistors of such an LSI are small signal transistors, and a withstand voltage of several tens of V is sufficient. In the case of manufacturing such an LSI, if the small signal transistors are arranged one by one on the above-described islands separated from the dielectric, the chip area of the semiconductor integrated circuit increases, which leads to an increase in production cost.

The present invention has been made in view of the above problems of the prior art. A high breakdown voltage element is housed in an island separated by a dielectric, and a plurality of elements that do not require a breakdown voltage are grouped together to form a PN junction. It is an object of the present invention to provide a high breakdown voltage semiconductor integrated circuit having a compact structure which can be housed in a separated island and can particularly simplify the GND wiring, and a manufacturing method thereof.

[0006]

In a semiconductor integrated circuit of the present invention, an island made of a single crystal semiconductor, an insulating film covering the lower surface and side surfaces of the island, and an island covered with the insulating film are embedded and supported. In a dielectric isolation type semiconductor integrated circuit comprising a supporting member and a supporting substrate to which the supporting member is fixed, the supporting member includes a polycrystalline silicon film fixed to an insulating film covering the island, and the polycrystalline silicon film. And a boron glass film adhered to the supporting substrate, the polycrystalline silicon film is doped with the same conductivity type as the PN junction isolation diffusion region in the island, and the PN via the opening of the insulating film on the lower surface of the island. It is connected to a junction isolation diffusion region, and the polycrystalline silicon film is connected to a GND electrode on the substrate surface of the dielectric isolation region. .

A method of manufacturing a semiconductor integrated circuit according to the present invention comprises a step of forming a separating groove on a semiconductor substrate to form an insulating film on the surface of the semiconductor substrate, and forming an opening in a part of the insulating film. A step of depositing a polycrystalline silicon film and a boron glass film by embedding the separation groove on the semiconductor substrate, and a step of attaching the adhered surface of the boron glass film to a support substrate; A step of polishing from the back surface of the semiconductor substrate until reaching the separation groove to form an island dielectrically separated by the insulating film; a step of forming a PN junction separation diffusion region in the island; Connecting the PN junction isolation diffusion region in the dielectrically isolated island and the polycrystalline silicon film through an opening;
And a wiring connection to a GND electrode on the surface of the substrate in the dielectric isolation region.

[0008]

[Function] In the island separated by the dielectric, PN is further added.
Since the islands separated by the junction are provided, the semiconductor element having a high withstand voltage is placed in the island separated by the dielectric, and the semiconductor element such as a small signal transistor which does not require the withstand voltage is formed by the P element.
It can be housed in an island separated by N junctions. The PN junction diffusion isolation region is connected to the polycrystalline silicon film through the insulating film opening, and is connected to the GND electrode on the substrate surface of the dielectric isolation region.
The GND potential is supplied to the N-junction isolation region from the GND electrode on the dielectric isolation region. Therefore, a plurality of small-signal semiconductor elements can be housed in the island separated by the dielectric, and it is not necessary to connect the GND electrode to the PN junction separation region in the island, and the GND electrode can be drawn on the island. No need to wire. Therefore, since the wiring area can be reduced, the chip size of the integrated circuit can be reduced and the production cost can be reduced.

Further, according to the manufacturing method of the present invention, it is possible to easily manufacture a semiconductor integrated circuit having the above-described structure and having a reduced chip size.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a partial cross-sectional view of an integrated circuit according to an embodiment of the present invention, where (A) shows a region of a dielectric-isolated island and (B) shows a dielectric-isolated island. One of the islands further separated by PN junction is shown. The semiconductor integrated circuit according to the present embodiment has an island 1 which is supported by a polycrystalline silicon film 24 and a boron glass film 11 on a supporting substrate 10 and is dielectrically separated by an oxide film 12.
Are formed in large numbers. Some of the islands 1 are provided with islands 2 which are PN junction separated by diffusion regions 16 and 18. The dielectrically separated N-type island 1 is PN-junction separated by a P-type diffusion region 16 from below and a P-type diffusion region 18 from above. Then, although not shown, a high breakdown voltage transistor having a breakdown voltage of, for example, several hundreds V, a DMO, is formed on the dielectric-isolated island 1.
Elements such as S and IGBT are stored. The island 2 separated by the PN junction has a small signal NPN that does not require breakdown voltage.
Type transistors and the like are stored.

That is, the island 1 dielectric-separated by the oxide film 12 is divided by the V-shaped groove 3, and the V-shaped groove 3 has a polycrystalline silicon film 24 at the tip thereof, so that the supporting substrate 10 is formed. The side is filled with a boron glass film 11. The polycrystalline silicon film 24 is doped with P-type impurities, and is doped with N through the opening 13 of the oxide film 12.
It is connected to P type diffusion regions 16 and 18 which are PN junction isolation regions in the type island 1. Further, the polycrystalline silicon film 24 has a GND surface on the substrate surface in the dielectric isolation region.
It is connected to the electrode 25. The boron glass film 11 plays a role of adhering the island 1 whose dielectric is separated to the supporting substrate 10 which is another semiconductor substrate.

The P-type diffusion region 16 from below forming the PN junction isolation is formed by diffusing the boron atoms of the polycrystalline silicon film 24 from the opening 13 of the oxide film 3 into the island 1. As shown in FIG. 1B, in the island 2 separated by the PN junction, a P-type base region 20, an N ⁺ -type emitter region 21, which form a small signal transistor,
N ⁺ type deep diffusion region 19, N ⁺ type buried diffusion layer 17
And so on.

The PN junction diffusion isolation regions 16 and 18 in the dielectric isolation island 1 are connected to the polycrystalline silicon film 24 of the same conductivity type through the opening 13 of the oxide film 12, and on the substrate surface of the dielectric isolation region. It is connected to the GND electrode 25. Therefore, the GND potential is supplied to the PN junction diffusion isolation regions 16 and 18 through the polycrystalline silicon film 24 which is a part of the support member supporting the dielectric isolation island 1. Conventionally, the GND potential of the PN junction isolation island 2 is set to G on the island by providing an opening in the oxide film on the substrate surface.
It is supplied from the ND electrode wiring. In this embodiment, the GND is provided through a part of the supporting member of the dielectric isolation island 1.
Since the potential is supplied, the conventional electrode wiring on the island 1 and the connection with the wiring are not required.

It should be noted that it is not always necessary to supply the GND potential depending on the element accommodated in the dielectric isolation island. For example, in the case of a high breakdown voltage transistor in the output stage, it may be necessary to float the emitter terminal from the GND potential. In such a case, if the opening 13 of the oxide film 12 is not provided in advance, the oxide film 12 allows the dielectric island 1 to be formed.
Can be insulated from the polycrystalline silicon film 24. In this way, whether to supply the GND potential can be set depending on whether or not the opening 13 of the oxide film 12 is provided.

Next, a method of manufacturing the semiconductor integrated circuit of this embodiment will be described. First, as shown in FIG. 2, the surface of the N-type semiconductor substrate 15 is selectively subjected to anisotropic dry etching by resist patterning to form a V-shaped or U-shaped groove 3 having a depth of 50 to 150 μm. The V-shaped or U-shaped groove 3 may be formed by anisotropic etching using a KOH solution.

Next, as shown in FIG. 3, arsenic is diffused over the entire surface of the semiconductor substrate 15 to form an N ⁺ -type diffusion layer 17 serving as a buried diffusion layer. Then, an oxide film 12 is formed on the entire surface of the semiconductor substrate 15 by thermal oxidation, and an opening 13 is formed by resist patterning as shown in FIG. After the V-shaped groove 3 is formed, first, the oxide film 12 is thermally grown on the entire surface, and then arsenic is ion-implanted to form the buried diffusion layer 17, and then the opening 13 is formed in the oxide film 3. May be.

Next, as shown in FIG. 5, a polycrystalline silicon film 24 is deposited on the surface of the semiconductor substrate 15 by CVD,
Next, the boron glass film 11 is deposited. Boron glass film 1
In No. 1, a silicate glass film containing boron called soot is formed by reacting silicon tetrachloride with boron trichloride or the like by CVD. The polycrystalline silicon film 24 has a high growth rate at the tip of the groove 3 and a low growth rate at the flat portion. By utilizing this difference in growth rate, the boron glass film 1
The depth of the groove 1 to be embedded is made shallow.

The boron glass film 11 is grown to such a thickness that the V-shaped groove 3 is filled and the surface is substantially flat. The polycrystalline silicon film 24 is preliminarily doped with P ⁺ type. Further, boron may be diffused and doped from the boron glass film 11 by the subsequent heat treatment.

Next, as shown in FIG. 6, the semiconductor substrate 15 is turned over and its surface is attached to the supporting substrate 10.
That is, the surface of the semiconductor substrate 15 on which the boron glass film 11 is adhered is fitted to the surface of the support substrate 10, and, for example, 1
Heat at 200-1300 ° C. By this heat treatment, the boron glass film 11 is softened and the semiconductor substrate 15 and the supporting substrate 10 are firmly bonded and fixed. A semiconductor substrate of the same type as the semiconductor substrate 15 is used as the support substrate 10. The support substrate 10 is made up of a semiconductor substrate 15 made of a support member composed of a polycrystalline silicon film 24 and a boron glass film 11.
Since it is for supporting the substrate, it is preferable to use the same type as the semiconductor substrate 15 from the viewpoint of the coefficient of thermal expansion and the like, but a ceramic substrate or the like may be used.

Next, as shown in FIG. 7, polishing is performed from the back surface side of the semiconductor substrate 15 and stopped when the head of the V-shaped groove 3 is exposed. The polishing of the semiconductor substrate 15 is performed by ordinary polishing. By this polishing, the semiconductor substrate 15 is divided into islands 1 which are dielectrically separated by the oxide film 12. In the island 1, boron atoms in the polycrystalline silicon film 24 are diffused from the opening 13 of the oxide film 3 to form a P-type isolation diffusion region 16 from below. The isolation diffusion region 16 and the N ⁺ type buried diffusion layer 17 from below are respectively formed in the island 1 by the growth of the polycrystalline silicon film 24 and the boron glass film 11 and the heat treatment at the time of attaching the semiconductor substrate 15 to the supporting substrate 10. It is formed by diffusing inside. Although the N ⁺ type buried diffusion layer 17 is initially formed on the entire surface of the semiconductor substrate, the concentration of boron atoms diffused from the polycrystalline silicon film 24 into the island 1 through the opening 13 of the oxide film 12 is high. Therefore, in the island 1 near the opening 13 of the oxide film 12, the conductivity type is converted from N ⁺ type to P ⁺ type.

Next, as shown in FIG. 1B, a P ⁺ type diffusion region 18, a deep collector N ⁺ type diffusion region 19, a P ⁺ type base diffusion layer 20, and an N ⁺ type emitter diffusion layer 21 from above are provided. Etc. are formed one after another, an island 2 having a PN junction isolation is formed in the island area 1 having a dielectric isolation, and a device diffusion region such as a small signal transistor is formed in the island 2. And although not shown, PN
On the island 2 which is not junction-separated, a semiconductor element such as a high voltage bipolar transistor is simultaneously formed by diffusion. The high breakdown voltage transistor and the small signal transistor are connected by a known wiring technique, the GND electrode 25 is connected to the polycrystalline silicon film 24 in the dielectric isolation region, and a semiconductor integrated circuit including a high breakdown voltage semiconductor element is formed. Complete.

In the embodiment described above, an example of forming the small signal transistor in the island region separated by the PN junction has been described. However, a diode, a MOS transistor or the like is formed in the island separated by the PN junction. Of course, it may be formed. Further, the boron glass film is not limited to the above-mentioned embodiment, and any film can be used as long as it can fix the dielectrically separated islands on the supporting substrate. As described above, various modifications can be made without departing from the spirit of the present invention.

[0024]

According to the present invention as described above,
An island in which a PN junction is further separated in an island in which a dielectric is separated, and a PN junction separation diffusion region is connected to a GND electrode on the dielectric separation region through a polycrystalline silicon film which is a part of a supporting member. Is. Therefore,
Since the GND potential is supplied to the PN junction isolation diffusion region, it is not necessary to draw the GND electrode wiring on the island and connect the wiring as in the conventional case. Therefore, it is possible to economically produce a semiconductor integrated circuit including a high breakdown voltage semiconductor element with a small chip area.

[Brief description of drawings]

1A and 1B are cross-sectional views of a semiconductor integrated circuit according to an embodiment of the present invention, in which FIG. 1A shows a region of an island with dielectric isolation, and FIG. 1B shows a region of an island with PN junction isolation. Show.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the embodiment of the present invention.

Claims (5)

[Claims] 1. An island made of a single crystal semiconductor, an insulating film covering the lower surface and the side surface of the island, a support member for embedding and supporting the island covered with the insulating film, and a support substrate to which the support member is fixed. In the dielectric isolation type semiconductor integrated circuit consisting of, the supporting member comprises a polycrystalline silicon film fixed to an insulating film covering the island, and a polycrystalline silicon film and a boron glass film fixed to the supporting substrate. The polycrystalline silicon film is doped with the same conductivity type as the PN junction isolation diffusion region in the island, and is connected to the PN junction isolation diffusion region through the opening of the insulating film on the lower surface of the island. A semiconductor integrated circuit, wherein the film is connected to a GND electrode on the substrate surface of the dielectric isolation region. 2. The semiconductor integrated circuit according to claim 1, wherein the polycrystalline silicon film is P-type doped from the boron glass film. 3. The dielectric isolated island is GN.
2. The semiconductor integrated circuit according to claim 1, wherein whether or not it is electrically connected to the D electrode is determined by the presence or absence of an opening in an insulating film that insulates the island. 4. A step of forming an isolation groove on a semiconductor substrate to form an insulating film on the surface of the semiconductor substrate, a step of forming an opening in a part of the insulating film, a polycrystalline silicon film and boron. A step of depositing a glass film by embedding the separation groove on the semiconductor substrate, a step of attaching the adhered surface of the boron glass film to a support substrate, and a separation groove from the back surface of the semiconductor substrate. To form an island dielectric-isolated by the insulating film, a PN junction isolation diffusion region in the island, and the dielectric isolation via an opening in the insulating film. A semiconductor integrated circuit, including a step of connecting a PN junction isolation diffusion region in the island and the polycrystalline silicon film, and a step of wiring connection to a GND electrode on the substrate surface of the dielectric isolation region. Manufacturing method. 5. The method of manufacturing a semiconductor integrated circuit according to claim 4, wherein diffusion is performed from below the PN junction isolation diffusion region in the island through the opening of the insulating film.