JPH07326661A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To accommodate a high withstand voltage element in a dielectrically isolated island, by dielectrically isolating boron in an island, forming a P-type isolation region from below, forming a P-type isolation region also from above, constituting an island of PN junction isolation, and forming a semiconductor element in the island. CONSTITUTION:Boron is diffused in a dielectrically isolated island 1, from a boron glass film 11, through an aperture 13 of an oxide film 12, and a P-type isolation region 16 is formed from below. A P-type isolation region 18 is formed from above, so as to abut against the P-type isolation region 16. An island 2 of PN junction isolation is formed in the dielectrically isolated island 1. A semiconductor element is formed in the island 2 of PN junction isolation. Thereby a high withstand voltage element can be accommodated in the dielectrically isolated island 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a method of manufacturing a semiconductor integrated circuit including a high breakdown voltage semiconductor element in an island separated by a dielectric.

[0002]

2. Description of the Related Art When manufacturing a semiconductor integrated circuit including a semiconductor element having a withstand voltage of several hundreds of volts or more, a dielectric material that does not use a PN junction to separate elements but an oxide film (dielectric material). A separate structure is used. There are several types of manufacturing methods, one of which is
A method is known in which after a groove is formed on the surface of a semiconductor substrate, the groove is filled with polycrystalline silicon and adhered to a supporting substrate, and the opposite surface is polished to use the polished surface as an element formation surface (for example, , JP-A-59-99735).

According to Japanese Patent Laid-Open No. 1-93143, unevenness (grooves) is formed on the main surfaces of the first semiconductor substrate and the second semiconductor substrate, and they are mutually bonded via a fluid adhesive material. After fitting the uneven surfaces of the two, the adhesive material is heated and hardened to bond the two semiconductor substrates, and the back surface of one of the semiconductor substrates is polished to form islands separated by the adhesive and the insulating layer. A method of doing so is disclosed. Here, as the adhesive material having fluidity, B
A glass material such as PSG is used.

[0004]

However, various LSs including transistors and the like whose breakdown voltage exceeds several hundreds of volts.
When manufacturing I, all the transistors mounted on this LSI do not necessarily require a withstand voltage of several hundreds of volts. In general, a large number of transistors of such an LSI are small signal transistors, and a withstand voltage of several tens of V is sufficient. In the case of manufacturing such an LSI, if the small signal transistors are arranged one by one on the above-described islands separated from the dielectric, the chip area of the semiconductor integrated circuit increases, which leads to an increase in production cost.

The present invention has been made in view of the above-mentioned problems of the prior art. A high withstand voltage element is housed in an island separated by a dielectric, and a plurality of elements that do not require a withstand voltage are grouped together. An object of the present invention is to provide a method for manufacturing a high breakdown voltage semiconductor integrated circuit having a compact structure that can be housed in one island separated from the body.

[0006]

A method of manufacturing a semiconductor integrated circuit according to the present invention comprises a step of forming a groove for isolation on an N-type semiconductor substrate, and a thin oxide film and a nitride film on the entire surface of the semiconductor substrate. Forming step, forming an opening in a part of the nitride film, ion-implanting N + -type impurities from the opening using the nitride film as a mask, and thickening the opening in the opening using the nitride film as a mask A step of forming an oxide film, a step of removing the nitride film and the thin oxide film used as the mask, a step of depositing a boron glass film on the semiconductor substrate by embedding the separation groove, and a step of forming the boron film. A step of adhering the adhered surface of the glass film to a support substrate; a step of polishing the back surface of the semiconductor substrate until reaching the separation groove to form islands separated from the dielectric; Through the membrane opening Forming a P-type isolation region boron from below diffuses into the dielectric isolated in an island Te, so as to contact the P-type isolation region from said lower,
Forming a P-type isolation region from above to form an island having a PN junction isolation in the dielectric isolation island; and forming a semiconductor element in the PN junction isolation island. Is characterized by.

[0007]

[Function] In the island separated by the dielectric, PN is further added.
Since the islands separated by the junction are provided, the semiconductor element having a high withstand voltage is placed in the island separated by the dielectric, and the semiconductor element such as a small signal transistor which does not require the withstand voltage is formed by the P element.
It can be housed in an island separated by N junctions. Therefore, a plurality of small-signal semiconductor elements can be accommodated in one dielectrically separated island, which makes it possible to reduce the chip size of the integrated circuit including the high breakdown voltage element and reduce the production cost. .

Further, the lower isolation region for PN junction isolation is formed by diffusing boron from the boron glass film through the opening of the oxide film in the island which is dielectrically isolated by the boron glass film. Since N + type impurities are ion-implanted into the inner surface of the dielectrically separated island using the nitride film as a mask, they are diffused by the subsequent heat treatment to form an N + type buried diffusion layer. Therefore, it becomes possible to easily form the islands having the PN junction isolation in the islands having the dielectric isolation, and the N + type buried diffusion layers in the islands having the PN junction isolation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a partial cross-sectional view of an integrated circuit according to a first embodiment of the present invention, where (A) shows a region of a dielectric-isolated island and (B) shows a dielectric-isolated island. 1 shows one of the islands further separated by PN junction. The semiconductor integrated circuit according to the present embodiment has an island 1 which is dielectrically separated by a boron glass film 11 on a support substrate 10.
Are formed in large numbers, and some of the islands 1 are provided with islands 2 separated by PN junction.
Although not shown, a high breakdown voltage transistor DM having a breakdown voltage of, for example, several hundreds V is applied to the island 1 having a dielectric isolation, DM.
Elements such as OS and IGBT are housed. The island 2 separated by the PN junction has a small signal NP that does not require a breakdown voltage.
An N-type transistor or the like is stored.

That is, the dielectric-isolated island 1 is
It is partitioned by the V-shaped groove 3, and the V-shaped groove 3 is filled with the boron glass film 11 via the oxide film 12. The boron glass film 11 plays a role of adhering the island 1 whose dielectric is separated to the supporting substrate 10 which is another semiconductor substrate. Island 1 with dielectric isolation
Are further separated by a P-type diffusion region 16 from below and a P-type diffusion region 18 from above.

Then, the island 2 separated from the PN junction is formed.
Each of them has an N + type buried diffusion layer 17, and a plurality of small signal transistors or other semiconductor elements which do not require a withstand voltage are housed in the dielectrically isolated island 1. The P-type diffusion region 16 from below that forms the PN junction isolation is formed by diffusing the boron atoms of the boron glass film 11 from the opening 13 of the oxide film 3 into the island 1. N +
The type buried diffusion layer 17 is formed by diffusion from an N + type impurity layer which is ion-implanted in advance on the inner surface side of the oxide film 17 around the dielectric island 1. As shown in FIG. 1B, a P-type base region 20, an N + type emitter region 21, an N + type deep diffusion region 19 and the like, which form a small signal transistor, are provided in the island 2 separated from the PN junction. ing.

Next, a method of manufacturing the semiconductor integrated circuit of this embodiment will be described. First, as shown in FIG. 2, the surface of the N-type semiconductor substrate 15 is selectively subjected to anisotropic dry etching by resist patterning to form a V-shaped or U-shaped groove 3 having a depth of 50 to 150 μm. The V-shaped or U-shaped groove 3 may be formed by anisotropic etching using a KOH solution.

Next, as shown in FIG. 3, a thin pad oxide film 20 of about several hundred angstroms is grown on the entire surface of the semiconductor substrate 15, and further, low pressure (LP) CVD is performed.
The nitride film 21 is grown. Next, as shown in FIG. 4, an opening 22 is formed in the nitride film 21 by resist patterning. Then, using the nitride film 21 as a mask, arsenic is ion-implanted through the opening 22 to form the N + type impurity layer 17A.

Next, as shown in FIG. 5, using the nitride film 21 as a mask, a thick oxide film 12 is grown in the opening 22 to remove the nitride film 21 and the thin oxide film 20. Then, the boron glass film 11 is deposited on the surface of the semiconductor substrate 15. The boron glass film 11 is a silicate glass-based coating containing boron called soot, which is formed by reacting silicon tetrachloride with boron trichloride or the like by CVD. The boron glass film 11 is grown to such a thickness that the V-shaped groove 3 is embedded and its surface is substantially flat.

Next, as shown in FIG. 6, the semiconductor substrate 15 is turned over and its surface is attached to the supporting substrate 10.
That is, the surface of the semiconductor substrate 15 on which the boron glass film 11 is adhered is fitted to the surface of the support substrate 10, and, for example, 1
Heat at 200-1300 ° C. By this heat treatment, the boron glass film 11 is softened and the semiconductor substrate 15 and the supporting substrate 10 are firmly bonded and fixed. The support substrate 10
For this, a semiconductor substrate of the same type as the semiconductor substrate 15 is used. Since the support substrate 10 is merely for supporting the semiconductor substrate 15 by the boron glass film 11, it is preferable that the support substrate 10 be of the same type as the semiconductor substrate 15 from the viewpoint of the thermal expansion coefficient and the like, but a ceramic substrate or the like may be used. There is no.

Next, as shown in FIG. 7, polishing is stopped from the back surface side of the semiconductor substrate 15 and stopped when the head of the V-shaped groove 3 is exposed. The polishing of the semiconductor substrate 15 is performed by ordinary polishing. By this polishing, the semiconductor substrate 15 is divided into islands 1 which are dielectrically separated by the boron glass film 11 and the oxide film 12. In Island 1,
Boron atoms in the boron glass film 11 are diffused from the opening 13 of the oxide film 3 to form a P-type isolation diffusion region 16 from below. The separation diffusion region 16 and the N + type buried diffusion layer 17 from below are formed by being diffused in the island 1 by the growth of the boron glass film 11 and the heat treatment when the semiconductor substrate 15 is attached to the supporting substrate 10. To be done. Also,
The N + type buried diffusion layer 17 is initially selectively formed in the island 1 by using the nitride film 21 as a mask in the step shown in FIG. 4, but the boron glass film 11 through the opening 13 of the oxide film 12 is used. Since the concentration of boron atoms diffused in the island 1 is high, the conductivity type is converted from N + type to P + type in the island 1 near the opening 13 of the oxide film 12.

Next, as shown in FIG. 1B, a P + type diffusion region 18, a deep collector N + type diffusion region 19, a P + type base diffusion layer 20, an N + type emitter diffusion layer 21 and the like from the above. Are formed one after another, an island 2 having a PN junction isolation is formed in the island area 1 having a dielectric isolation, and a diffusion region of a device such as a small signal transistor is formed in the island 2. And although not shown, P
On the island 2 where the N junction is not separated, a semiconductor element such as a high breakdown voltage bipolar transistor is simultaneously formed by diffusion. Then, the high breakdown voltage type transistor and the small signal transistor are connected by a known wiring technique to complete a semiconductor integrated circuit including a high breakdown voltage semiconductor element.

FIG. 8 shows a sectional structure of a semiconductor integrated circuit of the second embodiment of the present invention. In this embodiment, a two-layer film of a polycrystalline silicon film 24 and a boron glass film 11 is used instead of the boron glass film in the first embodiment. Here, the polycrystalline silicon film 24 plays a role of a cushion sandwiched between the island 1 and the boron glass film 11 which are dielectrically separated. Polycrystalline silicon film 24
Is deposited by CVD prior to the boron glass film 11 and is highly doped to P type. The semiconductor integrated circuit of this embodiment can be manufactured by the other manufacturing steps by the same manufacturing process as that of the first embodiment.

When the polycrystalline silicon film 24 is deposited by the CVD method, it is deposited thicker than the flat portion inside the groove 3.
Since there is a limit to the depth of the groove 3 in which the boron glass film 11 can be completely buried, the polycrystalline silicon film 24 is formed by making the groove 3 substantially shallow so that the boron glass film 11 can be formed.
There is an effect that the groove 3 having a depth equal to or more than the limit can be formed.

In each of the embodiments described above, the example of forming the small signal transistor in the island region having the PN junction isolation has been described. However, a diode or a MOS transistor may be provided in the island region having the PN junction isolation. It goes without saying that, etc. may be formed. or,
The boron glass film is not limited to the above-mentioned embodiment, and any film can be used as long as it can fix the dielectrically separated islands on the supporting substrate. As described above, various modifications can be made without departing from the spirit of the present invention.

[0022]

As described above, according to the present invention,
An island region having a PN junction isolation is further provided in the dielectric isolation island. Therefore, it is possible to realize a semiconductor integrated circuit in which a high-breakdown-voltage type semiconductor element is housed in an island region having a dielectric isolation, and small signal transistors and the like related thereto are accommodated in an island having a PN junction isolation. Therefore, it is possible to economically produce a semiconductor integrated circuit including a high breakdown voltage semiconductor element with a small chip area.

Further, the P-type diffusion region 16 is formed by the chamber film 2
Since it is formed by the self-alignment method using 1,
The number of photomasks can be reduced and the process can be simplified as compared with the case where the N + type buried diffusion layer 17 and the opening 22 are formed separately.

[Brief description of drawings]

1A and 1B are cross-sectional views of a semiconductor integrated circuit according to an embodiment of the present invention, in which FIG. 1A shows a region of an island with dielectric isolation, and FIG. 1B shows a region of an island with PN junction isolation. Show.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit according to the first embodiment of the invention.

FIG. 8 is a sectional view of a semiconductor integrated circuit according to a second embodiment of the present invention.

Claims (2)

[Claims] 1. A step of forming an isolation groove on an N-type semiconductor substrate, a step of forming a thin oxide film and a nitride film on the entire surface of the semiconductor substrate, and an opening formed in a part of the nitride film. And a step of ion-implanting N + -type impurities from the opening using the nitride film as a mask, a step of forming a thick oxide film in the opening using the nitride film as a mask, and a nitride film using the mask. A step of removing a thin oxide film, a step of depositing a boron glass film by embedding the separation groove on the semiconductor substrate, and a step of attaching a deposition surface of the boron glass film to a support substrate, Forming a dielectric-isolated island by polishing from the back surface of the semiconductor substrate to reach the isolation trench; and boron-dielectric-isolated island from the boron glass film through an opening in the oxide film. Diffused in Forming a P-type isolation region from below, so as to contact the P-type isolation region from said lower,
Forming a P-type isolation region from above to form an island having a PN junction isolation in the dielectric isolation island; and forming a semiconductor element in the PN junction isolation island. A method of manufacturing a semiconductor integrated circuit, comprising: 2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a double layer film of a polycrystalline silicon film and a boron glass film is used instead of the boron glass film.