JPH0817886A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0817886A JPH0817886A JP6146074A JP14607494A JPH0817886A JP H0817886 A JPH0817886 A JP H0817886A JP 6146074 A JP6146074 A JP 6146074A JP 14607494 A JP14607494 A JP 14607494A JP H0817886 A JPH0817886 A JP H0817886A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- terminals
- wiring
- substrate
- internal circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体素子に内部回路には接続されていない端子を設
け、この端子を被着基板上の配線に接続した半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element is provided with a terminal which is not connected to an internal circuit and the terminal is connected to a wiring on a substrate.
【０００２】[0002]
【従来の技術】半導体素子はその内部に内部回路を有
し、その表面に内部回路と被着基板などに形成された外
部回路とを接続するための入出力端子が形成されてい
る。このような半導体素子をこの入出力端子部が被着基
板と対峙するように搭載する方法（フェースダウン）と
しては、マイクロバンプボンディング法やフリップチッ
プ法がある。2. Description of the Related Art A semiconductor element has an internal circuit therein, and an input / output terminal for connecting the internal circuit and an external circuit formed on a substrate to be adhered is formed on the surface thereof. As a method (face down) for mounting such a semiconductor element so that the input / output terminal portion faces the adherend substrate, there are a micro bump bonding method and a flip chip method.
【０００３】マイクロバンプボンディング法は、図４に
示すように、半導体素子１１の入出力端子部１２、１３
に金バンプ１４、１５を形成し、この金バンプ１４、１
５をガラスやセラミックなどから成る被着基板１６の配
線１７、１８に当接させて、半導体素子１１と被着基板
１６を光硬化性あるいは熱硬化性樹脂１７で接着する。
この場合、半導体素子１１の金バンプ１４、１５と被着
基板１６の配線１７、１８は光硬化性あるいは熱硬化性
樹脂１７が硬化する際の収縮力で当接しているのみであ
る。In the micro bump bonding method, as shown in FIG. 4, input / output terminal portions 12, 13 of a semiconductor element 11 are used.
Gold bumps 14 and 15 are formed on the
5 is brought into contact with the wirings 17 and 18 of the adherend substrate 16 made of glass or ceramic, and the semiconductor element 11 and the adherend substrate 16 are adhered to each other with the photocurable or thermosetting resin 17.
In this case, the gold bumps 14 and 15 of the semiconductor element 11 and the wirings 17 and 18 of the adherend 16 are only in contact with each other due to the contracting force when the photocurable or thermosetting resin 17 is cured.
【０００４】またフリップチップ法は、図５に示すよう
に、半導体素子１１の入出力端子部１２、１３にハンダ
バンプ１９、２０を形成し、このハンダバンプ１９、２
０を加熱して被着基板１６の配線１７、１８に接合させ
る。In the flip chip method, as shown in FIG. 5, solder bumps 19 and 20 are formed on the input / output terminal portions 12 and 13 of the semiconductor element 11, and the solder bumps 19 and 2 are formed.
0 is heated and bonded to the wirings 17 and 18 of the adherend substrate 16.
【０００５】[0005]
【発明が解決しようとする課題】ところが上述のような
半導体素子１１の入出力端子部１２、１３を被着基板１
６に対峙させて接続するフェースダウンボンディング法
では、半導体素子１１と被着基板１６が対峙する部分に
電気的接合部が位置するため、接合の状況が視覚的に確
認しずらいという問題があった。However, the input / output terminal portions 12 and 13 of the semiconductor element 11 as described above are attached to the substrate 1 to be adhered.
In the face-down bonding method in which the semiconductor element 11 and the adherend substrate 16 are opposed to each other in the face-down bonding method, there is a problem that it is difficult to visually confirm the bonding state because the electrical bonding portion is located. It was
【０００６】また一般に半導体素子１１を搭載した後
に、これを搭載したデバイスの性能等を評価すること
で、半導体素子１１の実装の良否が判別される。しか
し、半導体素子１１の正常動作に対して問題のない接続
抵抗の上限値と比較した場合、どれ位の余裕度があるか
については評価できないとい問題があった。In general, after the semiconductor element 11 is mounted, the performance of the device mounted with the semiconductor element 11 is evaluated to determine whether the semiconductor element 11 is mounted properly. However, when compared with the upper limit value of the connection resistance that does not cause a problem for the normal operation of the semiconductor element 11, there is a problem that it is not possible to evaluate how much margin is available.
【０００７】さらにデバイスの性能に異常を生じた場合
にも、半導体素子１１の内部回路に原因があるのか、半
導体素子１１の接続工程に原因があるのかも評価できな
い場合が多いという問題もあった。Further, even when the device performance is abnormal, it is often impossible to evaluate whether the cause is the internal circuit of the semiconductor element 11 or the connecting step of the semiconductor element 11. .
【０００８】このような理由から、フェースダウンボン
ディング法における半導体素子１１の実装において、半
導体素子１１と被着基板１６間の接続抵抗をより直接的
な方法で確認することが工程管理上望まれる。For these reasons, in mounting the semiconductor element 11 by the face-down bonding method, it is desirable in terms of process control to check the connection resistance between the semiconductor element 11 and the adherend substrate 16 by a more direct method.
【０００９】本発明は、このような従来技術の問題点に
鑑みてなされたものであり、半導体素子と被着基板間の
接続抵抗を直接的な方法で確認できる半導体装置を提供
することを目的とする。The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a semiconductor device in which the connection resistance between a semiconductor element and a substrate to be adhered can be confirmed by a direct method. And
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
に本発明に係る半導体装置では、内部回路を有する半導
体素子に、この内部回路とは独立して互いに接続された
少なくとも二つの端子を設け、この端子を被着基板上の
半導体素子との対峙部の外側に延在する配線に接続し
た。To achieve the above object, in a semiconductor device according to the present invention, a semiconductor element having an internal circuit is provided with at least two terminals connected to each other independently of the internal circuit. The terminal was connected to a wiring extending outside the facing portion of the adherend substrate to the semiconductor element.
【００１１】[0011]
【作用】上記のように構成すると、被着基板の配線部
で、半導体素子の端子と被着基板の配線の接続抵抗を直
接測定できる。もって半導体素子の正常動作に対して問
題のない接続抵抗の上限値と比較した場合の余裕度を具
体的に把握できると共に、半導体素子を搭載したデバイ
スの性能に異常を生じた場合にも、半導体素子の内部回
路に原因があるのか、半導体素子の接続工程に原因があ
るのか容易に把握できる。With the above structure, the connection resistance between the terminals of the semiconductor element and the wiring of the substrate can be directly measured at the wiring portion of the substrate. Therefore, it is possible to concretely grasp the margin when compared with the upper limit value of the connection resistance that does not have a problem for the normal operation of the semiconductor element, and also when the performance of the device equipped with the semiconductor element is abnormal, It is possible to easily understand whether the cause is the internal circuit of the element or the connection process of the semiconductor element.
【００１２】[0012]
【実施例】以下、本発明の実施例を添付図面に基づき詳
細に説明する。図１は本発明に係る半導体装置に用いら
れる半導体素子を入出力端子部が形成された側から見た
図であり、１は例えばシリコンなどから成る半導体素
子、２は例えば信号の出力端子、３、４は電源などの入
力端子、５、６、７、８、９は半導体素子１の内部回路
には接続されていない端子である。この半導体素子１は
例えば液晶ディスプレイの駆動用ＩＣとして用いられる
場合、図示していないが内部には例えばサンプリングパ
ルス発生回路、サンプルホールド回路、あるいは出力回
路などの内部回路が設けられてる。端子５、６、７、
８、９はこれらの内部回路には接続されていない。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a view of a semiconductor element used in a semiconductor device according to the present invention as seen from a side where an input / output terminal portion is formed. 1 is a semiconductor element made of, for example, silicon or the like, 2 is a signal output terminal, 3 Reference numeral 4 denotes an input terminal such as a power source, and reference numerals 5, 6, 7, 8 and 9 denote terminals not connected to the internal circuit of the semiconductor element 1. When the semiconductor element 1 is used as a driving IC for a liquid crystal display, for example, an internal circuit such as a sampling pulse generation circuit, a sample hold circuit, or an output circuit is provided inside although not shown. Terminals 5, 6, 7,
8 and 9 are not connected to these internal circuits.
【００１３】図２は図１中のａ−ａ’断面図であり、１
０はシリコン基板、１１はシリコン基板１０を熱酸化し
たフィールド酸化膜（ＳｉＯ2 ）である。フィールド酸
化膜１１上に、アルミニウム（Ａｌ）などから成る配線
パターン１２を設ける。この配線パターン１２は、上述
した内部回路とは電気的に接続されていない。配線パタ
ーン１２上に、プラズマＣＶＤ法などで形成した窒化シ
リコン膜などから成る絶縁保護膜１３を設け、この絶縁
保護膜１３の一部に透孔を形成して配線パターン１２上
に電気的に接続された端子５ａ、５ｂを設ける。この端
子５ａ、５ｂは例えばバリアメタル１４ａ、１４ｂと金
バンプ１５ａ、１５ｂで構成される。バリアメタル１４
ａ、１４ｂは、配線パターン１２と金バンプ１５ａ、１
５ｂの密着力を向上させるための金属層であり、通常は
多層構造をなし、配線パターン１２側から一層目はクロ
ム（Ｃｒ）やチタン（Ｔｉ）などで構成され、二層目は
タングステン（Ｗ）、パラジウム（Ｐｄ）、あるいはニ
ッケル（Ｎｉ）などで構成される。三層目として金の薄
膜層を形成してもよい。バリアメタル１４ａ、１４ｂ上
に金バンプ１５ａ、１５ｂを例えば電解メッキにより形
成する。この端子５ａ、５ｂは数十ミクロン程度のもの
である。FIG. 2 is a sectional view taken along the line aa 'in FIG.
Reference numeral 0 is a silicon substrate, and 11 is a field oxide film (SiO 2 ) obtained by thermally oxidizing the silicon substrate 10. A wiring pattern 12 made of aluminum (Al) or the like is provided on the field oxide film 11. The wiring pattern 12 is not electrically connected to the internal circuit described above. An insulating protective film 13 made of a silicon nitride film or the like formed by a plasma CVD method or the like is provided on the wiring pattern 12, and a through hole is formed in a part of the insulating protective film 13 to electrically connect to the wiring pattern 12. The connected terminals 5a and 5b are provided. The terminals 5a and 5b are composed of, for example, barrier metals 14a and 14b and gold bumps 15a and 15b. Barrier metal 14
a and 14b are wiring patterns 12 and gold bumps 15a and 1a.
5b is a metal layer for improving the adhesion, and usually has a multilayer structure, the first layer from the wiring pattern 12 side is made of chromium (Cr) or titanium (Ti), and the second layer is tungsten (W). ), Palladium (Pd), nickel (Ni), or the like. A gold thin film layer may be formed as the third layer. Gold bumps 15a and 15b are formed on the barrier metals 14a and 14b by, for example, electrolytic plating. The terminals 5a and 5b are of the order of several tens of microns.
【００１４】図３は半導体素子１を被着基板１６上に搭
載した状態を示す図であり、同図（ａ）は被着基板１６
の裏面側から透過して見た図、同図（ｂ）は断面図であ
る。被着基板１６には半導体素子１の端子１５ａに接続
される配線１７と、端子１５ｂに接続される配線１８が
設けられている。この被着基板１６上の配線１７、１８
は端子１５ａ、１５ｂの対峙部分から、半導体素子１の
被着基板１６との対峙部分の外側に延在して設けられて
いる。すなわち電気抵抗を測定するためのプローブを当
接しやすくするためである。被着基板１６の配線１７、
１８近傍に光硬化性樹脂材料または熱硬化性樹脂材料１
９を滴下して、半導体素子１を被着基板１６側に押し付
けながら光硬化性樹脂材料または熱硬化性樹脂材料１９
に光または熱を与えて硬化させることにより半導体素子
１を被着基板１６に接着する。この状態になると被着基
板１６の配線１７、１８は、半導体素子１の端子１５
ａ、半導体素子１の表面部近傍に形成した配線パターン
１２、および半導体素子１の端子１５ｂを介して電気的
に接続されることから、被着基板１６の配線１７、１８
間の電気抵抗を測定すれば、半導体素子１の端子１５
ａ、１５ｂと被着基板１６の配線１７、１８の接続抵抗
を測定することができる。FIG. 3 is a diagram showing a state in which the semiconductor element 1 is mounted on the substrate 16 to be adhered, and FIG. 3A is a diagram showing the substrate 16 to be adhered.
FIG. 3B is a cross-sectional view seen from the back side of FIG. A wiring 17 connected to the terminal 15a of the semiconductor element 1 and a wiring 18 connected to the terminal 15b are provided on the adherend substrate 16. Wirings 17, 18 on the adherend substrate 16
Is provided so as to extend from the facing portion of the terminals 15a and 15b to the outside of the facing portion of the semiconductor element 1 with the adherend substrate 16. That is, this is for facilitating contact with a probe for measuring electrical resistance. Wiring 17 of the substrate 16
Photocurable resin material or thermosetting resin material 1 near 18
9 is dropped and the semiconductor element 1 is pressed against the adherend substrate 16 side while a photocurable resin material or a thermosetting resin material 19 is applied.
The semiconductor element 1 is bonded to the adherend substrate 16 by applying light or heat to the resin to cure it. In this state, the wirings 17 and 18 of the substrate 16 are connected to the terminals 15 of the semiconductor element 1.
a, the wiring pattern 12 formed in the vicinity of the surface of the semiconductor element 1, and the terminals 15b of the semiconductor element 1 are electrically connected to each other.
If the electrical resistance between them is measured, the terminal 15 of the semiconductor element 1
The connection resistance between the wirings a and 15b and the wirings 17 and 18 of the adherend substrate 16 can be measured.
【００１５】また図１に示すように、このような接続抵
抗を測定するための端子５、６、７、８、９を半導体素
子１の一主面の複数箇所に離間して設ければ、半導体素
子１が傾いて接着されていないかどうかも判定できる。Further, as shown in FIG. 1, if terminals 5, 6, 7, 8, 9 for measuring such a connection resistance are provided at a plurality of locations on one main surface of the semiconductor element 1 at a distance, It can also be determined whether the semiconductor element 1 is inclined and is not bonded.
【００１６】図３に示す被着基板１６の配線１７、１８
は、金バンプなどから成る端子１５ａ、１５ｂとの接続
部が酸化等の影響を受けにくい導電性の酸化インジウム
錫（ＩＴＯ）が好ましいが、金バンプなどから成る端子
１５ａ、１５ｂとの接続部以外は、アルミニウム等を被
着して配線抵抗を下げた方が測定の精度がより向上す
る。Wirings 17 and 18 of the substrate 16 shown in FIG.
Is preferably conductive indium tin oxide (ITO), which is less susceptible to oxidation or the like at the connection with the terminals 15a, 15b made of gold bumps, but other than the connection with the terminals 15a, 15b made of gold bumps, etc. In order to reduce the wiring resistance by depositing aluminum or the like, the measurement accuracy is further improved.
【００１７】上記のようにマイクロバンプボンディグ法
では、端子１５ａ、１５ｂを被着基板１６の配線１７、
１８に当接させるだけで電気的接続を得ることから、こ
の接続抵抗を測定することは極めて重要であるが、本発
明はフリップチップ法で半導体素子１を被着基板１６上
に搭載する場合にも適用できる。As described above, in the micro bump bonding method, the terminals 15a and 15b are connected to the wiring 17 of the adherend substrate 16,
It is extremely important to measure this connection resistance because an electrical connection can be obtained only by bringing the semiconductor element 1 into contact with the substrate 18. However, according to the present invention, when the semiconductor element 1 is mounted on the adherend substrate 16 by the flip chip method. Can also be applied.
【００１８】[0018]
【発明の効果】以上のように、本発明に係る半導体装置
では、内部回路を有する半導体素子に、この内部回路と
は独立して互いに接続された少なくとも二つの端子を設
け、この端子を被着基板上の半導体素子との対峙部の外
側に延在する配線に接続したことから、被着基板の配線
部で、半導体素子の端子と被着基板の配線の接続抵抗を
直接測定できる。もって半導体素子の正常動作に対して
問題のない接続抵抗の上限値と比較した場合の余裕度を
具体的に把握できると共に、半導体素子を搭載したデバ
イスの性能に異常を生じた場合にも、半導体素子の内部
回路に原因があるのか、半導体素子の接続工程に原因が
あるのか容易に把握できる。さらに端子間の抵抗値を工
程管理することにより、デバイス特性としては良品でも
市場に出て不良になる可能性のあるものを選別できる。As described above, in the semiconductor device according to the present invention, the semiconductor element having the internal circuit is provided with at least two terminals which are connected to each other independently of the internal circuit, and the terminals are attached. Since the wiring is connected to the wiring extending outside the portion facing the semiconductor element on the substrate, the connection resistance between the terminals of the semiconductor element and the wiring of the substrate can be directly measured at the wiring portion of the substrate. Therefore, it is possible to concretely grasp the margin when compared with the upper limit value of the connection resistance that does not have a problem for the normal operation of the semiconductor element, and also when the performance of the device equipped with the semiconductor element is abnormal, It is possible to easily understand whether the cause is the internal circuit of the element or the connection process of the semiconductor element. Further, by controlling the resistance value between the terminals in a process, it is possible to select a device having good device characteristics, which may be defective in the market.
【図１】本発明に係る半導体装置に用いられる半導体素
子を示す図である。FIG. 1 is a diagram showing a semiconductor element used in a semiconductor device according to the present invention.
【図２】図１のａ−ａ’線拡大断面図である。FIG. 2 is an enlarged cross-sectional view taken along line aa ′ of FIG.
【図３】本発明に係る半導体装置の一実施例を示す要部
拡大図である。FIG. 3 is an enlarged view of a main part showing an embodiment of a semiconductor device according to the present invention.
【図４】従来の半導体装置を示す図である。FIG. 4 is a diagram showing a conventional semiconductor device.
【図５】従来の他の半導体装置を示す図である。FIG. 5 is a diagram showing another conventional semiconductor device.
１・・・半導体素子、５、６、７、８、９・・・端子、
１６・・・被着基板、１７、１８・・・被着基板の配線1 ... Semiconductor element, 5, 6, 7, 8, 9 ... Terminal,
16 ... Adhering substrate, 17, 18 ... Wiring of adhering substrate
Claims (4)
部回路とは独立して互いに接続された端子を設け、この
端子を被着基板上の半導体素子との対峙部の外側に延在
する配線に接続した半導体装置。1. A semiconductor element having an internal circuit is provided with a terminal that is connected to each other independently of the internal circuit, and the wiring extends to the outside of a portion facing the semiconductor element on the adherend substrate. Device connected to.
基板上の配線に当接した状態で接続され、且つ前記半導
体素子が前記被着基板に樹脂で接着されていることを特
徴とする請求項１に記載の半導体装置。2. A terminal provided on the semiconductor element is connected in a state of being in contact with a wiring on the adherend substrate, and the semiconductor element is adhered to the adherend substrate with a resin. The semiconductor device according to claim 1.
とを特徴とする請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the terminals are provided at a plurality of positions separated from each other.
の他の配線に接続されていないことを特徴とする請求項
１に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the wiring on the adherend substrate is not connected to another wiring on the adherend substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6146074A JPH0817886A (en) | 1994-06-28 | 1994-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6146074A JPH0817886A (en) | 1994-06-28 | 1994-06-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0817886A true JPH0817886A (en) | 1996-01-19 |
Family
ID=15399519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6146074A Pending JPH0817886A (en) | 1994-06-28 | 1994-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0817886A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6884378B2 (en) | 2001-05-14 | 2005-04-26 | Nan Ya Plastics Corporation | Methods for manufacturing super micro fibers |
| JP2005353757A (en) * | 2004-06-09 | 2005-12-22 | Toshiba Matsushita Display Technology Co Ltd | Semiconductor device and connection resistance measuring method |
| JP2007042865A (en) * | 2005-08-03 | 2007-02-15 | Seiko Epson Corp | Semiconductor device, method of inspecting same, and semiconductor wafer |
| KR101356406B1 (en) * | 2012-05-22 | 2014-01-27 | 브로드콤 코포레이션 | Wafer level package resistance monitor scheme |
-
1994
- 1994-06-28 JP JP6146074A patent/JPH0817886A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6884378B2 (en) | 2001-05-14 | 2005-04-26 | Nan Ya Plastics Corporation | Methods for manufacturing super micro fibers |
| JP2005353757A (en) * | 2004-06-09 | 2005-12-22 | Toshiba Matsushita Display Technology Co Ltd | Semiconductor device and connection resistance measuring method |
| JP2007042865A (en) * | 2005-08-03 | 2007-02-15 | Seiko Epson Corp | Semiconductor device, method of inspecting same, and semiconductor wafer |
| KR101356406B1 (en) * | 2012-05-22 | 2014-01-27 | 브로드콤 코포레이션 | Wafer level package resistance monitor scheme |
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