JPH0817474B2 - VTR synchronous coupling device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR synchronous coupling device for synchronously coupling other video signals and outputting a reproduced video signal of a video tape recorder (VTR) or the like.

2. Description of the Related Art FIG. 2 is a block diagram of a conventional VTR synchronous coupling device. In FIG. 2, reference numeral 1 is a head drum that outputs a reproduction RF signal from a recording medium. 6 is a drum phase control circuit for controlling the rotation phase of the head drum. Reference numeral 2 is a reproduced video signal processing circuit that demodulates the reproduced RF signal and outputs a reproduced video signal. Reference numeral 3 is a memory for delaying a reproduced video signal, and 4 is an output terminal. Reference numeral 5 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the reproduced video signal. Reference numeral 13 is an input terminal for inputting an externally synchronized video signal, and 12 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the external video signal. Reference numeral 14 is a delay circuit that delays the vertical synchronizing signal and outputs a leading vertical synchronizing signal that is a reference phase for drum phase control. Reference numeral 15 is a write reset control circuit which outputs a reset pulse of a write address of the memory 3, and 16 is a read reset control circuit which similarly outputs a reset pulse of a read address.

In the conventional VTR synchronous coupling device configured as described above, the external video signal input from the input terminal 13 is synchronously separated by the synchronous separation circuit 12, and a horizontal synchronous signal and a vertical synchronous signal are output. It Then, by delaying the vertical synchronizing signal of the external video signal by the delay circuit 14,
The head drum 1 outputs a phase-advancing vertical synchronizing signal that is equivalently advanced in phase, and becomes the reference phase of the drum phase control circuit 6.
Control the rotation phase of. Therefore, the head drum 1 has a delay circuit for the external video signal input from the input terminal 13.
It rotates synchronously with the phase advanced by the phase that 14 has. Therefore, the reproduced video signal obtained by processing the reproduced RF signal output from the head drum 1 by the reproduced video signal processing circuit 2 leads the external video signal by about the lead phase of the delay circuit 14. It is output in phase. This reproduced video signal is stored in the memory 3 and the sync separation circuit 5.
Is input to Then, the horizontal sync signal and the vertical sync signal of the reproduced video signal output from the sync signal separation circuit 5 are input to the write reset control circuit 15 to output the write address reset pulse of the memory 2. Further, the horizontal sync signal and the vertical sync signal of the external video signal output from the sync signal separation circuit 12 are input to the read reset control circuit 16 to output the read address reset pulse of the memory 2. Therefore, the memory 2 absorbs the lead phase of the reproduced video signal with respect to the external video signal, and also absorbs the time-axis fluctuation of the reproduced video signal. Therefore, the reproduced video signal synchronized with the external video signal is output from the output terminal 4. can get.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-described configuration, since the synchronous coupling of the external video signal and the reproduced video signal is roughly performed by the rotational phase control of the head drum 1, the capacity of the memory 2 is Basically, it should have enough capacity to absorb the time base fluctuation of the reproduced video signal. For this capacity, one horizontal period is usually sufficient. However, in reality, there is a considerable difference in the recording position of the video signal recorded on the recording medium due to the difference in accuracy of the VTR mechanism. As a result, even if the head drum 1 rotates at exactly the same rotation phase as the reference phase of the drum phase control circuit 6, the phase of the reproduced video signal output from the head drum 1 with respect to the reference phase is not fixed. When the number is large, the 3-4 horizontal periods may also change. Therefore, the lead phase amount of the delay circuit 14 must be set to an extra lead phase by that amount, and as a result, the capacity of the memory 2 also includes the phase difference of the reproduced video signal due to the variation of the recording position of the recording medium. You need a capacity to absorb,
There is a problem that a large capacity memory is required.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a VTR synchronous coupling device that can be configured with a small-capacity memory.

Means for Solving the Problems The present invention provides a first sync separation means for separating a horizontal sync signal and a vertical sync signal from an external signal to be synchronously combined, and a horizontal sync signal and a vertical sync from a reproduced video signal to be synchronously combined. Second sync separating means for separating the signal, delay means for delaying the vertical sync signal output from the second sync separating means by n / 2 horizontal periods (where n is a natural number), and the delay means. Phase comparison means for phase-comparing the output delayed vertical synchronization signal and the vertical synchronization signal output from the first synchronization separation means, and outputting a phase error voltage, and the first based on the phase error voltage Phase modulating means for phase-modulating the vertical synchronizing signal output from the sync separating means, and the rotational phase of the head drum for outputting the reproduced video signal to be synchronously coupled based on the phase-modulated vertical synchronizing signal. A VTR synchronous coupling device comprising a drum phase control means for controlling and a memory of n horizontal period length for delaying the reproduced video signal.

With the above-described structure, the present invention delays the vertical synchronizing signal separated and output from the reproduced video signal by the delay means, and then compares the phase with the vertical synchronizing signal separated and output from the external video signal. The phase of the vertical sync signal separated from the external video signal is phase-modulated, and the rotational phase of the head drum is controlled based on that, so the phase of the playback luminance signal output from the head drum affects the recording position on the recording medium. It can be fixed without receiving it.

Embodiment FIG. 1 is a block diagram of a VTR synchronous coupling device according to an embodiment of the present invention. In FIG. 1, 1
Is a head drum that outputs a reproduction RF signal from a recording medium. 6 is a drum phase control circuit for controlling the rotation phase of the head drum. Reference numeral 2 is a reproduced video signal processing circuit that demodulates the reproduced RF signal and outputs a reproduced video signal. Reference numeral 3 is a memory for delaying a reproduced video signal, and 4 is an output terminal. Reference numeral 5 is a sync separation circuit for separating the horizontal sync signal and the vertical sync signal from the reproduced video signal, and 9 is a delay circuit for delaying the vertical sync signal. Reference numeral 13 is an input terminal for inputting an externally synchronized video signal, and 12 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the external video signal. Reference numeral 10 denotes a phase comparison circuit that compares the phase of the vertical synchronizing signal output from the delay circuit 9 with the vertical synchronizing signal output from the synchronization separating circuit 12 and outputs a phase error voltage. Reference numeral 11 is a phase modulator that phase-modulates the vertical synchronization signal output from the synchronization separation circuit 12 based on the phase error voltage output from the phase comparator 10. 7 is a sync separation circuit 5
Reference numeral 8 denotes a write reset control circuit that outputs a reset pulse for the write address of the memory 3 from the horizontal sync signal output from the same. Reference numeral 8 also resets the read address of the memory 3 from the horizontal sync signal output from the sync separation circuit 12. It is a read reset control circuit that outputs a pulse.

The operation of the VTR synchronous coupling device of the present embodiment configured as described above will be described below. Head drum 1
The reproduced video signal obtained by signal processing of the reproduced RF signal output by the reproduced video signal processing circuit 2 is input to the memory 3 and the sync separation circuit 5. Then, the vertical synchronizing signal of the reproduced video signal output from the sync separation circuit 5 is delayed by the delay circuit 9 and then input to the phase comparator 10. On the other hand, the external video signal input from the input terminal 13 is synchronously separated by the synchronous separation circuit 12, and the vertical synchronous signal is input to the phase comparator 10 and the phase modulator 11. In the phase comparator 10, the vertical synchronizing signal of the reproduced video signal delayed by the delay circuit 9 and the vertical synchronizing signal of the external video signal are phase-compared with each other and a phase error voltage is output. Then, in accordance with the phase error voltage, the vertical synchronizing signal separated from the external video signal is phase-modulated by the phase modulator 11 and used as the reference phase of the drum phase control circuit 6 to control the rotational phase of the head drum 1. Here, the response speed of the phase modulator 11 is set to a time constant much slower than the response speed of the drum phase control circuit 6. By doing so, variations in the recording position of the recording medium can be absorbed by the phase modulator 11. Therefore, the reproduced video signal output from the reproduced video signal processing circuit 2 is not affected by the recording position of the recording medium at all and is delayed by the delay circuit 9 with respect to the external video signal input from the input terminal 13. It is output in the phase advanced by the amount. In the memory 3, the write address is reset by the write address reset pulse output from the write reset control circuit 7 according to the horizontal sync signal of the reproduced video signal output from the sync signal separation circuit 5. . A read address reset pulse is output from the read reset control circuit 8 in response to the horizontal sync signal of the external video signal output from the sync signal separation circuit 12 to reset the read address of the memory 3. It goes without saying that the write clock of the memory 3 is generated in synchronization with the horizontal synchronizing signal separated from the reproduced video signal, and the read clock is generated in synchronization with the horizontal synchronizing signal separated from the external video signal. . In this way, in the memory 3, the lead phase difference of the reproduced video signal output in the lead phase with respect to the external video signal, and the time-axis variation of the reproduced video signal generated around the phase difference Are absorbed and removed. Therefore, from the memory 3, the reproduced video signal perfectly phase-synchronized with the external video signal input from the input terminal 13 is read and output to the output terminal 4. Here, the capacity of the memory 3 may be such that it can absorb the time base fluctuation of the reproduced video signal. Then, in order to remove the maximum fluctuation of the time axis with the maximum capacity of the memory 3, the delay amount of the delay circuit 9 becomes n / 2 horizontal periods, provided that the capacity of the memory 3 is n horizontal period lengths. , N is a natural number). In this case, if the capacity of the memory 3 is two horizontal periods or more, the write reset control circuit 7 generates a write address reset pulse by dividing the horizontal synchronizing signal separated from the reproduced video signal. Similarly, the read reset control circuit 8 generates a read address reset pulse by dividing the horizontal synchronizing signal separated from the external video signal. At that time, the average phase difference between the write address reset pulse and the read address reset pulse must be an amount corresponding to the average phase difference between the external video signal and the reproduced video signal output from the reproduced video signal processing circuit 2. I have to. Therefore, according to the frequency division phase of the write reset control circuit 7,
The frequency division phase of the read reset control circuit 8 may be controlled, or the frequency division position of the write reset control circuit 7 may be controlled according to the frequency division phase of the read reset control circuit 8.

In the configuration of the embodiment of FIG. 1, the sync separation circuit 5
The vertical synchronizing signal of the reproduced video signal output by the delay circuit 9 is delayed by the delay circuit 9 and then input to the phase comparator 10. The reproduced video signal output from the reproduced video signal processing circuit 2 is delayed by the delay circuit. Then, the vertical sync signal may be separated by the sync separation circuit and then input to the phase comparator 10.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to use a VTR with a small-capacity memory that absorbs fluctuations in the reproduced video signal on the time axis.
It is possible to perform synchronous combination of the reproduced video signals. As a result, a low-cost VTR synchronous coupling device can be provided, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a VTR synchronous coupling device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional VTR synchronous coupling device. 1 ... Head drum, 2 ... Playback video signal processing circuit, 3
...... Memory, 5, 12 …… Synchronous separation circuit, 6 …… Drum phase control circuit, 7 …… Write reset control circuit, 8 …… Read reset control circuit, 9 …… Delay circuit, 10 …… Phase comparator ,
11 ... Phase modulator.

Claims (1)

[Claims] 1. A first sync separation means for separating a horizontal sync signal and a vertical sync signal from an external signal to be synchronously combined, and a second sync separation means for separating a horizontal sync signal and a vertical sync signal from a reproduced video signal to be synchronously combined. Sync delay means, a delay means for delaying the vertical sync signal output from the second sync separator means by n / 2 horizontal periods (where n is a natural number), and a delay vertical sync output from the delay means. Phase comparison means for comparing the phase of the signal and the vertical synchronization signal output from the first synchronization separation means and outputting a phase error voltage; and output from the first synchronization separation means based on the phase error voltage. Phase modulation means for phase-modulating the generated vertical synchronization signal, and a drum phase for controlling the rotational phase of the head drum for outputting the reproduced video signal to be synchronously coupled based on the phase-modulated vertical synchronization signal Control means, a memory having an n horizontal period length for delaying the reproduced video signal, and a write reset means for resetting a write address of the memory based on a horizontal sync signal output from the second sync separation means. And a read reset means for resetting the read address of the memory based on the horizontal sync signal output from the first sync separation means.