JPH0817316B2 - Pulse supply circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse supply circuit, for example, a pulse supply circuit used when supplying a pulse train for head switching of a video tape recorder.

2. Description of the Related Art In some conventional video tape recorders, as shown in FIG. 3, four video heads H1, H2, H3 and H4 are attached to a head drum 30 to enable special reproduction. Heads H1 and H2 mounted 180 ° apart from each other are usually used in a tape speed mode other than tape speed mode (SP mode), and heads H3 and H4 mounted 180 ° apart from each other are normal tapes. Used in speed mode. In this case, the heads H3 and H4 are arranged at positions apart from the heads H1 and H2 by 2H (H is one horizontal period).

Therefore, in the tape speed mode other than the normal tape speed mode, switching to the heads H1 and H2 is performed by the pulse train signal as shown in FIG. 5B, whereas in the normal tape speed mode, the head H1 and H2 are switched. As shown in, the switching to the heads H3 and H4 must be performed by the pulse train signal delayed by 2H with respect to the pulse train signal (b). Whether to operate the pulse train signal (b) or the pulse train signal (d) is set by a circuit according to a control signal (mode signal).

FIG. 4 shows a conventional pulse supply circuit for supplying a pulse train used for such head switching. In the figure, 40 is a counter that counts the time of 2H from the rising edge and the falling edge of the input pulse train having a duty of 50% shown in FIG. Is the D flip-flop 41
Applied to the clock terminal of. This D flip-flop
The input pulse train (b) is directly input to the D terminal of 41. As a result, the Q terminal of the D flip-flop 41 has a fifth
As shown in Fig. 2 (d), a pulse train is generated by delaying the input pulse train (b) by 2H. AND gates 43 and 44, inverter 4
2. The NOR gate 45 constitutes a switching circuit for switching between the pulse trains (b) and (d). AND gate 43
An input pulse train (b) is given to one input of the signal, and a signal obtained by inverting the control signal (FIG. 5 (a)) by the inverter 42 is given to the example input. On the other hand, an inverted signal of the control signal (a) is given to one input of the AND gate 44, and the output (d) of the D flip-flop 41 is given to the other input. The control signal (a) is a mode signal, the low level of which is a tape speed mode other than the normal tape speed mode, and the high level of which is a normal tape speed mode.

However, this conventional circuit is not only complicated, but is of a form sandwiched at a high level as shown by 46 in FIG. 5 (e) depending on the timing of switching of the control signal (a). The low level part may occur. When such a low level portion 46 is generated, at B1 from B channel to A
After switching to channel, switch to B channel at T2, and then switch to A channel at T3 immediately. Switching between A channel and B channel unnecessarily near the mode switch (that is, T2). To be However, in this case, it is desirable that the high level (A channel) is maintained immediately after T2 and the B channel is not switched. The A channel is the channel reproduced by the head H1 or H3, and the B channel is the head.
This is the channel played on H2 or H4.

The present invention has been made in view of such points,
An object of the present invention is to provide a novel pulse supply circuit which is realized with a simple configuration and which does not cause an unnecessary output change according to the control signal switching timing.

Means for Solving the Problems In order to achieve the above object, the present invention provides a pulse supply circuit that has a state of outputting an input pulse train as it is according to a control signal and a state of outputting a pulse train delayed by a predetermined time. A counter for counting the predetermined time from the pulse inversion point of, a logical product circuit for taking a logical product of the output of the counter and the control signal, the output of the logical product circuit is input to the clock terminal, and the input pulse train is input to the D terminal. And an input D latch circuit, and an output pulse train is obtained from the D latch circuit.

Operation According to such a configuration, the circuit is simple, and when the control signal is switched, an unnecessary change in the output does not occur.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.
In FIG. 1 in which the present invention is implemented, the input terminal 1 has a second
A pulse train having a duty of 50% shown in FIG. Reference numeral 2 is a counter that counts the time of 2H from the rising and falling of the pulse train (b), and its output (FIG. 2 (c)) is applied to the NAND gate 4 through the inverter 3. A control signal (a) (see FIG. 2) is also applied to the NAND gate 4. As a result, the NAND gate 4 outputs the signal shown in FIG. The output (e) is given to the clock terminal L of the next D latch circuit 6, and the pulse train signal (b) is given from the input terminal 1 to the D terminal of the D latch circuit 6. Then, the output pulse train shown in FIG. 2D is generated at the Q terminal of the D latch circuit 6. In the case of a video tape recorder, the control signal (a) is a Moso signal, which is a tape speed mode other than the normal tape speed mode when it is low level and a normal tape speed mode when it is high level. In this embodiment, the output signal does not change undesirably between the low level and the high level when the control signal is switched. Therefore, when the mode of the video tape recorder is switched, the A channel and the B channel are not undesirably switched and a stable image can be obtained.

The D latch circuit outputs the signal of the D terminal as it is while the voltage applied to the L terminal is at the high level, and latches the previous state when the voltage applied to the L terminal becomes at the low level. It is a thing.

As described above, according to the present invention, when the control signal is switched, an unnecessary change does not occur in the output pulse train, so that the head switching is smoothly performed when the tape speed mode of the video tape recorder is switched, for example. , A stable image can be obtained. Moreover, the pulse supply circuit of the present invention has a simple structure and can reduce the cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a pulse supply circuit embodying the present invention, and FIG. 2 is a timing chart for explaining its operation. FIG. 3 is a plan view of the head drum showing the positional relationship of the video heads in the video tape recorder. FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a timing chart for explaining its operation. 1 ... input terminal, 2 ... counter, 3 ... inverter,
4 ... NAND gate. 6 ... D latch circuit, 7 ... output terminal, 30 ... head drum, (a) ... control signal, (b) ... input pulse train, (d) ... output pulse train.

Claims (1)

[Claims] 1. A pulse supply circuit having a state of outputting an input pulse train as it is according to a control signal and a state of outputting a pulse train delayed by a predetermined time, and a counter for counting the predetermined time from a pulse inversion point of the input pulse train. A D-latch circuit that inputs the output of the counter and the control signal and a D-latch circuit that inputs the output of the AND circuit to a clock terminal and the input pulse train to a D terminal. A pulse supply circuit characterized in that an output pulse train is obtained from a latch circuit.