JPH08172546A - Synchronizing signal correction circuit - Google Patents

Abstract

PURPOSE: To provide a synchronizing signal correction circuit providing a stable synchronizing signal even when a defect such as chipped pulse tip takes place in a synchronizing signal in a video equipment such as a video display device. CONSTITUTION: The correction circuit is made up of an oscillator 11 oscillated at a prescribed frequency, a counter 12 counting its output frequency and reset by an input synchronizing signal C0, two decoders 13, 14 decoding a binary signal outputted from the counter 12, a flip-flop 15 set by the output of the decoder 13 and reset by the output of the decoder 14, and an OR circuit 16 ORing the output pulse of the flip-flop 15 and an input synchronizing signal. Then the decoder 13 provides the output of a pulse whose period is slightly longer than the period of the input synchronizing signal and the decoder 14 provides an output slightly after the output of the decoder 13, an output C13 of the flip-flop 15 is used to correct a chipped input synchronizing signal as a correction signal and the result is given to a PLL circuit 17 as a reference signal C1 of a PLL circuit to obtain a stable clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal correction circuit using a PLL for providing a stable synchronizing signal in a video device such as a video display device.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional PLL circuit, and FIG. 4B is a waveform of a main signal. Reference signal C1
And the phase of the reference signal C2 are compared by the phase comparator 1, and the output signal C3 corresponding to the phase difference is averaged by the LPF2 to obtain the VCO.
(Voltage controlled oscillator) 3 is driven to oscillate a frequency corresponding to the above phase difference C3. The output of the VCO 3 is the frequency of the output signal C4 of the target PLL in the counting circuit 4 and the reference signal C1.
Count down with the frequency ratio. By using the output of the counting circuit 4 as the reference signal C2, the output signal C4 synchronized with the reference signal C1 can be obtained. But Figure 4
For some reason, as indicated by point a in (B), the reference signal C
When the pulse lacking occurs at 1, the phase difference C3 between the standard signal C1 and the reference signal C2 becomes large, and the control voltage of the VCO greatly changes. Therefore, it takes some time until the output signal C4 of the PLL is again synchronized with the reference signal C1, and the frequency of the output signal C4 is disturbed. Therefore, in such a video display device that uses the output signal C4 as a synchronizing signal, a problem such as image bending on the screen occurs.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a synchronizing signal correction circuit which can obtain an output signal with little frequency fluctuation and quick recovery even if a reference signal is missing. It is provided.

[0004]

Means for detecting a deficiency of an input signal to be a reference signal, means for generating a correction pulse after detection of a deficiency, and means for adding the correction pulse to the input signal are provided. The missing input signal is corrected and used as the reference signal.

An oscillator that oscillates at a constant frequency, a counter that counts its output frequency and resets with an input reference pulse, two decoders that decode the binary signal output from the counter, and the output of one decoder It consists of a flip-flop that is set and reset by the output of another decoder, and an OR circuit that takes the logical sum of the output signal of the flip-flop and the input signal, and one decoder generates a pulse in a period slightly longer than the cycle of the input signal. Output, the other decoder outputs another
The two decoders output the signal just after the output to correct the lack of the input signal and use it as the reference signal of the PLL.

As a means for detecting a lack of an input signal to be a reference signal, a retriggerable monostable multivibrator that outputs a period slightly longer than the cycle of a reference pulse signal by a trigger input is used as a means for generating a correction pulse. Use a monostable multivibrator that triggers at the trailing edge of the output of the triggerable monostable multivibrator and outputs a pulse of approximately the same period as the input signal.If the reference pulse is missing, generate a correction pulse to generate a reference signal. Correct the deficiency to eliminate deficiency in the reference signal.

The input signal to be the reference signal is the horizontal synchronizing signal of the video signal, the corrected horizontal synchronizing signal is the reference signal of the PLL circuit, and the output signal of the PLL circuit is the sampling clock of the video signal.

The video signal sampled by using the output signal of the PLL circuit as a sampling clock of the video signal is PD
Display on P (plasma display panel).

[0009]

Since the lack of the input signal to be the reference signal is detected, and when the lack is detected, a correction pulse is generated to correct the lack of the input signal, so that the reference signal with less period disturbance can be obtained. By counting the output of the oscillator that oscillates at a constant cycle and detecting the lack of the reference pulse, it is possible to obtain a correct sync signal correction circuit with less malfunction. If the retriggerable monostable multivibrator is used to correct the lack of the reference pulse, a synchronization signal correction circuit can be obtained with a simple configuration. By inputting the reference pulse to the PLL circuit as the horizontal synchronizing signal of the video signal and using the output of the PLL circuit as the sampling clock of the video signal, it is possible to eliminate the adverse effects such as image bending on the screen when the video signal is displayed. You can

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sync signal correction circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1A is a block diagram of the main part of the synchronization signal correction circuit according to the present invention, and FIG. 1B is the waveform of the main pulse. Here, 11 is an oscillator, 12 is a counter, 13 and 14 are decoders, 15 is a flip-flop 16, an OR circuit, and 17 is a PLL circuit. Further, C0 is an input synchronization signal, C1 is a reference signal of the PLL, C11 is an output signal of the counter 11, and C12 is the counter 1
2 is an output signal, and C13 is an output signal of the lip flop 16. The oscillator 11 oscillates a pulse having a constant frequency, the output of which is counted by the counter 12 and is reset by the input synchronizing signal C0. The binary signal output of the counter 12 is the decoder 1
3 and the decoder 14 decode. In the decoder 13, when the counter 12 counts for a period slightly longer than the cycle of the input synchronizing signal C0, the output pulse C11 is output. Similarly, the decoder 14 outputs the output pulse C12 after the counter 12 has counted for a slightly longer period than the decoder 13.
By setting the flip-flop 15 with the output pulse C11 and resetting it with C12, the flip-flop 1
An output C13 of 5 is obtained. The output pulse C13 is used as a correction pulse, and the logical sum circuit 16 logically sums it with the input synchronizing signal C0 to obtain the corrected reference pulse signal C1. By inputting this corrected reference pulse signal as the reference signal of the PLL circuit 17, the PLL with less period disturbance
Obtain the output signal C4.

FIG. 2A is a block diagram of a main part of another embodiment according to the present invention, and FIG. 2B is a timing diagram. Here, 21 is a retriggerable monostable multivibrator, 22 is a monostable multivibrator, 23 is an OR circuit, and 24 is a PLL circuit. The retriggerable monostable multivibrator 21 is triggered by the input synchronizing signal C0 and outputs the pulse output C21 for a period slightly longer than the cycle of the input synchronizing signal C0. The monostable multivibrator 22 is triggered by the trailing edge of the output C21 and has a pulse C having substantially the same width as the input synchronizing signal C0.
22 is output. Therefore, as shown in FIG. 2B, when the input synchronization signal C0 is lacked a, the output C21 of the retriggerable monostable multivibrator 21 becomes 0 shortly thereafter. At that time, the monostable multivibrator 22 is triggered and outputs the pulse output C22.
The output pulse C22 and the input synchronizing signal C0 are logically summed by the logical sum circuit 23 to obtain the corrected reference signal C1.
Get. The corrected reference pulse signal is supplied to the PLL circuit 24.
By inputting as a reference signal of P
Obtain the LL output signal C4.

FIG. 3 is a block diagram of a main part of another embodiment according to the present invention. Here, 31 is a sync signal correction circuit, 32 is a PLL circuit, 33 is an AD (analog digital) converter, 34 is a PDP (presma display panel), C30 is a horizontal sync signal, C31 is an analog video signal, and C34 is a sampling clock. It is a signal. The horizontal synchronizing signal C30 is input to a correction circuit 31 similar to the above-described synchronizing signal correction circuit and input as a reference signal of the post-correction PLL 32 to obtain an output signal C34 of the PLL. The AD conversion circuit 33 uses this signal as a sampling clock. The analog video signal C31 is digitally converted and input as display data for the PDP 34. Further, by using the C34 as the data input clock of the PDP, it is possible to obtain the display without the image distortion of the display image on the PDP.

In the above embodiment, the PDP is assumed as the display device for displaying the image, but the display device is not limited to the PDP, and it is natural that the same effect can be obtained with an LCD (liquid crystal display) or the like. .

[0014]

When the lack of the input synchronization signal is detected, a correction pulse is generated to correct the lack, and the corrected signal is PL.
Since it is input to the PLL circuit as the L reference signal, the output of the PLL circuit with less disturbance of the cycle can be obtained. By counting the output of the oscillator that oscillates at a constant cycle and detecting the lack of the reference pulse, it is possible to obtain a correct sync signal correction circuit with less malfunction. If the lack of the reference pulse is detected by using the retriggerable monostable multivibrator, the synchronization signal correction circuit can be obtained with a simple configuration. The input signal serving as the reference signal is used as the horizontal synchronizing signal of the video signal, and the horizontal synchronizing signal is corrected by the synchronizing signal correction circuit to obtain P.
By inputting as the LL reference signal and using the output of the PLL circuit as the sampling clock of the video signal, it is possible to obtain a good display without adverse effects such as image distortion on the screen when the video signal is displayed.

[Brief description of drawings]

FIG. 1A is a block diagram of a main part of a synchronization signal correction circuit according to an embodiment of the present invention, and FIG. 1B shows the same signal waveform.

2A and 2B are block diagrams of a main part of a synchronization signal correction circuit according to another embodiment of the present invention, and FIG. 2B shows the same signal waveform.

FIG. 3 is a block diagram of a sync signal correction circuit used for displaying an image in another embodiment according to the present invention.

FIG. 4 is a conventional PLL circuit.

[Explanation of symbols]

 1 Phase Comparator 2 LPF 3 VFO 4 Counter 11 Oscillator 12 Counter 13 Decoder 14 Decoder 15 Philip Flop 16 Logical sum circuit 16 PLL circuit 21 Retriggerable monostable multivibrator 22 Monostable multivibrator 23 Logical sum circuit 24 PLL circuit 31 sync signal correction circuit 32 PLL circuit 33 AD converter 34 PDP C0 input sync signal C1 reference signal C4 PLL output signal

Claims (5)

[Claims] 1. A means for detecting a lack of a pulse of an input signal to be a reference signal, a means for creating a correction pulse after detecting the lack, a means for adding the correction pulse to the input signal, and a correction pulse for the correction pulse. Equipped with means to add to the input signal,
A synchronization signal correction circuit characterized by correcting a missing pulse of an input signal. 2. An oscillator that oscillates at a constant frequency, a counter that counts its output frequency and resets it with an input signal that should be a reference signal, and two decoders that decode the binary signal output from the counter. It consists of a flip-flop that is set by the output of one decoder and reset by the output of another decoder, and an OR circuit that takes the logical sum of the output pulse of the flip-flop and the input signal. 2. The synchronization signal correction circuit according to claim 1, wherein the pulse is output in a slightly longer period and the other decoder outputs the pulse slightly after the output of the other decoder. 3. A retriggerable monostable multivibrator that outputs a period slightly longer than the period of the reference pulse signal by a trigger input as means for detecting the lack of the pulse of the input signal to be the reference signal, after detecting the loss. As a means for creating a correction pulse, a monostable multivibrator that outputs a pulse of substantially the same period as the input signal to be the reference signal by triggering at the trailing edge of the retriggerable monostable multivibrator is used. The synchronization signal correction circuit according to claim 1. 4. An input signal to be a reference signal is a horizontal synchronizing signal of a video signal, a corrected input signal is a reference signal of a PLL circuit, and an output signal of the PLL circuit is a sampling clock of the video signal. The synchronization signal correction circuit according to claim 1. 5. The synchronization signal correction circuit according to claim 4, wherein the output signal of the PLL circuit is displayed on a PDP (plasma display panel) as a video signal sampled as a sampling clock of the video signal.