JPH08167891A - Digital signal extension system - Google Patents

Abstract

PURPOSE: To extend a fast digital signal by providing a divider circuit and a restoration circuit. CONSTITUTION: A transmitting part includes a flip-flop 21 which divides a digital circuit, and a receiving part includes a PLL circuit 23 which performs the restoration. The flip-flops 21 to 24 and 25 divided the digital signals, and the circuit 23 restores the digital signals divided toy a divider circuit into the undivided cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal extension system for transmitting and extending a digital signal from a transmitting section to a receiving section, and in particular, by providing a frequency dividing circuit and a restoring circuit, a high speed digital signal is provided. The present invention relates to a digital signal extension method capable of extending the signal.

[0002]

2. Description of the Related Art Generally, in order to transmit a digital signal,
From the viewpoints of signal timing adjustment and reflection prevention, delay flip-flops (hereinafter referred to as DF / F) that latch signals to ensure signal timing, and terminators that match impedance to prevent reflection ( End) is used.

FIG. 4 is a block diagram of a digital circuit applied to this type of digital signal extension system, and FIG. 5 is a time chart for explaining the operation of this digital circuit. In this digital circuit, the clock signal CLK, the data signal DATA, and the enable signal ENAB are extended and transmitted from the transmitting side to the receiving side.

Here, the clock signal CLK is as shown in FIG.
As shown in, the clock signal line 1 is input to the first transmitting side DF / F 3 on the data signal line 2 and the second transmitting side DF / F 5 on the enable signal line 4, and at the same time, the clock signal line is input. 1 to the receiving side. The transmitted clock signal CLK is received through the first terminator 6 on the clock signal line 1 and transmitted to the reception destination.
Similar to (a), the first receiving side DF / on the data signal line 2
Second receiving side DF / F 8 on F 7 and enable signal line 4
Is input to

As shown in FIG. 5B, the data signal DATA is input to the first transmitting side DF / F 3 from the data signal line 2 and based on the clock signal CLK, the first transmitting side DF / F 3 F
5 as shown in FIG. 5C, and
It is received through the second terminator 9 and the first reception side DF / F 7 on the data signal line 2 and transmitted to the reception destination as shown in FIG. 5 (d).

The enable signal ENAB is transmitted from the enable signal line 4 to the second transmitting side DF / F 5 as shown in FIG. 5 (e).
Is input to the third terminator 1 on the enable signal line 4 while being transmitted as shown in FIG. 5 (f) through the second transmitting side DF / F 5 based on the clock signal CLK.
0 and the second receiving side DF / F 8 receive
It is transmitted to the receiver as shown in (g).

The first to third terminators 6, 6
As 9 and 10, active terminators, Thevenin terminations, series terminations, parallel terminations or AC terminations can be used.

[0008]

However, in the digital signal extension system as described above, although the terminators 6, 9 and 10 for antireflection are provided, about 30 [MH] is required.
When a high-speed digital signal equal to or more than z] is extended-transmitted, it becomes difficult to receive the digital signal due to occurrence of reflection and the like, and there is a problem that extension transmission of the high-speed digital signal is impossible.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a digital signal extension system capable of extending a high-speed digital signal by providing a frequency dividing circuit and a restoring circuit. .

[0010]

According to a first aspect of the invention, in a digital signal extension system for transmitting and extending a digital signal from a transmitter to a receiver, the digital signal extension system is provided in the transmitter and divides the digital signal. A flip-flop that goes around
It is a digital signal extension system including a PLL circuit which is provided in the receiving unit and restores the frequency-divided digital signal to the cycle before the frequency division.

According to a second aspect of the present invention, in the digital signal extension system according to the first aspect, a digital signal provided in the preceding stage of the PLL circuit in the receiving section and divided by the flip-flop is used. It is a digital signal extension system equipped with an impedance matching circuit for blocking the reflection of.

Further, the invention corresponding to claim 3 is the digital signal extension system according to claim 1 or 2, wherein the flip-flop is a toggle flip-flop.

[0013]

Therefore, according to the invention corresponding to claim 1, the flip-flop for frequency division is provided in the transmitter while the PLL circuit for restoration is provided in the receiver by taking the above means. Since the flip-flop divides the digital signal and the PLL circuit restores the digital signal divided by the flip-flop to the period before the division, in the extension section between the transmitter and the receiver. Digital signal is F /
Since the speed is reduced to n [Hz] and problems such as reflection do not occur, high speed digital signals can be extended and transmitted.

The invention according to claim 2 has the impedance matching circuit for blocking the reflection in the receiving section, so that the same operation as the invention according to claim 1 can be achieved with a simple structure. It is possible to improve the reliability of extended transmission.

Further, in the invention according to claim 3, since the flip-flop is a toggle flip-flop, the same operation as the invention according to claim 1 can be achieved with a simple structure.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining the principle of a digital signal extension system according to an embodiment of the present invention. As shown, in this digital signal extension system,
The frequency dividing circuit 11 divides the high-speed digital signal of F [Hz] into F / n [Hz] on the transmitting side and transmits it to the receiving side, and the restoring circuit 12 and the F / n on the receiving side. The digital signal of [Hz] is restored to the original digital signal of F [Hz] and sent to the receiver.

Here, in the extension section between the frequency dividing circuit 11 on the transmitting side and the restoring circuit 12 on the receiving side, the digital signal is F
Since the speed is reduced to / n [Hz], problems such as reflection do not occur and high-speed digital signals can be extended and transmitted.

Next, a digital circuit applied to such a digital signal extension system will be specifically described. FIG. 2 is a block diagram of such a digital circuit. The same parts as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.

That is, the circuit of the present embodiment is different from the circuit shown in FIG. 4 in that a toggle flip-flop (hereinafter, referred to as a frequency dividing circuit for dividing the clock signal CLK of the clock signal line 1)
It is called TF / F. ) 21, and DF / F22 for timing and transmitting the output signal of this TF / F21, and
The clock signal line 1 includes a PLL circuit 23 as a restoration circuit that restores the clock signal CLK transmitted from the DF / F 22 and passed through the terminator 6 to the original frequency.

Also, D- for transparent latch
F / F 24 for terminator 9 of data signal line 2 and for receiving
It is provided between the DF / F 7, and similarly, the transparent latch DF / F 25 is provided between the terminator 10 of the enable signal line 4 and the receiving DF / F 8.

Next, a digital signal extension system using such a digital circuit will be described with reference to the time chart of FIG. Now, the clock signal CLK has a frequency of F [Hz], and as shown in FIG. 3 (h), the clock signal line 1 to the TF / F 21 and the DF / F 2 on the clock signal line 1 are
2, input to the first transmitting side DF / F 3 on the data signal line 2 and the second transmitting side DF / F 5 on the enable signal line 4.

The TF / F 21 supplies this clock signal CLK to
As shown in FIG. 3 (i), the frequency is divided into F / 2 [Hz] and DF /
Give to F 22. The DF / F 22 latches the divided clock signal of F / 2 [Hz] based on the clock signal CLK,
As shown in FIG. 3J, this divided clock signal is transmitted to the receiving side via the clock signal line 1. The transmitted divided clock signal is input to the PLL circuit 23 through the terminator 6 on the clock signal line 1.

The PLL circuit 23 multiplies this frequency-divided clock signal to F [Hz] and outputs the original clock signal CLK as shown in FIG.
Restored as shown in (k), the clock signal CLK is transmitted to the receiver, and the first receiver side on the data signal line 2
DF / F 7 and the second receiving side DF / on enable signal line 4
Enter in F8.

On the other hand, the data signal DATA is input from the data signal line 2 to the first transmitting side DF / F 3 as shown in FIG. 3 (l), and based on the clock signal CLK, the first transmitting side is sent.
It is transmitted through the DF / F 3 as shown in FIG. 3 (m) and is received by the transparent latch DF / F 24 through the second terminator 9 on the data signal line 2.

The DF / F 24 latches the data signal DATA on the basis of the clock signal CLK received from the PLL circuit 23 and, as shown in FIG.
To the first reception side DF / F 7 and the clock signal CLK
This data signal DATA is latched based on
The data is transmitted to the receiver as shown in (o).

Similarly, the enable signal ENAB is shown in FIG.
As shown in (p), the signal is input from the enable signal line 4 to the second transmitting side DF / F 5, and is transmitted through the second transmitting side DF / F 5 based on the clock signal CLK as shown in FIG. And is received by the transparent latch DF / F 25 through the third terminator 10 on the enable signal line 4.

The DF / F 25 receives the enable signal ENAB based on the clock signal CLK received from the PLL circuit 23.
Is latched and the second receiving side DF /
The second receiving side DF / F 8 supplies the clock signal to the F 8
Based on CLK, this enable signal ENAB is latched and transmitted to the receiver as shown in FIG. 3 (s).

As described above, according to this embodiment, TF / F
21 transmits a high-speed digital signal of F [Hz] on the transmission side to F
The frequency is divided into ½ [Hz] and transmitted to the receiving side via the DF / F 22, and the PLL circuit 23 at the receiving side receives this F / 2 [Hz].
The digital signal of is restored to the original digital signal of F [Hz] and is sent to the receiver. Therefore, the digital signal is as low as F / n [Hz] between the TF / F 21 and the PLL circuit 23. It is possible to extend and transmit a high-speed digital signal without causing a problem such as reflection due to being converted.

Further, according to this embodiment, each DF / F 3, 5, 7, 8, 22, 24, 25 on the transmitting side and the receiving side is based on the clock signal CLK having the original frequency F [Hz]. Since the latch is executed by the above, the signal timing can be adjusted without being affected by the provision of the TF / F 21 for frequency division and the PLL circuit 23 for restoration.

Further, according to the present embodiment, since the receiving section is provided with the terminators 6, 9 and 10 for preventing reflection, the reliability of extended transmission can be improved with a simple structure.

In the above embodiment, one TF / F 21
Although the case where the clock signal CLK is divided by 1/2 has been described by using, the present invention is not limited to this, and a plurality of TF / Fs are connected in multiple stages to divide the clock signal CLK by 1/4 and 1/8. 1 /
Even with a configuration in which the frequency is divided by 16, the same effects can be obtained by implementing the present invention in the same manner.

Further, in the above embodiment, the case where the divided clock signal of F / 2 [Hz] is doubled and restored to the clock signal CLK of F [Hz] by using one PLL circuit 23 will be described. However, not limited to this, the divided clock signal may be F / 4 [Hz], F / 8 [Hz], F / 16 [H]
z] ..., a configuration in which a plurality of PLL circuits are connected in multiple stages to restore the original clock signal CLK of F [Hz] can be implemented in the same manner and the same effect can be obtained.

Further, in the above embodiment, the case where the terminators 6, 9 and 10 are used for antireflection has been described, but the present invention is not limited to this, and the TF / F 21 for frequency division and the P for restoration are used.
When the frequency can be sufficiently reduced by only the LL circuit 23 to prevent reflection, the present invention can be similarly implemented and the same effect can be obtained even if the terminator is omitted.

In the above embodiment, the case where the transparent latch DF / Fs 24 and 25 are provided has been described. However, the present invention is not limited to this, and the transparent latch DF / Fs 24 and 25 may be omitted. Even if the first and second receiving side DF / Fs 7 and 8 are configured to adjust the timing of signals, the same effects can be obtained by implementing the present invention in the same manner. In addition, the present invention can be modified in various ways without departing from the scope of the invention.

[0035]

As described above, according to the first aspect of the present invention, while the flip-flop for frequency division is provided in the transmitting section, the PLL circuit for restoration is provided in the receiving section, and the flip-flop is a digital signal. And the PLL circuit restores the digital signal divided by the flip-flop to the period before the division, so that the digital signal is F / F in the extension section between the transmitter and the receiver. It is possible to provide a digital signal extension system capable of extending and transmitting a high-speed digital signal without causing a problem such as reflection due to a low speed of n [Hz].

Further, according to the invention of claim 2, since the receiving part is provided with the impedance matching circuit for preventing reflection, the effect of claim 1 can be obtained with a simple structure, and further, It is possible to provide a digital signal extension method capable of improving the reliability of extension transmission.

Further, according to the invention of claim 3, since the flip-flop is a toggle flip-flop, it is possible to provide a digital signal extension system having the same effect as that of claim 1, with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the principle of a digital signal extension system according to an embodiment of the present invention,

FIG. 2 is a configuration diagram of a digital circuit in the same embodiment,

FIG. 3 is a time chart for explaining the operation in the embodiment.

FIG. 4 is a configuration diagram of a digital circuit applied to a conventional digital signal extension system,

FIG. 5 is a time chart for explaining the operation of a conventional digital circuit.

[Explanation of symbols]

1 ... Clock signal line, 2 ... Data signal line, 3 ... First transmission side DF / F, 4 ... Enable signal line, 5 ... Second transmission side
DF / F, 6 ... First terminator, 7 ... First receiving side D-
F / F, 8 ... Second receiving side DF / F, 9 ... Second terminator, 10 ... Second terminator, 21 ... TF / F, 22,
24, 25 ... DF / F, 23 ... PLL circuit.

Claims (3)

[Claims] 1. A digital signal extension system for transmitting and extending a digital signal from a transmission unit to a reception unit, wherein a flip-flop provided in the transmission unit for dividing the digital signal, and provided in the reception unit, A digital signal extension system, comprising: a PLL circuit that restores the digital signal divided by the flip-flop to the period before the division. 2. The digital signal extension system according to claim 1, wherein the digital signal extension system is provided in a stage preceding the PLL circuit in the receiving section,
A digital signal extension system comprising an impedance matching circuit for preventing reflection of a digital signal divided by the flip-flop. 3. The digital signal extension system according to claim 1 or 2, wherein the flip-flop is a toggle flip-flop.