JPH08167597A - Etching method and device - Google Patents

Abstract

PURPOSE: To carry out an anisotropic etching process without using plasma by a method wherein halogen fluoride is introduced into a reaction chamber, and a light source is made to irradiate a stubstrate placed in the reaction chamber with light rays at a right angle. CONSTITUTION: A substrate 206 is placed on a substrate holder 204, and a reaction chamber 201 is reduced in pressure. Thereafter, a light source 205 provided above the substrate holder 204 is made to irradiate the substrate 206 with ultraviolet rays at a right angle, and halogen fluoride such as chlorine trifluaride diluted with nitrogen or argon for controlling an etching rate to a concentration of 1 to 10% is introduced as etching gas into the reaction chamber 201. An etching process is carried out keeping the reaction chamber 201 at 100m Torr. By this setup, foreign elements such as carbon and sulfur undesirable for a silicon semiconductor are restrained from mixing into it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to anisotropic etching of a conductive coating film whose composition is 95% or more of silicon, molybdenum and tungsten. Examples of such a conductive film include silicon in a single crystal, polycrystal or amorphous state, tungsten silicide (WSi ₂ ), molybdenum silicide (MoSi ₂ ), or a multilayer film of these, and the present invention substantially comprises these films. To a method of etching without using plasma.

[0002]

2. Description of the Related Art Due to the demand for miniaturization of semiconductor integrated circuits,
Various dry etching methods have been developed. In particular, as the aspect ratio (the ratio of length to width) becomes higher due to miniaturization, anisotropic etching (etching method in which etching selectively advances in the vertical direction) is required. Such fine processing requires halogen especially in the processing of semiconductor substrates, gate electrodes / wiring, and underlying wiring.
And for such wiring, silicon, tungsten,
Since molybdenum or a silicide thereof (silicide, for example, tungsten silicide (WSi ₂ ), molybdenum silicide (MoSi ₂ )) is used, an anisotropic etching technique for these materials has been important.

Conventionally, such etching is performed by using CF ₄ , S.
By ionizing F _{6 and} other fluoride gases with plasma, fluorine active species are generated and reacted with silicon, molybdenum and tungsten to etch as volatile silicon fluoride, molybdenum fluoride and tungsten fluoride. The method was common. However, in such an etching process, there is a risk that carbon and sulfur contained in the etching gas will combine with silicon and be mixed into the semiconductor element, and that the inner wall of the chamber used for etching for a long time has a Teflon-like shape. There is a problem that the polymer adheres.

Plasma is generated during etching.
It is necessary to prevent the plasma plasma from being applied to the semiconductor device.
There is also a problem that the image deteriorates device reliability.
On the other hand, with silicon, tungsten, and molybdenum as the main components
As the etching gas for the material
Nachi, chemical formula XF_n(X is a halogen other than fluorine, n
Is an integer) (eg ClF, ClF₃,
BrF, BrF ₃, IF, IF₃Etc.) are known.
Because these materials have an extremely strong fluorination effect,
Etching without generating active species by plasma
It had the feature that it could be done (gas etching). Only
However, in normal gas etching, side etching
To suppress etching and selectively etch only in the vertical direction.
Therefore, anisotropic etching is difficult
won.

[0005]

The present invention has been made to solve these problems. That is,
An object of the present invention is to provide a method of performing anisotropic etching using halogen fluoride as an etching gas and substantially not using plasma. As a result, foreign elements such as carbon and sulfur that are not preferable for silicon semiconductors are not mixed in the element. Further, maintenance of the etching chamber becomes easy. of course,
Plasma damage to the semiconductor element is also reduced, and reliability can be improved.

[0006]

DISCLOSURE OF THE INVENTION The present invention relates to chlorine fluoride (ClF), chlorine trifluoride (ClF ₃ ), chlorine pentafluoride (ClF ₅ ), bromine fluoride (BrF), bromine trifluoride ( BrF ₃ ), iodine fluoride (IF), iodine trifluoride (IF ₃ ), and other halogen fluorides are used as an etching gas, and the surface to be etched is exposed to light (ultraviolet light) substantially perpendicular to the substrate. Or laser light) to impart anisotropy to the etching. Further, for that purpose, an etching apparatus having a means for introducing halogen fluoride into the reaction vessel and a means for irradiating the substrate with light substantially perpendicularly is required.

[0007]

Function Gas etching using a normal fluoride halide is isotropic etching as in wet etching. For example, as shown in FIG. 1A, an etching mask 10 of a photoresist is formed on the silicon film 102 on the substrate 101.
When the film on which No. 3 is formed is etched, the halogen fluoride molecules that are responsible for the etching are isotropically incident on the sample surface, so that the etching surface becomes oblique as shown in FIG. In etching, the dotted line in FIG. 1B is the original etching mask. Due to the fluorination effect of halogen fluoride, the etching proceeds while the photoresist is also being etched. (Fig. 1 (B))

In order to have anisotropy in etching, the amount of radicals incident on the pattern side wall is reduced. A protective film is formed on the side wall to prevent contact between the film to be etched and the radical on the side wall. The reaction itself on the side wall is suppressed. It is necessary to meet either of the above. The present invention pays attention to one of these, and preferentially advances the reaction on the etching surface as compared with the reaction on the side surface, thereby giving anisotropy during etching.

In the present invention, light is irradiated substantially perpendicularly to the substrate to activate the halogen fluoride or the surface to be etched on the etching surface irradiated with light,
Allow the reaction to proceed easily. On the other hand, the reaction is slow on the side where light does not enter directly or the total amount of light is small. As a result, it is possible to give directivity to the etching direction, and it is possible to give anisotropy as shown in FIG. (Fig. 1 (B))

In order to carry out the present invention more effectively, it is advisable to cool the substrate in the case of a highly reactive material such as ClF or ClF ₃ . This is because, in such a highly reactive gas, a sufficiently high etching rate can be obtained even at room temperature, so that vertical etching cannot be selectively performed (anisotropy cannot be increased). is there.

[0011]

【Example】

[Embodiment 1] FIG. 2 shows an etching apparatus according to the present invention. The reaction vessel (chamber) 201 is provided with a gas introduction system 202 for introducing a reaction gas and an exhaust system 203 for reducing the pressure of the reaction vessel and having a detoxifying device for treating exhaust gas. The gas introduction system is ClF, Cl
_{F 3, ClF 5, BrF,} BrF 3, IF, as a diluting gas to adjust the addition to the etching rate of the halogen fluoride, including IF ₃ or the like, nitrogen and argon are provided. In this example, ClF ₃ was used as the halogen fluoride.

Further, the substrate holder 204 installed inside the reaction vessel is of a sheet type, and this holder has a room temperature to −
A temperature controller capable of changing the temperature up to about 20 ° C. is provided. Further, a light source 205 is provided above the substrate holder. In this embodiment, a UV lamp is used as this light source. this is,
It was preferred for etching large area substrates. Other than that, a rectangular laser beam or the like may be used.

An example of etching a mask-patterned silicon film as shown in FIG. 1A in an etching apparatus having the above-described structure is shown. First, the substrate 206 was placed on the substrate holder 204 and the pressure of the reaction container was reduced. Thereafter, while irradiating the substrate 204 with light (ultraviolet light in this embodiment) substantially vertically, ClF ₃ diluted with nitrogen or argon to 1 to 10% was introduced as an etching gas while controlling the etching rate. In this example, the concentration of ClF ₃ was diluted with nitrogen so as to be 5%. Then, set the pressure in the reaction vessel to 1
Etching was performed at 00 mTorr. As a result of performing the etching as described above, the etching selectively progressed in the vertical direction, and as shown in FIG. 1C, a substantially vertical etching end face was obtained.

Example 2 An example of manufacturing a new field effect transistor according to the present invention will be described with reference to FIG. As the design rules of semiconductor integrated circuits shrink, the drain-
Due to the steepness of the electric field strength between the channels, a hot carrier injection phenomenon has come to occur. The deterioration of the characteristics due to the reduction of the design rule (that is, the shortening of the channel) is generally called the short channel effect. As a method of suppressing such a short channel effect, a low concentration impurity region (low concentration drain, LDD) 30 as shown in FIG.
A MIS field effect transistor having 6,307 has been developed.

In this type of device, the LDD 30 having a lower concentration than the source / drain is provided between the source 304 and the channel forming region or between the drain 305 and the channel forming region.
Since Nos. 6 and 307 are provided, the effect of relaxing the electric field is produced, and the generation of hot carriers can be suppressed.
In the LDD as shown in FIG. 3, first, after forming the gate electrode 301, doping is performed to form a low-concentration impurity region, and then the side wall 302 is formed with a material such as silicon oxide. A method of forming a source / drain by consistently doping was adopted.

Therefore, the gate electrode does not exist on the LDD, and due to the further shortening of the channel, the phenomenon that hot carriers are trapped in the gate insulating film on the LDD occurs. Then, due to the trapping of such hot carriers, especially hot electrons, the conductivity type of the LDD is inverted, and the short channel effect such as the fluctuation of the threshold value, the increase of the subthreshold coefficient, and the decrease of the punch-through breakdown voltage is avoided. I can no longer.

In order to solve such a problem, an overlapping LDD structure (GOLD) structure has been proposed in which the LDD is also covered with a gate electrode. By adopting this structure, it is possible to avoid the deterioration of characteristics due to the trapping of hot carriers in the gate insulating film on the LDD as described above. However, it was not easy to produce GOLD. GOLD reported so far
As a MIS type field effect transistor having a structure, IT-
LDD structure (TY Huang: IEDM Tec
h. Digest 742 (1986)). The outline of the manufacturing method is shown in FIG.

First, after forming the field insulator 402 and the gate insulating film 403 on the semiconductor substrate 401, a conductive film 404 such as polycrystalline silicon is formed. (Fig. 4
(A) Then, the conductive film 404 is appropriately etched to form a gate electrode 406. At this time, it should be noted that the conductive film 404 is not completely etched, but the conductive film 407 is thin and has an appropriate thickness (100 to 1000 Å). Therefore, this etching process is extremely difficult. (405 indicated by the dotted line is the original conductive film.)

In this manner, LDDs 408 and 409 are formed by through doping through the thin conductive film 407 and the gate insulating film 403. At this time, if the conductive film is thick, it is not possible to sufficiently dope through-doping. Also,
If the thickness of the conductive coating differs between the substrates and between the batches, the dose amount will vary. (FIG. 4B) After that, a film 410 is formed on the entire surface with a material such as silicon oxide. (FIG. 4C) Then, the side wall 412 is formed by etching the film 410 by an anisotropic etching method as in the case of manufacturing a conventional LDD structure. In this etching process, the thin conductive film 407 is also etched.
Then, using the sidewalls thus formed as a mask, doping is performed in a self-aligned manner to form a source 413 and a drain 414. (Fig. 4 (D))

After that, the interlayer insulator 415, the source electrode,
A wiring 416 and a drain electrode / wiring 417 are formed to form MI.
The S-type field effect transistor is completed. (FIG. 4 (E)) As is clear from the figure, the gate electrode portion has an inverted T-shape (I
It is referred to as IT-LDD. Since the thin portion of the gate electrode exists on the LDD, the carrier density on the LDD surface can be controlled to some extent by the gate electrode. As a result, even if the impurity concentration of the LDD is made smaller, mutual conductance is reduced by the series resistance of the LDD, and device characteristics are less likely to be changed by hot carriers injected into the insulating film on the LDD.

These advantages are not unique to the IT-LDD structure but are common to all GOLD structures. Since the impurity concentration of LDD can be lowered, the electric field relaxation effect is large, and since the LDD can be made shallow, the short channel effect and punch through can be suppressed.

However, as a method for producing GOLD, there has been no effective method other than the IT-LDD structure. In the conventional LDD structure, it is not practical to simply form the sidewall with a conductive film containing silicon as a main component. This is because it is difficult to stop the etching at the time of forming the sidewalls with the gate insulating film containing silicon oxide as a main component, and there is a possibility that the substrate may be largely etched. This is because the conventional dry etching process does not have a sufficiently large selection ratio with respect to silicon oxide when etching silicon, and that the thickness of the gate insulating film is larger than that of the gate electrode (= sidewall). Is because it was as small as about 1/10.

Although the IT-LDD structure has many advantages as described above, there is a problem that the manufacturing method thereof is extremely difficult. In particular, it was extremely difficult to control the etching of the conductive film shown in FIG. If there is variation in the thickness of the thin conductive film 407 between the substrates or within the substrate, the impurity concentration of the source / drain fluctuates,
Therefore, the characteristics of the transistor vary.

By using the present invention, the sidewalls can be made of a material containing silicon, molybdenum, tungsten or the like as a main component (made of silicon having a purity of 95% or more) very easily. That is, a GOLD structure can be obtained by forming the sidewalls as a part of the gate electrode. In order to obtain such a structure, a conductive coating film made of a material containing silicon, molybdenum, or tungsten as a main component is formed so as to cover the central portion of the gate electrode, and then the present invention is carried out. Anisotropic etching may be performed.

According to the present invention, it is possible to sufficiently increase the etching selectivity between the sidewall material and the gate insulating film material in the etching for forming the sidewall. This is because the fluorinated halide has a characteristic that it hardly etches silicon oxide. As a result, not only overetching of the semiconductor substrate can be avoided, but also overetching of the gate insulating film is eliminated.

In the following, in the present embodiment, the portion corresponding to the gate electrode (301 in FIG. 3) in the conventional LDD structure is the gate electrode, but in the sense that it is not all of the gate electrode, the central portion of the gate electrode. Called. In addition, the portion corresponding to the sidewall of the conventional LDD structure (302 in FIG. 3) is also a conductive material composed of a material containing silicon as a main component, and at the same time, it is also a part of the gate electrode. Besides, it is also referred to as a side portion of the gate electrode.

FIG. 5 shows this embodiment. First, a silicon substrate 501 having a thickness of 3 is formed by a known LOCOS forming method.
A field insulator 502 having a thickness of 000Å to 1 μm was formed. Also, as a gate insulating film, a thickness of 100 to 500 Å
The silicon oxide film 503 was formed by the thermal oxidation method. Further, a polycrystalline silicon film (thickness 2000 to 5000 Å) having a conductivity increased by doping phosphorus by the thermal CVD method is deposited and etched to etch the central portion 50 of the gate electrode.
4 was formed. Then, phosphorus ion implantation was performed in a self-aligning manner using the central portion 504 of the gate electrode as a mask to form low-concentration N-type impurity regions (= LDD) 505 and 506. It is preferable that the concentration of phosphorus in LDD is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and the depth is 300 to 1000 Å. (Figure 5 (A))

Then, a polycrystalline silicon film (thickness: 2000), which is doped with phosphorus by the thermal CVD method to increase the conductivity,
Å-1 μm) 507 was deposited. (FIG. 5 (B)) After that, anisotropic etching with ClF ₃ was performed. This example uses the apparatus shown in FIG.
Same as above. First, the substrate 206 was placed on the substrate holder 204, and the reaction container was depressurized. Then substrate 2
While irradiating 04 with light (ultraviolet light in this example), ClF ₃ diluted with argon to 1 to 10% was introduced as an etching gas. In this embodiment,
It was diluted with nitrogen so that the concentration of ClF ₃ was 5%. Then, the pressure in the reaction vessel was set to 10 Torr.
The flow rate of ClF ₃ is 500 sccm, and the flow rate of nitrogen is 500
It was set to sccm.

As a result, the silicon film 507 was etched in the vertical direction, and the side portion (sidewall) 509 of the gate electrode was formed on the side surface of the central portion 504 of the gate electrode. (FIG. 5C) After that, arsenic ion implantation is performed to perform self-aligned doping using the gate electrode as a mask to form the source 5
10 and the drain 511 were produced. Arsenic concentration is 1 × 1
It was set to 0 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ . Then, the LDD and the source / drain were recrystallized by thermal annealing. (FIG. 5D) After that, a silicon oxide film 512 having a thickness of 3000 Å to 1 μm was deposited as an interlayer insulator by a thermal CVD method. Then, a contact hole is formed in the source electrode 5
13 and the drain electrode 514 were formed. In this way, a GOLD type transistor could be manufactured.
(Fig. 5 (E))

[0030]

According to the present invention, etching of a silicon substrate, which is important in a semiconductor integrated circuit, or polycrystalline silicon, molybdenum, tungsten, molybdenum silicide, tungsten silicide, polycide (a multi-layer film of silicon and tungsten silicide or molybdenum silicide), etc. Wiring can be etched. Moreover, in the etching of the present invention, since carbon and sulfur are not produced as by-products, the characteristics of the semiconductor element are not adversely affected. Further, even if the etching is performed for a long period of time, the polymer or the like does not adhere to the inner wall of the chamber, and the maintenance is easy.

Moreover, since the etching of the present invention does not use plasma, the reliability of the semiconductor device can be improved. Particularly, it is advantageous that the semiconductor substrate, the gate electrode / wiring, and the like which are the objects of the present invention are free from plasma damage. In the embodiments, an example of manufacturing a field effect transistor having a GOLD structure has been described, but the present invention is also effective in other cases. Needless to say, the same effect can be obtained by applying the present invention to a TFT formed on an insulating substrate other than the element on the semiconductor substrate. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1 shows a cross section of an isotropic and anisotropic etched shape of the present invention.

FIG. 2 schematically shows an etching apparatus of the present invention. (Example 1)

FIG. 3 shows a transistor having an LDD structure according to a conventional method.

FIG. 4 shows a method for manufacturing an IT-LDD type transistor by a conventional method.

FIG. 5 shows a method for manufacturing a GOLD type transistor according to a second embodiment.

[Explanation of symbols]

 101 ... Substrate 102 ... Silicon Film 103 ... Mask Patterning 201 ... Reaction Container (Chamber) 202 ... Gas Introducing System 203 ... Exhaust System 204 ... Sample holder 205 ... Light source 206 ... Substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 21/336 H01L 29/78 301 L (72) Inventor Yasuhiko Takemura Hase, Atsugi, Kanagawa Prefecture No. 398 Inside Semiconductor Energy Laboratory Co., Ltd.

Claims (6)

[Claims] 1. An etching apparatus comprising: a means for introducing halogen fluoride into a reaction container; and a light source for irradiating light substantially perpendicular to a substrate installed in the reaction container. . 2. The etching apparatus according to claim 1, wherein the light source is a UV lamp. 3. The etching apparatus according to claim 1, wherein the light source is a laser light source. 4. A material which is formed on a substrate by irradiating the substrate with light in a halogen fluoride atmosphere in a direction substantially perpendicular to the substrate and containing 95% or more of the composition of silicon, tungsten, or molybdenum in a vertical direction. An etching method characterized by etching in a direction. 5. The halogen according to claim 4, wherein the halogen fluoride is chlorine fluoride (ClF), chlorine trifluoride (ClF ₃ ), chlorine pentafluoride (ClF ₅ ), bromine fluoride (BrF), bromine trifluoride. (BrF ₃ ), iodine fluoride (IF) or iodine trifluoride (IF ₃ ), which is an etching method. 6. The material according to claim 4, in which 95% or more of the composition is occupied by any one of silicon, tungsten, and molybdenum, is tungsten silicide (WSi).
₂ ) or molybdenum silicide (MoSi ₂ ) is used.