JPH08163444A - Solid-state image pickup element and its drive method - Google Patents

Abstract

PURPOSE: To simplify the structure of a horizontal shift register of the solid-state image pickup element by holding information charge on an output side of a vertical shift register of an even numbered column. CONSTITUTION: Output control gate electrodes 33, 34 of a 1st layer with a wider width in an odd numbered column and a narrower width in an even numbered column are arranged on an output side of a vertical shift register 30 in parallel with a transfer gate electrode 32. Then output control gate electrodes 35, 36 of a 2nd layer with a narrower width in an odd numbered column and a wider width in an even numbered column are arranged onto the transfer gate electrode 32 and the output control gate electrodes 33, 34. Thus, the output control gate electrodes 35, 36 are overlapped onto the output control gate electrodes 33, 34 on an odd numbered column without being protruded and overlapped on an even numbered column so as to cover the gaps among the transfer gate electrode 32 and the output control gate electrodes 33, 34. Thus, the information charge of the vertical shift register 30 on an odd numbered column and the information charge of the vertical shift register 30 on an even numbered column are alternately extracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional solid-state image pickup device in which a plurality of light receiving pixels are arranged in a matrix and a driving method thereof.

[0002]

2. Description of the Related Art In a two-dimensional solid-state image pickup device used in an image pickup device such as a video camera, a so-called area sensor, a plurality of light-receiving pixels are arranged in a matrix, and a plurality of information charges generated in each light-receiving pixel by photoelectric conversion are formed. It is configured to read out in a predetermined order through the shift register.

In the case of a frame transfer type CCD solid-state image pickup device, as shown in FIG. 5, a plurality of vertical shift registers 1 continuous from the image pickup portion to the storage portion are arranged in parallel, and the output side of these vertical shift registers 1 is arranged. The horizontal shift register 2 is arranged at. The imaging unit electrically separates the vertical shift register 1 to form a plurality of light receiving pixels.
The information charges generated in these light receiving pixels are transferred from the image pickup section to the storage section in each vertical shift register 1 by the frame transfer clock FS and are temporarily stored therein. The information charges transferred to the storage section are transferred from each vertical shift register 1 to each bit of the horizontal shift register 2 in units of one row by the vertical transfer clock VS. Then, the information charges transferred to the horizontal shift register 2 are serially transferred to the output section 3 row by row by the horizontal transfer clock HS,
The output unit 3 converts the charge amount into a voltage value and outputs it as a video signal. On the other hand, in the case of an interline CCD solid-state image pickup device, as shown in FIG. 6, vertical shift registers 5 are arranged between columns of a plurality of light receiving pixels 4 arranged in rows and columns. The horizontal shift register 6 is arranged on the output side of the. The information charges generated in each light receiving pixel 4 are transferred to the vertical shift register 5, and then transferred from the vertical shift register 5 to the horizontal shift register 6 in units of one row by the vertical transfer clock VS. The information charges transferred to the horizontal shift register 6 are C in the frame transfer method.
Similar to the CD solid-state image pickup device, it is serially transferred row by row by the horizontal transfer clock HS to the output section 7 and output from the output section 3 as a video signal.

FIG. 7 shows a structure of a connecting portion between a vertical shift register and a horizontal shift register of such a CCD solid-state image pickup device. The vertical shift register 10 includes a channel region 11 formed on a semiconductor substrate and a plurality of transfer gate electrodes 12 and 13 having a two-layer structure. The channel region 11 is partitioned by a channel isolation region 14 formed of a thick oxide film or the like formed by selective oxidation, and each is electrically independent. This channel region 11 is P
It has a buried channel structure in which an N-type region is formed on the surface of the mold region. The transfer gate electrodes 12 of the first layer cross the channel isolation regions 14 and are arranged in parallel on each channel region 11 with a certain distance. The second-layer transfer gate electrode 13 is arranged on the channel region 11 so as to cover the gap between the transfer gate electrodes 12. The transfer gate electrodes 12 and 13 partially overlap each other, and are formed in common in each vertical shift register 10. Then, four-phase vertical transfer clocks VS1 to VS4 are applied to the transfer gate electrodes 12 and 13, respectively, and the information charges in the channel region 11 are sequentially transferred in the vertical direction by these vertical transfer clocks VS1 to VS4. . The horizontal shift register 20 includes a channel region 21 and a plurality of transfer gate electrodes 22 and 23 having a two-layer structure.
The channel region 21 is an island-shaped channel isolation region 24 continuous with the channel isolation region 14 of the vertical shift register 10.
And a separation region 25 opposed to the channel separation region 24, and is connected to the end of the channel region 11 of the vertical shift register 10 through each channel separation region 24. Like the channel region 11 of the vertical shift register 10, this channel region 21 also has a buried channel structure. The transfer gate electrode 22 of the first layer is arranged so as to extend between the channel isolation regions 24 and 25. In addition, every other transfer gate electrode 22 is extended to the vertical shift register 10 side to cover the connection portion between the channel region 11 and the channel region 21 of the vertical shift register 10 and also the output side end portion of the vertical shift register 10. Overlap with the transfer gate electrode 13 of. The transfer gate electrode 23 of the second layer is arranged on the channel region 21 so as to cover the gap between the transfer gate electrodes 22. The transfer gate electrodes 22 and 23 partially overlap each other, and two adjacent transfer gate electrodes 22 and 23 are commonly connected. Then, two-phase horizontal transfer clocks HS1 and HS2 are applied to the transfer gate electrodes 22 and 23, and the information charges in the channel region 21 are transferred in the horizontal direction by the horizontal transfer clocks HS1 and HS2. The horizontal transfer clocks HS1 and HS2 are vertical transfer clocks VS1 to VS4.
Is set so that the transfer of the information charges for one row is completed every time one bit of the information charges in the vertical shift register 10 is transferred. Therefore, all the information charges transferred from the vertical shift register 10 to the horizontal shift register 20 are output to the outside of the horizontal shift register 20 before the next information charge is transferred from the vertical shift register 10.

[0005]

In the CCD solid-state image sensor as described above, the transfer gate electrodes 22 and 23 of the horizontal shift register 20 are one column of the vertical shift register 10.
4 pieces are arranged for each. Therefore, the arrangement pitch of the vertical shift registers 10 cannot be narrower than the minimum interval required to arrange the four transfer gate electrodes 22 and 23 of the horizontal shift register 20. Therefore, in order to increase the number of light-receiving pixels and increase the resolution of the CCD solid-state imaging device, the chip area of the device must be increased, which is a factor of cost increase.

Therefore, an object of the present invention is to simplify the structure of the connecting portion between the vertical shift register and the horizontal shift register and to narrow the arrangement pitch of the vertical shift registers to enable high integration.

[0007]

The present invention has been made to solve the above-mentioned problems, and is characterized in that the information is arranged in the row and column directions and is responsive to light emitted. A plurality of light receiving pixels which generate electric charges, a plurality of vertical shift registers which are associated with each column of the plurality of light receiving pixels and which receive the information charges from the respective light receiving pixels and transfer them in the vertical direction, and a plurality of these vertical shift registers. Each bit is associated with each output of the shift register, and the horizontal shift register that receives the information charges from each vertical shift register and transfers them in the horizontal direction, and the information charges that are sequentially transferred and output from this horizontal shift register as voltage values In the solid-state image pickup device including: an output unit that generates a video signal by converting into a plurality of vertical shift registers, the plurality of vertical shift registers are commonly driven in each column, and the number of odd-numbered columns is larger than that of even-numbered columns. A plurality of output control electrodes disappears is to be disposed at the output end.

Then, the outputs of a plurality of vertical shift registers corresponding to each column of a plurality of light receiving pixels arranged in a matrix are received by each bit of a horizontal shift register, and one row of information charges generated in the plurality of light receiving pixels are received. In a method of driving a solid-state image sensor that outputs in units, the plurality of vertical shift registers are commonly driven in each column, and the plurality of output control electrodes arranged on the output side are independently driven in the vertical shift registers in even columns. However, while the information charges in the vertical shift registers in the odd columns are transferred and output through the horizontal shift registers, the information charges are held on the output side of the vertical shift registers in the even columns.

[0009]

According to the solid-state image pickup device of the present invention, by arranging a plurality of output control electrodes, the number of which is smaller in the odd columns than in the even columns, at the output side end of the vertical shift register, the vertical shift registers in the even columns It is possible to transfer the information charges from the vertical shift registers in the odd-numbered columns to the horizontal shift registers in a state in which the information charges are accumulated at the output side end of the. As a result, in the process of transferring the information charges from each vertical shift register to the horizontal shift register, the information charges from the light receiving pixels in the even columns and the information charges from the light receiving pixels in the odd columns can be distributed.

According to the solid-state image pickup device driving method of the present invention, while the information charges of the vertical shift registers in the odd columns are transferred and output through the horizontal shift registers, the information charges are output to the output side of the vertical shift registers in the even columns. By holding the information charges, the information charges are alternately output from the vertical shift registers in the odd columns or the vertical shift registers in the even columns to the horizontal shift registers. Therefore, the number of packets of information charges simultaneously transferred to the horizontal shift register is halved, and the number of bits of the horizontal shift register can be halved.

[0011]

1 is a plan view showing the structure of a connecting portion between a vertical shift register 30 and a horizontal shift register 40 of a solid-state image pickup device according to the present invention. The structure of this connection is
The present invention can be applied to any of the frame transfer type, interline type, and frame interline type solid-state imaging devices.

The vertical shift register 30 includes a channel region 31 formed on a semiconductor substrate, a plurality of transfer gate electrodes 32, first-layer output control gate electrodes 33 and 34, and second-layer output control gate electrodes 35 and 36. , 37. The channel region 31 is partitioned by a plurality of channel separation regions 38 arranged in parallel with each other, and each is electrically independent. This channel region 31 has a P
It has a buried channel structure in which an N-type region is formed on the surface of the mold region. The plurality of transfer gate electrodes 32 intersect the channel separation region 38 and are arranged in parallel on each channel region 31. Here, the transfer gate electrode 32
Has a single-layer structure, but it is also possible to have a two-layer structure in which a part thereof overlaps. The output control gate electrodes 33 and 34 of the first layer are the vertical shift registers 3 of the odd columns.
The width is 0 and the width is wide, and the width is formed narrow in the vertical shift registers 30 in even columns, and is arranged in parallel with the transfer gate electrode 32. As a result, the gap between the transfer gate electrode 32 and the output control gate electrodes 33 and 34 is narrow in the odd columns and wide in the even columns. Output control gate electrodes 35 and 36 of the second layer
Contrary to the output control gate electrodes 33 and 34 of the first layer,
The vertical shift registers 30 in the odd-numbered columns have a narrow width, and the vertical shift registers 30 in the even-numbered columns have a large width, and are arranged so as to overlap the transfer gate electrode 32 and the output control gate electrodes 33 and 34. At this time, in the odd-numbered columns, the output control gate electrodes 35 and 36 are respectively connected to the output control gate electrode 3
They overlap without protruding from 3, 34, and in the even-numbered columns, they overlap so as to cover the gap between the transfer gate electrode 32 and the output control gate electrodes 33, 34. As a result, the output control gate electrodes 35 and 36 of the second layer are effective for the channel region 31 only in the even columns. The output control gate electrode 37 of the second layer overlaps the output control gate electrode 34 at the output side end of the vertical shift register 30, and is arranged in parallel with the output control gate electrodes 35 and 36.

The transfer gate electrode 32, the output control gate electrodes 33, 34 of the first layer, and the output control gate electrodes 35, 36, 37 of the second layer are provided in each vertical shift register 30.
Are formed so that they are common to each other. For example, a three-phase vertical transfer clock V is applied to the plurality of transfer gate electrodes 32.
S1 to VS3 are applied respectively. The vertical transfer clock VS2 and the output control clock TG2 having the same phase as that of the third transfer gate electrode 32 are applied to the output control gate electrodes 33 and 34 of the first layer from the output control gate electrode 33 side, respectively. The output control gate electrode 3 of the second layer
5, 36 and 37, an output control clock TG1, a vertical transfer clock VS1 and an output control clock T having the same phase as the first transfer gate electrode 32 from the output control gate 35 side.
G3 is applied respectively. As a result, on the output side of the vertical shift register 30, only the potentials in the channel regions 31 of even columns are affected by the output control clock TG1 and the vertical transfer clock VS1. Therefore, it becomes possible to hold the information charges while the information charges are transferred from the vertical shift registers 30 in the odd columns to the horizontal shift register 40 side.

The horizontal shift register 40 comprises a channel region 41 and a plurality of transfer gate electrodes 42 and 43 having a two-layer structure. The channel region 41 is partitioned by an island-shaped channel isolation region 44 that is continuous with the channel isolation region 36 of the vertical shift register 30 and an isolation region 45 that faces the channel isolation region 44. It is connected to the end of the channel region 31 of the shift register 30. Similar to the channel region 31 of the vertical shift register 30, this channel region 41 also has a buried channel structure. The transfer gate electrode 42 of the first layer is formed in each channel isolation region 44, 45.
And extends to the side of the vertical shift register 30 and covers the connection portion between the channel region 31 and the channel region 41 of the vertical shift register 30. The second-layer transfer gate electrode 43 is arranged on the channel region 41 so as to cover the gap between the transfer gate electrodes 42. The transfer gate electrodes 42 and 43 partially overlap each other, and two adjacent transfer gate electrodes 42 and 43 are commonly connected. Then, the two-phase horizontal transfer clocks HS1 and HS2 are applied to the transfer gate electrodes 42 and 43, and the channel region 4 is caused by the action of the potential that changes in response to the clock operation of the horizontal transfer clocks HS1 and HS2.
The information charges in 1 are transferred in the horizontal direction.

FIG. 2 is a timing chart for explaining the driving method of the solid-state image pickup device of the present invention, and FIGS. 3 and 4 are the channel regions 31 and 41 at the timings TA0 to TA12 and TB0 to TB10 of FIG. It is a figure which shows the state of the potential inside.
Each gate electrode is turned on when the applied clock is at high level (H) and turned off when it is at low level (L).

First, as shown in FIG. 3, timing TA0
At ~ TA12, the information charges in the odd-numbered channel regions 31 are transferred to the channel regions 41 of the horizontal shift register 40. T when VS2 is H and VS1 and VS3 are L
At A0, the transfer gate electrode 32 corresponding to VS2 is turned on to form a potential well. Information charges will be accumulated in this potential well. At this time, in the potential well formed below the output control gate electrode 33 to which the vertical transfer clock VS2 is applied, the transfer of the information charge by the transfer operation before this has been completed, and the information charge has been accumulated. Absent. In addition, TG
1, TG2 and TG3 are all L, and the output control gate electrodes 34, 35 and 37 are off. VS3
When TA1 becomes H, the transfer gate electrode 32 corresponding to VS3 is turned on to form a potential well, and subsequently, at TA2 when VS2 becomes L, the transfer gate electrode 32 corresponding to VS2 is turned off. The potential well disappears. As a result, the information charges are transferred from below the transfer gate electrode 32 corresponding to VS2 to below the transfer gate electrode 32 corresponding to VS3. Similarly, at TA3 when VS1 becomes H, the transfer gate electrode 32 corresponding to VS1 is turned on,
When TA3 when VS3 becomes L and the corresponding transfer gate electrode 32 of VS3 is turned off, the information charges under the transfer gate electrode 32 corresponding to VS3 are transferred under the transfer gate electrode 32 corresponding to VS1. The transfer of the information charges from TA0 to TA4 is the same for the odd and even columns.

At TA5, when VS2 and TG1 are H,
The transfer gate electrode 32 corresponding to VS2 and the output control gate electrodes 33 and 35 are turned on to form a potential well, and subsequently, at TA6 when VS1 becomes L, the transfer gate electrode 32 corresponding to VS1 is turned off and the potential is increased. Well disappears. As a result, the information charges under the transfer gate electrode 32 corresponding to VS1 are transferred under the transfer gate electrode 32 corresponding to VS2 and under the output control gate electrodes 33, 35. At this time, in the odd column, the output control gate electrode 34 is arranged on the output control gate electrode 36, and even if VS1 applied to the output control gate electrode 34 changes, the potential under the output control gate electrode 36 remains It does not change. At TA7 when VS3 and TG2 become H, V
The transfer gate electrode 32 and the output control gate electrode 34 corresponding to S3 are turned on to form a potential well, and subsequently, at TA8 where VS2 becomes L, the transfer gate electrode 32 and the output control gate electrode 33 corresponding to VS2 are formed. Turns off and the potential well disappears. This allows VS
The information charge under the transfer gate electrode 32 corresponding to 2 is VS
3 is transferred below the transfer gate electrode 32. At the same time, in the odd columns, the information charges under the output control gate electrode 33 are transferred under the output control gate electrode 34. On the other hand, in the even-numbered columns, since the output control gate electrode 36 is off, the information charges below the output control gate electrode 33 are not transferred to below the output control gate electrode 34, but below the output control gate electrode 35. Collected in. T when TG3 became H
At A9, the output control gate electrode 37 is turned on to form a potential well, and then TG2 becomes L. TA1
At 0, the output control gate electrode 34 turns off and the potential well disappears. At this time, the transfer gate electrodes 42 corresponding to the vertical shift registers 30 in the odd columns are turned on, and in the channel regions 31 in the odd columns, the information charges below the output control gate electrodes 34 are transferred gate electrodes of the horizontal shift registers 40. 42. In the even-numbered columns, the information charge is not accumulated in the potential well below the output control gate electrode 34, so that the idle driving is performed. VS2 is H
At TA11 in which TG3 becomes L, the transfer gate electrode 32 and the output control gate electrode 33 corresponding to VS2 are turned on to form a potential well, and the output control gate electrode 37 is turned off to eliminate the potential well. To do. And, TA12 when VS3 and TG1 became L
Then, the transfer gate electrode 32 and the output control gate electrode 35 corresponding to VS3 are turned on to form a potential well. As a result, the information charges under the transfer gate electrode 32 corresponding to VS3 are reversely transferred under the transfer gate electrode 32 corresponding to VS2. At the same time, in the even-numbered columns, the information charges under the output control gate electrode 35 are transferred under the output control gate electrode 33. In this TA12 state, H
The clock operation of S1 and HS2 is repeated, and the information charges under the transfer gate electrodes 42 of the odd columns are horizontally transferred to the horizontal shift register along the channel region 41 of the gate 40. The horizontal shift register 4 is finally connected to HS1 and HS2.
The cycle is set so that the transfer of the information charges of 1/2 row in 0 is completed within a predetermined period. As a result, all the information charges in the channel region 41 of the horizontal shift register 40 are output to the outside of the horizontal shift register 40 until the next information charge is transferred from the vertical shift register 30.

Next, as shown in FIG. 4, timing TB0
From ~ TB10, the information charges in the even-numbered channel regions 31 are transferred to the channel regions 41 of the horizontal shift register 40. At the timing TB0 when the horizontal transfer operation of the horizontal shift register 40 is completed, HS1 is fixed to L and HS2 is fixed to H. As a result, the transfer gate electrodes 42 corresponding to the vertical shift registers 30 in the odd columns are turned off and the potential wells disappear, and the transfer gate electrodes 42 corresponding to the vertical shift registers 30 in the even columns are turned on and potential wells are formed. It By the way, in the odd-numbered columns, TA0-TA1
2, the transfer of the information charges has been completed, and the output control gate electrodes 33 to 37 and the output control gate electrode 3 have been completed.
Information charges are not accumulated under the transfer gate electrode 32 adjacent to the electrodes 3, 35.

At TB1 when VS1 and TG2 become H,
The transfer gate electrode 32 and the output control gate electrode 34 corresponding to VS1 are turned on to form a potential well,
Then, at TB2 when VS2 becomes L, the transfer gate electrode 32 and the output control gate electrode 33 corresponding to VS2 are turned off and the potential well disappears. This allows VS
The information charge under the transfer gate electrode 32 corresponding to 2 is V
Reverse transfer is performed under the transfer gate electrode 32 corresponding to S1. At the same time, information charges under the output control gate electrode 33 in the even columns are transferred under the output control gate electrodes 34, 36. At TB3 when VS3 becomes H, the transfer gate electrode 32 corresponding to VS3 is turned on to form a potential well, and subsequently at TB4 when VS1 becomes L, the transfer gate electrode 32 corresponding to VS1 and the output control. Gate electrode 3
6 turns off and the potential well disappears. As a result, the transfer gate electrode 32 corresponding to VS1 in TB1 to TB2
The information charges transferred below are further transferred below the transfer gate electrode 32 corresponding to VS1. At this time, the information charges under the output control gate electrodes 34 and 36 are collected on the output control gate electrode 34 side. At TB5 when TG3 becomes H, the output control gate electrode 37 is turned on to form a potential well, and then TG2 becomes L.
At B6, the output control gate electrode 34 is turned off and the potential well disappears. As a result, the information charges under the output control gate electrode 34 pass under the output control gate electrode 37 and are transferred under the transfer gate electrode 42 of the horizontal shift register 40. At TB7 where VS1 becomes H and TG3 becomes L, the transfer gate electrode 32 corresponding to VS1 is turned on to form a potential well, and the output control gate electrode 37 is turned off to eliminate the potential well. Then, at TB8 where VS3 becomes L, the transfer gate electrode 32 corresponding to VS3 is turned on to form a potential well. As a result, the information charges under the transfer gate electrode 32 corresponding to VS1 are transferred under the transfer gate electrode 32 corresponding to VS3. Furthermore, at TB9 when VS2 becomes H, the transfer gate electrode 32 corresponding to VS2 is transferred.
Is turned on to form a potential well, and then V
At TB10 when S1 becomes L, the transfer gate electrode 32 corresponding to VS1 is turned off and the potential well disappears. As a result, the transfer gate electrode 32 corresponding to VS1
Information charges below the transfer gate electrode 32 corresponding to VS2
Be transferred under. Then, in the state of TB10, the clock operations of HS1 and HS2 are repeated, and the information charges under the transfer gate electrodes 42 of the even columns are transferred in the horizontal direction along the channel region 41 of the horizontal shift register 40. The horizontal transfer operation of the information charges is the same as the transfer operation of the information charges under the transfer gate electrodes 42 in the odd columns.

The above timings TA0 to TA12, TB0 to TB
By repeating the operation of 10 and the horizontal transfer operation of the horizontal shift register 40, the information charges accumulated in the vertical shift register 30 can be sequentially read every 1/2 row. According to such a method of reading information charges, since the information charges for one row are separately collected in the odd columns and the even columns, the color filters to which different color components are given in the odd columns and the even columns are respectively received. It is suitable for a color solid-state image sensor mounted on a pixel. Further, when a continuous video signal is obtained in a predetermined order for each row, a line memory capable of storing a signal for ½ row is used to alternately take out the signals in the odd columns and the signals in the even columns. You can do this.

[0021]

According to the present invention, since the information charges of the odd columns and the information charges of the even columns of the solid-state image sensor are alternately read out, the horizontal shift register of the horizontal shift register receiving the outputs of the plurality of vertical shift registers is read. The number of bits can be reduced. Therefore, in the horizontal shift register, it is sufficient to dispose two transfer gate electrodes for one column of the vertical shift register. Therefore, the arrangement pitch of the vertical shift registers can be made narrower as the number of transfer gate electrodes is reduced, so that it is possible to improve the resolution by high integration and further reduce the cost by reducing the chip area.

When the color solid-state image pickup device equipped with a color filter composed of a plurality of color components is used, the video signals from the light receiving pixels in the odd columns and the video signals from the light receiving pixels in the even columns are used. Can be obtained in a pre-separated state. Therefore, the information representing the color component in the video signal does not include a high frequency component, and various signal processing for the video signal can be simplified.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a main part of a solid-state image sensor according to the present invention.

FIG. 2 is a timing diagram illustrating a method for driving a solid-state image sensor according to the present invention.

FIG. 3 is a potential diagram illustrating a method for driving a solid-state image sensor according to the present invention, showing a transfer process of information charges in odd columns.

FIG. 4 is a potential diagram illustrating a method for driving a solid-state image sensor according to the present invention, showing a process of transferring information charges in even columns.

FIG. 5 is a schematic diagram showing an outline of a frame transfer type solid-state imaging device.

FIG. 6 is a schematic diagram showing an outline of an interline type solid-state imaging device.

FIG. 7 is a plan view showing a structure of a connecting portion between a vertical shift register and a horizontal shift register of a conventional solid-state image sensor.

[Explanation of symbols]

1, 5, 10, 30 Vertical shift register 2, 6, 20, 40 Horizontal shift register 3, 7 Output unit 11, 21, 31, 41 Channel region 12, 13, 22, 23, 32, 42, 43 Transfer gate electrode 14, 24, 25, 36, 44, 45 Channel separation region 33, 34 First layer output control gate electrode 35, 36, 37 Second layer output control gate electrode

Claims (5)

[Claims] 1. A plurality of light receiving pixels, which are arranged in the row and column directions and generate information charges in response to light emitted, are associated with each column of the plurality of light receiving pixels. A plurality of vertical shift registers that receive the information charges and transfer them in the vertical direction, and each bit is associated with each output of the plurality of vertical shift registers, and receive the information charges from each vertical shift register and transfer them in the horizontal direction. In the solid-state imaging device, the horizontal shift register, and an output unit that converts the information charges sequentially transferred and output from the horizontal shift register into a voltage value to generate a video signal,
The solid-state imaging device according to claim 1, wherein the plurality of vertical shift registers are commonly driven in each column, and a plurality of output control electrodes, the number of which is smaller in an odd number column than in an even number column, is arranged at an output side end portion. 2. A plurality of light receiving pixels which are arranged in the row and column directions and which generate information charges in response to the applied light, and a plurality of light receiving pixels which are associated with each of the columns of the plurality of light receiving pixels. A plurality of vertical shift registers that receive the information charges and transfer them in the vertical direction, and each bit is associated with each output of the plurality of vertical shift registers, and receive the information charges from each vertical shift register and transfer them in the horizontal direction. In the solid-state imaging device, the horizontal shift register, and an output unit that converts the information charges sequentially transferred and output from the horizontal shift register into a voltage value to generate a video signal,
In the plurality of vertical shift registers, a plurality of transfer electrodes continuous in each column are arranged in parallel with each other, and at least two first output control electrodes parallel to the plurality of transfer electrodes are provided at an output side end portion. And at least two second output control electrodes are arranged so as to overlap the first output control electrodes in odd columns and cover the gap between the transfer electrodes and the first output control electrodes in even columns. A solid-state image sensor. 3. The solid-state image pickup device according to claim 1, wherein the horizontal shift register has two transfer electrodes corresponding to each column of the plurality of vertical shift registers. 4. A row of information charges generated in the plurality of light-receiving pixels is received by receiving the output of the plurality of vertical shift registers corresponding to each column of the plurality of light-receiving pixels arranged in a matrix into each bit of the horizontal shift register. In a method of driving a solid-state image sensor that outputs in units, the plurality of vertical shift registers are commonly driven in each column, and the plurality of output control electrodes arranged on the output side are independently driven in the vertical shift registers in even columns. However, while the information charges in the vertical shift registers in the odd columns are transferred and output through the horizontal shift registers, the information charges are held on the output side of the vertical shift registers in the even columns. Driving method. 5. The timing of transfer of the information charges to the horizontal shift register is set to 1 / horizontal scanning period in the vertical shift registers in the even columns than in the vertical shift registers in the odd columns.
The method for driving a solid-state imaging device according to claim 4, wherein the period is delayed by 2.