JPH08162643A - Structure of thin-film transistor and its manufacture - Google Patents
Structure of thin-film transistor and its manufactureInfo
- Publication number
- JPH08162643A JPH08162643A JP32978794A JP32978794A JPH08162643A JP H08162643 A JPH08162643 A JP H08162643A JP 32978794 A JP32978794 A JP 32978794A JP 32978794 A JP32978794 A JP 32978794A JP H08162643 A JPH08162643 A JP H08162643A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- semiconductor layer
- film transistor
- thin film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000010408 film Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 3
- 239000002019 doping agent Substances 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 18
- 238000010276 construction Methods 0.000 abstract 3
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子の薄膜トラン
ジスタに係り、特にＳＲＡＭのメモリセルに適する薄膜
トランジスタの構造及びその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor of a semiconductor device, and more particularly to a structure of a thin film transistor suitable for a memory cell of SRAM and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】一般に、ｐ型薄膜トランジスタは１Ｍ級
以上のＳＲＡＭ素子において負荷抵抗器の代わりに用い
られ、Ｎ型薄膜トランジスタは液晶表示素子において各
画素領域の画像データ信号をスイッチングするスイッチ
ング素子として広く用いられている。2. Description of the Related Art Generally, a p-type thin film transistor is used in place of a load resistor in an SRAM element of 1M class or higher, and an N-type thin film transistor is widely used as a switching element for switching an image data signal of each pixel region in a liquid crystal display element. Has been.
【０００３】高品質のＳＲＡＭを作るためには、ｐ型薄
膜トランジスタのオフ電流を減少させ且つオン電流を増
加させなければならず、これにより、ＳＲＡＭセルの消
費電力を減少させることができ、記憶特性を向上させる
ことができる。In order to manufacture a high quality SRAM, the off current and the on current of the p-type thin film transistor must be reduced, which can reduce the power consumption of the SRAM cell and the storage characteristics. Can be improved.
【０００４】最近、前記の原理によってオン／オフ電流
比を向上させるための研究が活発に行われている。この
ようにオン／オフ電流比を向上させるための従来の薄膜
トランジスタの製造方法を図面とともに説明する。Recently, studies have been actively conducted to improve the on / off current ratio based on the above-mentioned principle. A conventional method of manufacturing a thin film transistor for improving the on / off current ratio will be described with reference to the drawings.
【０００５】図１は、従来の薄膜トランジスタの工程断
面図である。従来の薄膜トランジスタの製造方法は、図
１（ａ）のように絶縁基板１上にゲート電極２を形成
し、全面にゲート絶縁膜３を形成する。図１（ｂ）のよ
うにその上にポリシリコン等の真性半導体層４を蒸着す
る。図１（ｃ）のように前記真性半導体層４にチャンネ
ルイオン（ｎ型イオン）を注入する。図１（ｄ）のよう
に全面にわたって第１酸化膜５を蒸着し、ホトエッチン
グ工程によりゲート電極２の上側のチャンネル領域にの
み残るように第１酸化膜５をパターニングした後、前記
パターニングされた第１酸化膜５をマスクとして前記真
性半導体層４に低濃度のソース／ドレーンイオン（ｐ
- ）を注入して低濃度のソース／ドレーン不純物領域６
を形成する。図１（ｅ）のように、全面にわたって第２
酸化膜を厚く蒸着し、前記第２酸化膜を異方性エッチン
グして第２酸化膜の側壁７を形成した後、前記第１酸化
膜５と第２酸化膜の側壁７をマスクに用いて高濃度のソ
ース／ドレーンイオン（ｐ+ ）を注入する。図１（ｆ）
のように、前記第１酸化膜５と第２酸化膜の側壁７を除
去して、ＬＤＤ構造の薄膜トランジスタを完成する。FIG. 1 is a process sectional view of a conventional thin film transistor. In the conventional method of manufacturing a thin film transistor, a gate electrode 2 is formed on an insulating substrate 1 and a gate insulating film 3 is formed on the entire surface as shown in FIG. As shown in FIG. 1B, an intrinsic semiconductor layer 4 such as polysilicon is vapor-deposited thereon. As shown in FIG. 1C, channel ions (n-type ions) are implanted into the intrinsic semiconductor layer 4. As shown in FIG. 1D, a first oxide film 5 is deposited on the entire surface, and the first oxide film 5 is patterned by a photo-etching process so that it remains only in a channel region above the gate electrode 2. Then, the patterning is performed. Using the first oxide film 5 as a mask, the intrinsic semiconductor layer 4 has a low concentration of source / drain ions (p
- ) Is implanted to form a low concentration source / drain impurity region 6
To form. As shown in FIG. 1 (e), the second
After thickly depositing an oxide film and anisotropically etching the second oxide film to form a sidewall 7 of the second oxide film, the sidewalls 7 of the first oxide film 5 and the second oxide film are used as a mask. Implant a high concentration of source / drain ions (p + ). Figure 1 (f)
As described above, the sidewalls 7 of the first oxide film 5 and the second oxide film are removed to complete a thin film transistor having an LDD structure.
【０００６】[0006]
【発明が解決しようとする課題】しかし、このような従
来の薄膜トランジスタには次のような問題点がある。即
ち、ＬＤＤ構造のソース／ドレーン領域を形成するため
には別途のマスク工程と、前記マスクを除去する工程と
が必要であるから、工程が複雑であり、さらに、工程の
回数が増加して歩留まりが低下し、薄膜トランジスタの
特性が低下するという問題点がある。However, such a conventional thin film transistor has the following problems. That is, since a separate mask process and a process for removing the mask are required to form the source / drain regions of the LDD structure, the process is complicated, and the number of processes is increased and the yield is increased. And the characteristics of the thin film transistor are degraded.
【０００７】本発明は、上記問題点を解決するためのも
のであり、工程の回数を減少させて歩留まり及び薄膜ト
ランジスタの特性を向上させることにその目的がある。The present invention is intended to solve the above problems, and its object is to reduce the number of steps and improve the yield and characteristics of thin film transistors.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明の薄膜トランジスタの構造は、絶縁基板と、
前記絶縁基板上に形成されるゲート電極と、前記ゲート
電極と絶縁基板とに形成されたゲート絶縁膜と、前記ゲ
ート絶縁膜上に形成される半導体層と、前記半導体層の
前記ゲート電極の両側面に沿う部分に形成されるチャン
ネル領域と、前記ゲート電極の上側の半導体層に形成さ
れる高濃度の第１導電型第１不純物領域と、前記ゲート
電極の部分以外の絶縁基板上の半導体層に形成されるＬ
ＤＤ構造の第１導電型第２不純物領域とを有する。本発
明の薄膜トランジスタの製造方法は、絶縁基板上にゲー
ト電極を形成し、全面にわたってゲート絶縁膜を形成す
る工程と、前記ゲート絶縁膜上に半導体層を形成する工
程と、前記半導体層に垂直に低濃度のソース／ドレーン
不純物イオンを注入する工程と、前記ゲート電極の両側
の半導体層の側壁に絶縁膜の側壁を形成する工程と、前
記絶縁膜の側壁をマスクとして用いて半導体層に高濃度
のソース／ドレーンイオンを注入する工程とを含んでな
ることを特徴とする。In order to achieve the above object, the structure of a thin film transistor of the present invention comprises an insulating substrate,
A gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode and the insulating substrate, a semiconductor layer formed on the gate insulating film, and both sides of the gate electrode of the semiconductor layer. A channel region formed in a portion along the surface, a high-concentration first conductivity type first impurity region formed in the semiconductor layer above the gate electrode, and a semiconductor layer on the insulating substrate other than the gate electrode portion L formed on
And a first conductivity type second impurity region having a DD structure. A method of manufacturing a thin film transistor of the present invention comprises a step of forming a gate electrode on an insulating substrate and forming a gate insulating film over the entire surface, a step of forming a semiconductor layer on the gate insulating film, and a step perpendicular to the semiconductor layer. Implanting low concentration source / drain impurity ions, forming sidewalls of an insulating film on sidewalls of the semiconductor layer on both sides of the gate electrode, and using high concentration on the semiconductor layer using the sidewalls of the insulating film as a mask And the step of implanting source / drain ions of.
【０００９】[0009]
【実施例】前記本発明の薄膜トランジスタの構造及びそ
の製造方法を図面とともに説明する。図２は本発明の薄
膜トランジスタの構造斜視図であり、図３は本発明の薄
膜トランジスタの工程断面図である。本発明の薄膜トラ
ンジスタの構造は、図２のように絶縁基板１上にゲート
電極２が形成され、前記ゲート電極２と基板とに酸化膜
などのゲート絶縁膜３が形成され、前記ゲート絶縁膜３
上に半導体層４が形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the thin film transistor of the present invention and the manufacturing method thereof will be described with reference to the drawings. 2 is a structural perspective view of the thin film transistor of the present invention, and FIG. 3 is a process sectional view of the thin film transistor of the present invention. In the structure of the thin film transistor of the present invention, as shown in FIG. 2, the gate electrode 2 is formed on the insulating substrate 1, and the gate insulating film 3 such as an oxide film is formed on the gate electrode 2 and the substrate.
The semiconductor layer 4 is formed thereon.
【００１０】そして、半導体層４の前記ゲート電極の両
側面に沿う部分にはトランジスタのチャンネル領域が形
成され、前記ゲート電極２の上側の部分には高濃度ｐ型
第１不純物領域９が形成される。さらに前記ゲート電極
２の部分を除いた基板上の半導体層４にはＬＤＤ構造の
ｐ型第２不純物領域１０ａ，１０ｂが形成される。A channel region of the transistor is formed in a portion of the semiconductor layer 4 along both side surfaces of the gate electrode, and a high concentration p-type first impurity region 9 is formed in an upper portion of the gate electrode 2. It Further, p-type second impurity regions 10a and 10b having an LDD structure are formed in the semiconductor layer 4 on the substrate except the gate electrode 2.
【００１１】前記構造を有する本発明の薄膜トランジス
タの製造方法を説明すると、次の通りである。図３
（ａ）のように絶縁基板１上にゲート電極２を形成し、
全面にわたってゲート絶縁膜３を形成する。この際、ゲ
ート電極２の厚さ（高さ）がチャンネル領域の長さを決
めるので、所望のチャンネル長さを考慮してゲート電極
２の厚さを調節する。The method of manufacturing the thin film transistor of the present invention having the above structure will be described as follows. FIG.
As shown in (a), the gate electrode 2 is formed on the insulating substrate 1,
A gate insulating film 3 is formed on the entire surface. At this time, since the thickness (height) of the gate electrode 2 determines the length of the channel region, the thickness of the gate electrode 2 is adjusted in consideration of the desired channel length.
【００１２】図３（ｂ）のように全面にわたってポリシ
リコン等の半導体層４を蒸着する。図３（ｃ）のように
前記半導体層４に低濃度のソース／ドレーン不純物イオ
ン（ｐ-）を注入する。ここで、低濃度のソース／ドレ
ーン不純物イオン（ｐ-）としてＢＦ2 イオンを使用す
る場合、５〜５０ＫｅＶエネルギーにより濃度１×１０
10〜１×１０12程度のイオンを注入する。これにより、
ゲート電極２の上側、及びゲート電極２が形成されてい
ない絶縁基板１の上側の半導体層４にのみ低濃度のソー
ス／ドレーン不純物イオンが注入され、ゲート電極２の
両側に沿う半導体層４には低濃度のソース／ドレーン不
純物イオンが注入されない。As shown in FIG. 3B, a semiconductor layer 4 such as polysilicon is vapor-deposited on the entire surface. As shown in FIG. 3C, low concentration source / drain impurity ions (p − ) are implanted into the semiconductor layer 4. Here, when BF 2 ions are used as the low concentration source / drain impurity ions (p − ), the concentration is 1 × 10 5 by 5 to 50 KeV energy.
Ions of about 10 to 1 × 10 12 are implanted. This allows
Low concentration source / drain impurity ions are implanted only into the semiconductor layer 4 above the gate electrode 2 and above the insulating substrate 1 where the gate electrode 2 is not formed, and the semiconductor layer 4 along both sides of the gate electrode 2 is implanted. Low concentration source / drain impurity ions are not implanted.
【００１３】図３（ｄ）のように、酸化膜などの絶縁膜
を厚く蒸着し、それを異方性エッチングして絶縁膜の側
壁７を形成した後、前記絶縁膜の側壁７をマスクとして
高濃度のソース／ドレーンイオン（ｐ+） を注入する。
それによってゲート電極２の両側に沿う半導体層４にチ
ャンネル領域１１が形成され、ゲート電極２の上部と側
壁７の両外側の絶縁基板１上の半導体層４に高濃度のｐ
型第１・第２不純物領域９，１０ａ，１０ｂが形成さ
れ、半導体層４の側壁７の下側の部分に低濃度領域（ｐ
-） が形成された薄膜トランジスタを完成する。ここ
で、高濃度のソース／ドレーン不純物イオンとしてＢＦ
2 を使用する場合、５〜５０ＫｅＶのエネルギーにより
濃度１×１０13以上（１×１０13〜１×１０16）のイオ
ンを注入する。そして、前記工程によって不純物領域を
形成すると、ドレーン領域はゲート電極２とオフセット
になりながらＬＤＤ構造を有することになる。As shown in FIG. 3D, an insulating film such as an oxide film is vapor-deposited thickly and anisotropically etched to form a sidewall 7 of the insulating film, and then the sidewall 7 of the insulating film is used as a mask. Implant a high concentration of source / drain ions (p + ).
As a result, the channel region 11 is formed in the semiconductor layer 4 along both sides of the gate electrode 2, and the semiconductor layer 4 on the insulating substrate 1 on both sides of the upper portion of the gate electrode 2 and the side wall 7 has a high concentration of p.
The first and second type impurity regions 9, 10a and 10b are formed, and the low concentration region (p
- ) Is completed to complete the thin film transistor. Here, BF is used as high-concentration source / drain impurity ions.
When 2 is used, ions with a concentration of 1 × 10 13 or more (1 × 10 13 to 1 × 10 16 ) are implanted with an energy of 5 to 50 KeV. When the impurity region is formed by the above process, the drain region has an LDD structure while being offset from the gate electrode 2.
【００１４】[0014]
【発明の効果】以上説明したように、本発明の薄膜トラ
ンジスタの構造及びその製造方法には、下記の効果があ
る。 一．マスク工程無しに自己整合によってＬＤＤ構造のド
レーン領域を形成することができるので、工程の変化に
関係なく薄膜トランジスタの一定の特性を得ることがで
きる。 二．マスク工程が不必要であり、それによる除去工程も
不必要であるので、工程が簡単で歩留まりが増加する。 三．チャンネルが垂直形に形成されるのでデザインルー
ルが縮小しても、一定長さのチャンネルを有する薄膜ト
ランジスタを確保することができる。As described above, the structure of the thin film transistor and the manufacturing method thereof according to the present invention have the following effects. one. Since the drain region having the LDD structure can be formed by self-alignment without a mask process, certain characteristics of the thin film transistor can be obtained regardless of changes in the process. two. Since the mask process is unnecessary and the removal process by it is also unnecessary, the process is simple and the yield is increased. three. Since the channel is formed in a vertical shape, a thin film transistor having a channel of a certain length can be secured even if the design rule is reduced.
【図１】 従来の薄膜トランジスタの工程断面図であ
る。FIG. 1 is a process sectional view of a conventional thin film transistor.
【図２】 本発明の薄膜トランジスタの構造斜視図であ
る。FIG. 2 is a structural perspective view of a thin film transistor of the present invention.
【図３】 本発明の薄膜トランジスタの工程断面図であ
る。3A to 3D are process cross-sectional views of a thin film transistor of the invention.
１…絶縁基板、２…ゲート電極、３…ゲート絶縁膜、４
…半導体層、７…側壁、９，１０ａ，１０ｂ…不純物領
域、１１…チャンネル領域。1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4
... semiconductor layer, 7 ... sidewall, 9, 10a, 10b ... impurity region, 11 ... channel region.
Claims (8)
と、 前記ゲート絶縁膜上に形成される半導体層と、 前記半導体層の前記ゲート電極の両側面に沿う部分に形
成されるチャンネル領域と、 前記ゲート電極上側の半導体層に形成される高濃度の第
１導電型第１不純物領域と、 前記ゲート電極部分以外の絶縁基板上の半導体層に形成
されるＬＤＤ構造の第１導電型第２不純物領域と、を有
することを特徴とする薄膜トランジスタの構造。1. An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode and the insulating substrate, and a semiconductor layer formed on the gate insulating film. A channel region formed in a portion of the semiconductor layer along both side surfaces of the gate electrode, a high-concentration first conductivity type first impurity region formed in the semiconductor layer above the gate electrode, other than the gate electrode portion And a second impurity region of the first conductivity type having an LDD structure formed in the semiconductor layer on the insulating substrate.
ットになることを特徴とする請求項１記載の薄膜トラン
ジスタの構造。2. The structure of the thin film transistor according to claim 1, wherein the second impurity region is offset from the gate electrode.
にわたってゲート絶縁膜を形成する工程と、 前記ゲート絶縁膜上に半導体層を形成する工程と、 前記半導体層に垂直に低濃度のソース／ドレーン不純物
イオンを注入する工程と、 前記ゲート電極の両側の半導体層の側壁に絶縁膜の側壁
を形成する工程と、 前記絶縁膜の側壁をマスクとして用いて半導体層に高濃
度のソース／ドレーンイオンを注入する工程と、 を含んでなることを特徴とする薄膜トランジスタの製造
方法。3. A step of forming a gate electrode on an insulating substrate and forming a gate insulating film over the entire surface, a step of forming a semiconductor layer on the gate insulating film, and a low-concentration source perpendicular to the semiconductor layer. / Drain Impurity ion implantation, forming sidewalls of insulating film on sidewalls of the semiconductor layer on both sides of the gate electrode, and using high-concentration source / drain on the semiconductor layer using the sidewalls of the insulating film as a mask A method of manufacturing a thin film transistor, comprising: a step of implanting ions.
長さに比例することを特徴とする請求項３記載の薄膜ト
ランジスタの製造方法。4. The method of manufacturing a thin film transistor according to claim 3, wherein the thickness of the gate electrode is proportional to a desired channel length.
注入は、ドーパントとしてＢＦ2 イオンを使用する場
合、５〜５０ＫｅＶエネルギーにより濃度１×１０10〜
１×１０12位のイオンを注入することを特徴とする請求
項３記載の薄膜トランジスタの製造方法。5. A low concentration source / drain impurity ion implantation is performed at a concentration of 1 × 10 10 to 5 to 50 KeV energy when BF 2 ions are used as a dopant.
The method of manufacturing a thin film transistor according to claim 3, wherein ions at 1 × 10 12 positions are implanted.
注入は、ドーパントとしてＢＦ2 を使用する場合、５〜
５０ＫｅＶのエネルギーにより濃度１×１０13以上のイ
オンを注入することを特徴とする請求項３記載の薄膜ト
ランジスタの製造方法。6. High-concentration source / drain impurity ion implantation is performed when BF 2 is used as a dopant.
4. The method of manufacturing a thin film transistor according to claim 3, wherein ions having a concentration of 1 × 10 13 or more are implanted with an energy of 50 KeV.
とを特徴とする請求項３記載の薄膜トランジスタの製造
方法。7. The method of manufacturing a thin film transistor according to claim 3, wherein the semiconductor layer is made of polysilicon.
を特徴とする請求項３記載の薄膜トランジスタの製造方
法。8. The method of manufacturing a thin film transistor according to claim 3, wherein the sidewall of the insulating film is formed of an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32978794A JPH08162643A (en) | 1994-12-06 | 1994-12-06 | Structure of thin-film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32978794A JPH08162643A (en) | 1994-12-06 | 1994-12-06 | Structure of thin-film transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08162643A true JPH08162643A (en) | 1996-06-21 |
Family
ID=18225262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32978794A Pending JPH08162643A (en) | 1994-12-06 | 1994-12-06 | Structure of thin-film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08162643A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006511091A (en) * | 2002-12-19 | 2006-03-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | FinFET SRAM Cell Using Inverted FinFET Thin Film Transistor |
| WO2015134083A1 (en) * | 2014-03-06 | 2015-09-11 | Eastman Kodak Company | Vtfts including offset electrodes |
-
1994
- 1994-12-06 JP JP32978794A patent/JPH08162643A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006511091A (en) * | 2002-12-19 | 2006-03-30 | インターナショナル・ビジネス・マシーンズ・コーポレーション | FinFET SRAM Cell Using Inverted FinFET Thin Film Transistor |
| WO2015134083A1 (en) * | 2014-03-06 | 2015-09-11 | Eastman Kodak Company | Vtfts including offset electrodes |
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