JPH08162643A - Structure of thin film transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To reduce the number of steps and improve the yield and characteristics of thin film transistors. [Structure] A semiconductor layer 4 formed on a gate insulating film,
A channel region 11 formed in the semiconductor layer on both sides of the gate electrode, a high-concentration first conductivity type first impurity region formed in the semiconductor layer above the gate electrode, and on the insulating substrate excluding the gate electrode A step of forming a gate electrode on an insulating substrate, including a second impurity region of the first conductivity type having an LDD structure formed in a semiconductor layer, and forming a gate insulating film over the entire surface, and a semiconductor on the gate insulating film. A step of forming a layer, a step of implanting low concentration source / drain impurity ions perpendicularly to the semiconductor layer, a step of forming a side wall 7 of an insulating film on the side wall of the semiconductor layer on both sides of the gate electrode, A step of implanting high concentration source / drain ions into the semiconductor layer using the sidewalls as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor of a semiconductor device, and more particularly to a structure of a thin film transistor suitable for a memory cell of SRAM and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, a p-type thin film transistor is used in place of a load resistor in an SRAM element of 1M class or higher, and an N-type thin film transistor is widely used as a switching element for switching an image data signal of each pixel region in a liquid crystal display element. Has been.

In order to manufacture a high quality SRAM, the off current and the on current of the p-type thin film transistor must be reduced, which can reduce the power consumption of the SRAM cell and the storage characteristics. Can be improved.

Recently, studies have been actively conducted to improve the on / off current ratio based on the above-mentioned principle. A conventional method of manufacturing a thin film transistor for improving the on / off current ratio will be described with reference to the drawings.

FIG. 1 is a process sectional view of a conventional thin film transistor. In the conventional method of manufacturing a thin film transistor, a gate electrode 2 is formed on an insulating substrate 1 and a gate insulating film 3 is formed on the entire surface as shown in FIG. As shown in FIG. 1B, an intrinsic semiconductor layer 4 such as polysilicon is vapor-deposited thereon. As shown in FIG. 1C, channel ions (n-type ions) are implanted into the intrinsic semiconductor layer 4. As shown in FIG. 1D, a first oxide film 5 is deposited on the entire surface, and the first oxide film 5 is patterned by a photo-etching process so that it remains only in a channel region above the gate electrode 2. Then, the patterning is performed. Using the first oxide film 5 as a mask, the intrinsic semiconductor layer 4 has a low concentration of source / drain ions (p
^- ) Is implanted to form a low concentration source / drain impurity region 6
To form. As shown in FIG. 1 (e), the second
After thickly depositing an oxide film and anisotropically etching the second oxide film to form a sidewall 7 of the second oxide film, the sidewalls 7 of the first oxide film 5 and the second oxide film are used as a mask. Implant a high concentration of source / drain ions (p ⁺ ). Figure 1 (f)
As described above, the sidewalls 7 of the first oxide film 5 and the second oxide film are removed to complete a thin film transistor having an LDD structure.

[0006]

However, such a conventional thin film transistor has the following problems. That is, since a separate mask process and a process for removing the mask are required to form the source / drain regions of the LDD structure, the process is complicated, and the number of processes is increased and the yield is increased. And the characteristics of the thin film transistor are degraded.

The present invention is intended to solve the above problems, and its object is to reduce the number of steps and improve the yield and characteristics of thin film transistors.

[0008]

In order to achieve the above object, the structure of a thin film transistor of the present invention comprises an insulating substrate,
A gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode and the insulating substrate, a semiconductor layer formed on the gate insulating film, and both sides of the gate electrode of the semiconductor layer. A channel region formed in a portion along the surface, a high-concentration first conductivity type first impurity region formed in the semiconductor layer above the gate electrode, and a semiconductor layer on the insulating substrate other than the gate electrode portion L formed on
And a first conductivity type second impurity region having a DD structure. A method of manufacturing a thin film transistor of the present invention comprises a step of forming a gate electrode on an insulating substrate and forming a gate insulating film over the entire surface, a step of forming a semiconductor layer on the gate insulating film, and a step perpendicular to the semiconductor layer. Implanting low concentration source / drain impurity ions, forming sidewalls of an insulating film on sidewalls of the semiconductor layer on both sides of the gate electrode, and using high concentration on the semiconductor layer using the sidewalls of the insulating film as a mask And the step of implanting source / drain ions of.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the thin film transistor of the present invention and the manufacturing method thereof will be described with reference to the drawings. 2 is a structural perspective view of the thin film transistor of the present invention, and FIG. 3 is a process sectional view of the thin film transistor of the present invention. In the structure of the thin film transistor of the present invention, as shown in FIG. 2, the gate electrode 2 is formed on the insulating substrate 1, and the gate insulating film 3 such as an oxide film is formed on the gate electrode 2 and the substrate.
The semiconductor layer 4 is formed thereon.

A channel region of the transistor is formed in a portion of the semiconductor layer 4 along both side surfaces of the gate electrode, and a high concentration p-type first impurity region 9 is formed in an upper portion of the gate electrode 2. It Further, p-type second impurity regions 10a and 10b having an LDD structure are formed in the semiconductor layer 4 on the substrate except the gate electrode 2.

The method of manufacturing the thin film transistor of the present invention having the above structure will be described as follows. FIG.
As shown in (a), the gate electrode 2 is formed on the insulating substrate 1,
A gate insulating film 3 is formed on the entire surface. At this time, since the thickness (height) of the gate electrode 2 determines the length of the channel region, the thickness of the gate electrode 2 is adjusted in consideration of the desired channel length.

As shown in FIG. 3B, a semiconductor layer 4 such as polysilicon is vapor-deposited on the entire surface. As shown in FIG. 3C, low concentration source / drain impurity ions (p ⁻ ) are implanted into the semiconductor layer 4. Here, when BF ₂ ions are used as the low concentration source / drain impurity ions (p ⁻ ), the concentration is 1 × 10 5 by 5 to 50 KeV energy.
Ions of about ¹⁰ to 1 × 10 ¹² are implanted. This allows
Low concentration source / drain impurity ions are implanted only into the semiconductor layer 4 above the gate electrode 2 and above the insulating substrate 1 where the gate electrode 2 is not formed, and the semiconductor layer 4 along both sides of the gate electrode 2 is implanted. Low concentration source / drain impurity ions are not implanted.

As shown in FIG. 3D, an insulating film such as an oxide film is vapor-deposited thickly and anisotropically etched to form a sidewall 7 of the insulating film, and then the sidewall 7 of the insulating film is used as a mask. Implant a high concentration of source / drain ions (p ⁺ ).
As a result, the channel region 11 is formed in the semiconductor layer 4 along both sides of the gate electrode 2, and the semiconductor layer 4 on the insulating substrate 1 on both sides of the upper portion of the gate electrode 2 and the side wall 7 has a high concentration of p.
The first and second type impurity regions 9, 10a and 10b are formed, and the low concentration region (p
^- ) Is completed to complete the thin film transistor. Here, BF is used as high-concentration source / drain impurity ions.
_{When 2} is used, ions with a concentration of 1 × 10 ¹³ or more (1 × 10 ¹³ to 1 × 10 ¹⁶ ) are implanted with an energy of 5 to 50 KeV. When the impurity region is formed by the above process, the drain region has an LDD structure while being offset from the gate electrode 2.

[0014]

As described above, the structure of the thin film transistor and the manufacturing method thereof according to the present invention have the following effects. one. Since the drain region having the LDD structure can be formed by self-alignment without a mask process, certain characteristics of the thin film transistor can be obtained regardless of changes in the process. two. Since the mask process is unnecessary and the removal process by it is also unnecessary, the process is simple and the yield is increased. three. Since the channel is formed in a vertical shape, a thin film transistor having a channel of a certain length can be secured even if the design rule is reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view of a conventional thin film transistor.

FIG. 2 is a structural perspective view of a thin film transistor of the present invention.

3A to 3D are process cross-sectional views of a thin film transistor of the invention.

[Explanation of symbols]

1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4
... semiconductor layer, 7 ... sidewall, 9, 10a, 10b ... impurity region, 11 ... channel region.

Claims (8)

[Claims] 1. An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode and the insulating substrate, and a semiconductor layer formed on the gate insulating film. A channel region formed in a portion of the semiconductor layer along both side surfaces of the gate electrode, a high-concentration first conductivity type first impurity region formed in the semiconductor layer above the gate electrode, other than the gate electrode portion And a second impurity region of the first conductivity type having an LDD structure formed in the semiconductor layer on the insulating substrate. 2. The structure of the thin film transistor according to claim 1, wherein the second impurity region is offset from the gate electrode. 3. A step of forming a gate electrode on an insulating substrate and forming a gate insulating film over the entire surface, a step of forming a semiconductor layer on the gate insulating film, and a low-concentration source perpendicular to the semiconductor layer. / Drain Impurity ion implantation, forming sidewalls of insulating film on sidewalls of the semiconductor layer on both sides of the gate electrode, and using high-concentration source / drain on the semiconductor layer using the sidewalls of the insulating film as a mask A method of manufacturing a thin film transistor, comprising: a step of implanting ions. 4. The method of manufacturing a thin film transistor according to claim 3, wherein the thickness of the gate electrode is proportional to a desired channel length. 5. A low concentration source / drain impurity ion implantation is performed at a concentration of 1 × 10 ¹⁰ to ⁵ to 50 KeV energy when BF ₂ ions are used as a dopant.
The method of manufacturing a thin film transistor according to claim 3, wherein ions at 1 × 10 ¹² positions are implanted. 6. High-concentration source / drain impurity ion implantation is performed when BF ₂ is used as a dopant.
4. The method of manufacturing a thin film transistor according to claim 3, wherein ions having a concentration of 1 × 10 ¹³ or more are implanted with an energy of 50 KeV. 7. The method of manufacturing a thin film transistor according to claim 3, wherein the semiconductor layer is made of polysilicon. 8. The method of manufacturing a thin film transistor according to claim 3, wherein the sidewall of the insulating film is formed of an oxide film.