JPH08162627A - Charge-coupled device and solid-state image pickup device - Google Patents

Abstract

PURPOSE: To provide a charge-coupled device wherein charges are prevented from being left untaken in transfer due to the height of a barrier during two- phase drive, and high-speed drive is thus possible. CONSTITUTION: An n-type CCD buried channel 2 is formed in the surface layer of a p-type silicon substrate 1 in the direction of signal charge transfer. Transfer gates 10 (11, 12, 13) are formed on the channel 2, and storage regions 2 and barrier regions 3, different in impurity concentration from one another, are formed under the gates 10, one each. In the resultant charge-coupled device, signal charges are transferred by driving the transfer gates 10 using a two-phase clock ϕ1, ϕ2. The potential of the respective storage regions 2 and barrier regions 3 is set so that the difference in potential between the storage regions 2 and the barrier regions 3 is 0.5V when 0V is applied to the transfer gates 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a charge coupled device, and more particularly to a two-phase drive type charge coupled device and a solid-state image pickup device using the same.

[0002]

2. Description of the Related Art In recent years, solid-state image pickup devices have been used as image pickup devices such as video cameras and electronic still cameras. This solid-state imaging device converts input light into signal charges and stores them in a photoelectric conversion storage region, and transfers the accumulated signal charges to a horizontal transfer charge coupled device (horizontal CCD) by a vertical transfer charge coupled device (vertical CCD). Then, the horizontal CCD transfers the image signal to the on-chip amplifier and outputs the image signal.

The horizontal CCD is usually a two-phase driven CC.
D is used. In a two-phase driving CCD, storage regions for storing signal charges and barrier regions having a lower channel potential than the storage regions are alternately formed in the buried channel. One storage region and a barrier region adjacent thereto in the opposite direction to the transfer direction form one pair, and the same drive voltage is applied to the transfer gate above this pair. Therefore, it is possible to transfer the signal charges only in the transfer direction by applying two types of opposite-phase driven pulses (two-phase pulses) every other pair.

In the prior art, in a two-phase driving horizontal CCD which is normally driven by 5V, the difference in channel potential between the storage region and the barrier region (barrier height) is about 2.0V which is about half of the driving voltage. I was doing. This is because the height of the barrier is increased to increase the transfer charge capacity per unit area of the horizontal CCD and reduce the area of the horizontal CCD.

FIG. 8 is a diagram showing a cross section in the transfer direction of a conventional two-phase drive CCD and a channel potential of a transfer channel. In the figure, 1 is a p-type silicon substrate, 2 is a buried n-type impurity layer, 3 is an n ⁻ -type impurity layer, 11, 12, 13
Indicates a transfer gate. In this example, the difference in channel potential between the storage region and the barrier region (barrier height) is set to 2.5V. Therefore, the transfer charge capacity per unit area of the CCD is large.

To transfer the signal charge in the two-phase driving CCD, the voltage φ1 applied to the transfer gate 11 at the next stage is increased,
The voltage φ2 applied to the transfer gate 12 under which the signal charges are accumulated is lowered. In general, the voltage applied to the transfer gate gradually changes with time due to the delay of the wiring on the way. The channel potential under the transfer gate also gradually changes with time as the applied voltage changes. Then, the transfer starts when the channel potential of the storage region under the transfer gate 11 becomes higher than the channel potential under the transfer gate 12. At this time, since the barrier height is as high as 2.5 V, it can be seen that it takes time to start the transfer. That is, when the driving frequency is increased, there is a problem in that the transfer cannot be completed completely and the remaining portion is left behind.

The state of transfer of signal charges in the two-phase driving CCD will be described below. FIG. 9 is a diagram schematically showing changes in channel potential and movement of signal charges when transferring signal charges in the two-phase drive CCD. φ1 is “L”
The case where the signal charges are transferred to the left by changing the level from the “H” level to φ2 from the “H” level to the “L” level is shown. .

FIG. 1A is a diagram showing a state in which φ1 is at the “L” level, φ2 is at the “H” level, and signal charges are accumulated under the transfer gate 12. Next-stage transfer gate 11
When the signal charge is transferred to the lower side, φ1 is gradually changed to the “H” level and φ2 is changed to the “L” level.

FIG. 3B is a diagram showing a state when φ1 and φ2 are exactly equal. Since the channel potential of the storage region below the transfer gate 12 is lower than the channel potential of the barrier region below the transfer gate 11, no transfer has occurred yet.

In (c), φ1 is further set to the “H” level, φ
2 is a diagram showing a state in which the channel potential of the storage region below the transfer gate 12 and the channel potential of the barrier region below the transfer gate 11 become equal by further setting 2 to the “L” level. At this time, the transfer of the signal charge (electrons) starts, and the signal charge starts moving to the accumulation region below the transfer gate 11.

In (d), φ1 is completely at “H” level, φ
FIG. 2 is a diagram showing a state when 2 has become “L” level and the transfer is completed. Generally, in a solid-state image pickup device, a better reproduced image can be obtained as the number of pixels is increased. For example, HDTV
The number of pixels in the solid-state image pickup device for use is about 2 million. When the number of pixels of the solid-state imaging device is increased in this way, an increase in data rate becomes a problem. The increase in data rate is
It is necessary to increase the driving frequency of the CCD inside the solid-state imaging device. For example, the driving frequency of the horizontal CCD of the solid-state imaging device for HDTV is about 74 MHz when the horizontal CCD does not have a double channel structure. When the drive frequency is high as described above, the transfer efficiency is deteriorated due to the fact that the signal charges cannot be completely transferred and are left behind.

In the above description, the case where the signal charge amount is small has been described, but in general, when the signal charge amount is small, the transfer efficiency of the CCD is easily deteriorated, and it is at this time that the performance of the CCD is determined. Is the transfer efficiency. Therefore, it is possible to discuss the transfer efficiency of the CCD when discussing when the signal charge amount is small. However, the present invention is effective even when the signal charge amount is large.

Further, in the above, for simplicity of explanation, "the channel potential of the storage region under the transfer gate 11 is
The transfer starts when it becomes higher than the channel potential under the transfer gate 12. Strictly speaking, the voltage difference ΔV that suppresses the potential pockets increases and the transfer starts after the potential pockets existing between the transfer gates disappear. However, since it does not relate to the essence of the present invention, the following will be similarly described.

Further, in the above description, the modulation coefficient with respect to the voltage applied to the transfer gate of the channel potential is set to 1 for the sake of simplicity of description. Actually, the channel potential changes by α × V with respect to the change V of the applied voltage (α
Is the modulation coefficient). The modulation coefficient has a value of about 0.8 to 0.9, but for simplicity, the modulation coefficient will be similarly described below as 1.

[0015]

As described above, in the conventional two-phase driving CCD, the height of the barrier in the transfer direction (potential difference between the storage region and the barrier region) is generally as large as about 2.5 V, and this barrier is large. Because of the transfer takes some time. Further, when the driving frequency is increased, there is a problem that the electric charges cannot be completely transferred and the electric charges are left behind.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to prevent charge transfer from remaining due to the height of a barrier in two-phase driving and to realize high-speed driving. An object of the present invention is to provide a charge-coupled device and a solid-state imaging device using the same.

[0017]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention (claim 1), transfer gates are arranged in one direction on a semiconductor substrate, these transfer gates are driven by a two-phase clock, and a storage region and a barrier region are formed under each gate. In a charge-coupled device that transfers signal charges by applying a voltage of 0 V to the transfer gate, the potential difference between the storage region and the barrier region is 1 V or less.
The feature is that the potential of each region is set.

The preferred embodiments of the present invention are as follows. (1) One accumulation region and one barrier region having different impurity concentrations are formed under the transfer gate. (2) The potential difference between the accumulation region and the barrier region is caused by the difference in the film thickness of the gate insulating film. (3) The transfer gate is formed of a single conductive layer.

Further, according to the present invention (claim 5), a plurality of photoelectric conversion storage regions arranged two-dimensionally on a semiconductor substrate,
A plurality of vertical transfer charge-coupled devices that vertically transfer the signal charges read from the photoelectric conversion storage region, and a horizontal transfer charge-coupled device that receives the signals of these vertical transfer charge-coupled devices and horizontally transfers them. In the solid-state image pickup device including: the horizontal transfer charge coupled device, which is driven by two-phase clocks to form a storage region and a barrier region under each transfer gate, and the potential of the storage region and the barrier region are It is characterized in that the difference from the potential is set to 1 V or less.

[0020]

According to the present invention, when the signal charge is transferred to the next stage, the height of the barrier under the transfer gate of the next stage is as low as 1 V or less, so that when the voltage applied to the transfer gate is changed, The transfer of signal charge starts quickly. Therefore, the transfer of the signal charges can be completed quickly. Therefore, the driving frequency of the two-phase driving CCD can be increased without deteriorating the transfer efficiency. More specifically, by setting the barrier height to 1 V or less, no decrease in transfer efficiency is observed even at a drive frequency of 74 MHz used in horizontal CCDs such as HDTV, and good transfer of signal charges is achieved. It has become possible.

In the present invention, since the height of the barrier is as low as 1 V or less, the transfer charge capacity per unit area is reduced. This is a problem in a case where a large number of CCDs are arranged in the image pickup area such as a vertical CCD, but it is easy to increase the area in a case where there are only one or two outside the image pickup area such as a horizontal CCD. As a result, a sufficient transfer charge capacity can be secured.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a cross section in the transfer direction of a two-phase driving CCD according to the first embodiment of the present invention and a potential of its transfer channel.

In FIG. 1, reference numeral 1 denotes a p-type silicon substrate, and a buried n-type impurity layer (buried channel) 2 is provided on the surface layer of the substrate 1 along the signal charge transfer direction. A plurality of transfer gates 10 (11, 12, 1) made of polysilicon are formed on the n-type buried channel 2 via a gate oxide film 4.
3) are arranged along the signal charge transfer direction. Under each transfer gate, an n ⁻ type impurity layer 3 serving as a barrier layer is provided in the front half of the transfer direction.

In the present embodiment, the difference between the channel potential of the storage region and the channel potential of the barrier region (barrier height) is determined by the method such as ion implantation in the n-type impurity diffusion layer 2 forming the buried channel. ,
It is made by forming the barrier region n ⁻ layer 3. The height of this barrier can be set according to the conditions of ion implantation, and is set to 0.5 V in this embodiment. The height of the barrier is defined by the condition when 0V is applied to the transfer gate. When the applied voltage becomes higher, the height of the barrier becomes slightly smaller than the above value due to the influence of the above-mentioned modulation coefficient α, but it can be regarded that they are substantially the same.

A specific example for forming the barrier will be described. The substrate 1 is boron (B) -doped silicon, and
The concentration was 3 × 10 ¹⁵ cm ^-3 . n-type buried channel 2
Is formed by doping phosphorus (P) and has a P peak concentration of 6
It was set to × 10 ¹⁶ cm ^-3 . At this time, the B peak concentration of the n ⁻ barrier layer 3 formed by ion implantation is 7 × 10 ¹⁵ cm
^A barrier height of 1 V could be obtained at ^-3 . n ^-
Lowering the B peak concentration of the barrier layer 3 results in a lower barrier height. By the way, the conventional n ^- barrier layer 3
B peak concentration was about 2 × 10 ¹⁶ cm ⁻³ .

The reason why the CCD of this embodiment starts transfer faster than the conventional example shown in FIG. 8 will be described with reference to FIG. In FIG. 2, the voltage φ2 applied to the transfer gate 12 under which the signal charges are accumulated is changed from "H" level (5V) to "L" level (0V), and the voltage is transferred to the transfer gate 11 of the next stage. It is a figure which shows the change of a channel potential when changing the applied voltage (phi) 1 from "L" level to "H" level. Even if the input waveform is a rectangular wave, the voltage applied to the transfer gate does not become a perfect rectangular wave because the waveform is usually blunted due to the parasitic capacitance in the wiring stage in the middle.
This becomes remarkable especially when the driving frequency is high. Here, for simplicity, it is described that the applied voltage changes linearly.

The channel potential below the transfer gate 11 and the channel potential below the transfer gate 12 in the conventional example are indicated by A and B, respectively. Similarly, the channel potential in the embodiment is indicated by C below the transfer gate 11 and D below the transfer gate 12.

In the conventional example, it is at time t3 that the channel potential A under the transfer gate of the next stage becomes higher than B due to the change of the voltage applied to the transfer gate. On the other hand, in this embodiment in which the barrier height is low, C becomes higher than D at time t2. That is, the transfer start of the signal charges is faster in this embodiment. Therefore, the transfer can be completed quickly. Especially when driving the CCD at 5V, 1V
The following barriers are sufficiently small compared to the drive voltage of 5V, so that the effect of this embodiment is large.

FIG. 3 is a diagram showing the results of measuring the drive frequency dependence of the transfer efficiency of the two-phase drive CCD. When the barrier height is 2V, the deterioration of the transfer efficiency in the high frequency region is more remarkable than when it is 1V, and the transfer efficiency is 100 at the driving frequency of 74 MHz used in the horizontal CCD of HDTV.
% Has not been achieved. However, when the barrier height is 1 V as in this embodiment, the transfer frequency is not deteriorated even at 74 MHz.

FIG. 4 is a diagram showing the relationship between the channel potential and the transfer efficiency at a drive frequency of 74 MHz. From this figure, the difference in channel potential is 1.2V.
It can be seen that the transfer efficiency drops sharply when the voltage exceeds 1.0 V, and almost 100% is obtained when the voltage is 1 V or less. Therefore, if the driving frequency is 74 MHz, it is possible to prevent the deterioration of the transfer efficiency by setting the channel potential difference to 1 V or less.

Further, in FIG. 3, the height of the barrier is 0.6.
When V is set, the transfer efficiency does not deteriorate even at 100 MHz. Therefore, considering the application to a higher driving frequency, it is desirable to set the height of the barrier to 0.6 V or less.

As described above, according to this embodiment, since the difference in channel potential between the storage region and the barrier region is as low as 0.5 V, the signal charge to the transfer gate is transferred to the next stage. The transfer starts faster when the applied voltage is changed. Therefore, the signal charges are transferred more quickly than in the conventional case. Therefore, there is an advantage that the transfer efficiency is less deteriorated even if the driving frequency is increased.

In the embodiment, the height of the barrier is lower than that of the conventional one, so that the transfer charge capacity per unit area is reduced, but this can be easily solved by increasing the channel width of the CCD. (Embodiment 2) FIG. 5 is a sectional view in the transfer direction of a two-phase CCD according to a second embodiment of the present invention and a diagram showing the potential of its transfer channel. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The height of the barrier in this embodiment is formed by selectively thinning the gate insulating film by a method such as reactive ion etching after forming the buried channel and the gate insulating film. The height of the barrier can be set by the difference in the film thickness of the gate insulating film between the storage region and the barrier region. In this embodiment, the difference between the channel potential of the storage region and the channel potential of the barrier region is 0.5V. Is done. Then, after forming the barrier region, the transfer gate is formed.

Specifically, the impurity concentrations of the substrate 11 and the buried channel layer 2 are the same as those in the first embodiment, and the film thickness of the gate oxide film 4a in the accumulation region is 90 nm and the film thickness of the gate oxide film 4b in the barrier region. When the thickness was set to 80 nm, a barrier height of 0.5 V could be obtained. The barrier height could be lowered as the thickness of the gate oxide film 4b in the barrier region was brought closer to 90 nm.

Also in this embodiment, since the height of the barrier is low, it is possible to increase the driving frequency as compared with the conventional example as in the first embodiment. The present embodiment has an advantage over the first embodiment that inline QC for aligning the barrier region and the transfer gate becomes easier. That is, in the first embodiment, since the barrier region is formed by ion implantation, it is impossible to form the alignment mark for the next lithography process. Therefore, it is difficult to measure how much the barrier region and the transfer gate are aligned.

On the other hand, in this embodiment, since the barrier region is formed by the method such as reactive ion etching, it is possible to form the alignment mark for the next lithography process. For this reason, it becomes easy to QC how much the barrier region and the transfer gate are misaligned.

Although the barrier region is formed by reactive ion etching in this embodiment, the gate insulating film in the barrier region is selectively peeled off and then oxidized again.
The gate insulating film may be formed using a means such as deposition to form a step. (Embodiment 3) FIG. 6 is a diagram showing a basic configuration of a solid-state image pickup device according to a third embodiment of the present invention.

A plurality of photodiodes (photoelectric conversion storage regions) 61 are two-dimensionally arranged and formed on a silicon substrate 60, and vertical CCDs 62 are provided between adjacent photodiodes 61.
Are arranged along the column direction. Vertical CCD
One horizontal CCD 63 is arranged at the end of 62.
The vertical CCD 62 is four-phase driven, and the horizontal CCD 63 is two-phase driven. The signal charges photoelectrically converted and accumulated in the photodiode 61 are read out to the vertical CCD 62 and transferred in the vertical direction, further transferred in the horizontal direction by the horizontal CCD 63, and output to the outside via the output amplifier 64. Has become.

Here, the horizontal CCD 63 is constructed as in the first or second embodiment described above. That is,
The horizontal CCD 63 is driven by two-phase clocks φH1 and φH2 to form a storage region and a barrier region under each transfer gate, and the difference between the potential of the storage region and the potential of the barrier region is 1 V or less. Is configured.

With such a configuration, it is possible to transfer the signal charges with high transfer efficiency without leaving the charges left in the horizontal CCD 63 even at the drive frequency of 74 MHz as in the HDTV. In addition, the horizontal CCD 63
Unlike the vertical CCD 62, only one CCD needs to be arranged. Therefore, even if the channel width of the CCD is increased, it has almost no effect on the increase of the chip area as a whole. Therefore,
Even if the height of the barrier is lowered, a sufficient transfer capacity can be secured.

The present invention is not limited to the above embodiments. Although the transfer gate is formed of a single layer in the embodiment, it may be formed of two layers of polysilicon as shown in FIG. Specifically, the transfer gates 71, 72, 73
Is composed of a first layer a and a second layer b, and one of the first layer a and the second layer b is a storage region and the other is a barrier region. Further, in order to form the storage region and the barrier region, at least one of the concentration of impurities under each gate and the thickness of the gate insulating film may be made different. In addition, various modifications can be made without departing from the scope of the present invention.

[0043]

As described above in detail, according to the present invention, when the signal charge is transferred to the next stage, the height of the barrier under the transfer gate of the next stage is as low as 1 V or less, so When the applied voltage of is changed, the transfer starts quickly. Therefore, the transfer of the signal charges can be completed quickly. Therefore, the two-phase drive CCD can be used without deterioration of transfer efficiency
Drive frequency can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing an element structure in a transfer direction and a transfer channel potential of a two-phase drive CCD according to a first embodiment.

FIG. 2 is a diagram showing a change in potential when a voltage applied to a transfer gate is changed.

FIG. 3 is a diagram showing the relationship between drive frequency and transfer efficiency when the height of the barrier is changed.

FIG. 4 is a diagram showing a relationship between channel potential and transfer efficiency at a drive frequency of 74 MHz.

FIG. 5 is a diagram showing an element structure in a transfer direction and a transfer channel potential of a two-phase drive CCD according to a second embodiment.

FIG. 6 is a diagram showing a basic configuration of a solid-state imaging device according to a third embodiment.

FIG. 7 is a diagram showing a modified example of the present invention.

FIG. 8 is a diagram showing a device structure in a transfer direction and a potential of a transfer channel of a conventional two-phase drive CCD.

FIG. 9 is a diagram schematically showing changes in channel potential and movement of signal charges when transferring signal charges in a conventional two-phase drive CCD.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... n-type impurity layer (buried channel) 3 ... n ^- type impurity layer 4 ... gate oxide film 11,12,13 ... transfer gate 60 ... silicon substrate 61 ... photodiode 62 ... vertical CCD 63 ... Horizontal CCD 64 ... Output amplifier

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/335 F

Claims (5)

[Claims] 1. Transfer gates are arranged along a direction on a semiconductor substrate, these transfer gates are driven by a two-phase clock, and a storage region and a barrier region are formed under each gate to transfer signal charges. In the charge coupled device, the potential difference between the storage region and the barrier region is set to 1 V or less when 0 V is applied to the transfer gate. 2. The charge coupled device according to claim 1, wherein one accumulation region and one barrier region having different impurity concentrations are formed under the transfer gate. 3. The charge-coupled device according to claim 1, wherein the potential difference between the accumulation region and the barrier region is caused by the difference in film thickness of the gate insulating film under the transfer gate. 4. The charge coupled device according to claim 1, wherein the transfer gate is formed of a single conductive layer. 5. A plurality of photoelectric conversion storage regions arranged two-dimensionally on a semiconductor substrate, and a plurality of vertical transfer charge coupled devices for vertically transferring signal charges read from the photoelectric conversion storage regions. And a horizontal transfer charge-coupled device that receives signals from these vertical transfer charge-coupled devices and horizontally transfers the signals, the horizontal transfer charge-coupled devices are driven by two-phase clocks to transfer each transfer. A solid-state imaging device for forming a storage region and a barrier region under a gate, wherein a difference between the potential of the storage region and the potential of the barrier region is set to 1 V or less.