JPH08161897A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To shorten a test time by making the writing of the same data possible in both of a data bit and a redundant bit and by respectively executing a burn-in test and a high temp. preservation test one time in a semiconductor memory having the redundant bit for correcting an error. CONSTITUTION: This memory is constituted of an address buffer part 1, a column decoder part 2, a row decoder part 3, a memory part 4, a reading and writing circuit part 5, an error correcting circuit part 6 and a control part 7 and is provided with a test writing mode executing only the erasing operation of the memory part 4. In this constitution, it is made possible that bits of both of the data bit and the redundant bit are rewritten into states of the same data by executing a test writing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having redundant bits in addition to data bits.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the structure of a conventional semiconductor memory device. This semiconductor memory device is shown in FIG.
As shown in, the address A ₀ ... A _N input from the outside
To a column address and a row address, and outputs the converted data, a column address buffer unit 2 and a row address buffer unit 3 to which the column address and the row address output from the address decoder unit 1 are input, and a data bit. And a memory section 4 having redundant bits and having an access position designated by a column address and a row address provided from the column address buffer section 2 and the row address buffer section 3, respectively.
And a read / write circuit unit 5 connected to the memory unit 4 via the row address buffer unit 3 for reading data from the memory unit 4 and writing data to the memory unit 4, and a read / write circuit unit 5 A redundant bit is added to the data D ₀ ... D _M connected to the outside and supplied to the read / write circuit unit 5 and a redundant bit for the data supplied from the read / write circuit unit 5. An error correction circuit unit 6 for performing error correction using the output and outputting to the outside, and an address decoder unit 1.
A read / write circuit section 5 and an error correction circuit section 6 and a control section 7 for giving control signals for various modes such as reading and writing.

The column address buffer unit 2 has a function of selectively applying a high voltage to the word line corresponding to the column address given from the address decoder unit 1. The row address buffer unit 3 also has a function of selecting a bit line corresponding to the row address given from the address decoder unit 1. The operation of the semiconductor memory device configured as above will be described. The control section 7 outputs control signals C1, C2, C3 in accordance with a signal IN of a condition such as an instruction code or terminal setting. And
The control unit 7 supplies the control signals C1, C2, and C3 to the address decoder unit 1, the read / write circuit unit 5, and the error correction circuit unit 6, respectively, whereby operations such as data writing and reading are executed.

The operation mode of the semiconductor memory device is as follows.
Read mode, write mode, write enable mode (write mode cannot be executed unless this instruction is executed), analysis test mode (direct memory data is viewed), analysis data read mode (read data before error correction) ), A redundant bit reading mode for analysis (reading of redundant bits before error correction), etc., and the operation mode is selected according to a signal IN input from the outside.

Now, the control signals C1, C2 and C3 will be described. The control signal C1 supplied from the control unit 7 to the address decoder unit 1 is called an address decoder control signal and determines whether to transmit the column address and the row address to the column address buffer unit 2 and the row address buffer unit 3. Play a role in. The column address and the row address are transmitted to the column address buffer unit 2 and the row address buffer unit 3 at the time of reading and writing, and stopped at the time of stop. By the way, when stopped, all addresses are selected.

The control signal C2 supplied from the control unit 7 to the read / write unit 5 is called a read / write control signal, and controls the operation of the read / write unit 5 to read and write data. Play a role of The control signal C3 supplied from the control unit 7 to the error correction circuit unit 6 is called an error correction control signal and is a signal for switching the input / output of read / write data.

The signal I input to the control unit 7
N is a mode signal from the outside, and is a command signal from the outside such as a read command, a write command, a write permission command, and a test mode command. The signal IN is, for example, 8-bit serial data, and its detection is made up of a group of flip-flops that perform serial-parallel conversion, a group of MOS transistors that logically processes the outputs of these flip-flop groups, and the like.

Next, the write operation and the read operation will be described. The write operation is as follows. When a write command is supplied to the control unit 7 from the outside as the signal IN, the address decoder unit 1 converts the addresses A ₀ ... A _N into column addresses and row addresses by the control signal C1 and converts them into the column address buffer unit 2
To the row address buffer unit 3, and as a result, one memory cell in the memory unit 4 is selected by the column address and the row address output from the column address buffer unit 2 and the row address buffer unit 3. Then, the error correction circuit unit 6 enters a write mode (input mode) by the control signal C3, forms redundant bits for performing error correction from the input data D ₀ ... D _M , and the redundant bits of the data bits and the redundant bits are formed. Both are supplied to the read / write circuit unit 5. The control signal C2 causes the read / write circuit unit 5 to write data by applying a high voltage to a required bit of the selected memory cell via the row address buffer unit 3.

The read operation is as follows. When a read command is supplied to the control unit 7 as a signal IN from the outside, the address decoder unit 1 transmits the column address and the row address to the column address buffer unit 2 and the row address buffer unit 3 by the control signal C1. The control signal C2 controls the read circuit (sense amplifier circuit) of the read / write circuit unit 5 to supply data to the error correction circuit unit 6. The error correction circuit unit 6 is set to the read mode (output mode) by the control signal C3,
Performs error correction and outputs the data to the outside.

[0010]

In the semiconductor memory device as described above, in order to guarantee its reliability, tests such as a burn-in test and a high temperature storage test are conducted. When performing a burn-in test or a high temperature storage test, it is necessary to set the data in the memory unit to the state of "0" or "1". However, in the case of a semiconductor memory device having an error correction function,
Since the redundant bits are uniquely formed from the data bits, even if the same data (all “1” data or all “0” data) is input, the redundant bits cannot be made the same data.

As described above, it is necessary to set the memory data to the state of "0" or "1" in the burn-in test or the high temperature storage test, but all the bits including the data bit and the redundant bit are made the same data. Since it is impossible to do so, the data bit and the redundant bit are separately set to the state of “1” or “0”, and the burn-in test,
It is necessary to perform a high temperature storage test, which increases the inspection time.

An object of the present invention is to provide a semiconductor memory device capable of shortening the inspection time when performing a burn-in test, a high temperature storage test and the like.

[0013]

According to another aspect of the present invention, there is provided a semiconductor memory device having an address decoder section for converting an externally input address into a column address and a row address and outputting the column address and the row address, and a data bit and a redundant bit. A memory part whose access position is specified by a column address and a row address, a read / write circuit part for reading data from the memory part and writing data to the memory part, and redundant to externally input data An error correction circuit unit that adds a bit and supplies it to the read / write circuit unit, and also performs error correction on the data supplied from the read / write circuit unit using a redundant bit and outputs it to the outside, and an address decoder Read and write to the read / write circuit and error correction circuit And a test mode select circuit unit that detects the test write command signal supplied from the outside and causes the control unit to select the test write mode. When the test write mode is selected, the control unit gives a control signal to the read / write circuit unit to perform only the erase operation, and the read / write circuit unit erases both the data bit and the redundant bit of the memory unit. To do.

According to another aspect of the semiconductor memory device of the present invention, an address decoder unit for converting an address inputted from the outside into a column address and a row address and outputting the column address and a row address, and having a data bit and a redundant bit are provided by the column address and the row address. A memory part whose access position is specified, a read / write circuit part that reads data from the memory part and writes data to the memory part, and a redundant bit is added to data input from the outside to read An error correction circuit unit that supplies the data to the write circuit unit and performs error correction on the data supplied from the read / write circuit unit using a redundant bit and outputs the data to the outside, an address decoder unit, and a read / write circuit Modes such as reading and writing in the memory section and error correction circuit section Corresponding to data bit and redundant bit, a control section that gives a control signal, a test mode select circuit section that is built in the control section and detects an externally supplied test write command signal that causes the control section to select the test write mode. And a data setting circuit section that can arbitrarily set data, regardless of the output of the error correction circuit section by giving a control signal for activation from the control section to the data setting circuit section when the test write mode is selected. The data setting circuit section gives arbitrary data to the read / write circuit section, and the control section gives a control signal to the read / write circuit section to perform the erase operation and the write operation. Data setting circuit for both bits and redundant bits Characterized in that so as to write the data.

A semiconductor memory device according to claim 3 is the semiconductor memory device according to claim 1 or 2, wherein
An address select circuit section that can select all addresses at the same time is provided, and when the test write mode is selected, a control signal for activation is given from the control section to the address select circuit section so that the address select circuit section can control the output address of the address decoder section. It is characterized in that all addresses in the memory section are simultaneously selected.

[0016]

According to the structure of claim 1, both the data bit and the redundant bit in the memory section are erased, and as a result, the same data is written in both the data bit and the redundant bit in the memory section. It will be. Therefore,
The burn-in test and the high temperature storage test can be simultaneously performed on all the bits of the memory section, and the inspection time can be shortened.

According to the structure of claim 2, arbitrary data is given from the data setting circuit section to the read / write circuit section when the test write mode is selected, and the erase / write operation is performed to the read / write circuit section. Thus, it is possible to write arbitrary data given from the data setting circuit unit to both the data bit and the redundant bit of the memory unit regardless of the output of the error correction circuit unit. Therefore, if all "1" or all "0" data is set in the data setting circuit section, the same data can be written in both the data bit and the redundant bit of the memory section. Therefore, it becomes possible to simultaneously perform a burn-in test and a high temperature storage test on all bits of the memory section.
The inspection time can be shortened. At this time, the data to be written in the memory unit can be set to any "1" or all "0", and the accuracy of the inspection can be improved by performing the burn-in test and the high temperature storage test with the data of both. .

According to the third aspect of the invention, all addresses of the memory section are simultaneously selected by the address select circuit section regardless of the output address of the address decoder section, and all the data bits and the redundant bits are combined. The bits can be collectively rewritten to the same data. Therefore, the time required to make the data bits and redundant bits of all addresses in the memory unit the same can be shortened, and the inspection time when performing a burn-in test or a high temperature storage test can be further shortened.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of a semiconductor memory device according to the first embodiment of the present invention. This semiconductor memory device, as shown in FIG. 1, includes a test mode select circuit unit that detects a test write command signal which is built in the control unit 7 and is externally supplied as a signal IN and causes the control unit 7 to select a test write mode. 7a is added, and when the test write mode is selected, the control section 7 gives a control signal C2 to the read / write circuit section 5 to perform only an erase operation, and the read / write circuit section 5 provides both the data bit and the redundant bit of the memory section 4. Is to be erased. Other configurations are similar to those of the conventional example shown in FIG.

In this semiconductor memory device, the control
The command code or terminal setting condition is externally sent to the part 7.
When the test write command is supplied as the signal IN, the test
Mode select circuit section 7a detects a test write command.
Control unit 7 is in the test writing mode.
Control signals C1, C2, C3 corresponding to the mode
Output. The address decoder unit 1 is controlled by the control signal C1.
Address A₀… A_NColumn address and
C Address is stored in the column address buffer unit 2 and the lower
It is transmitted to the dress buffer unit 3 respectively, and as a result, a memo
The memory cell at a specific address in
Output from address buffer unit 2 and row address buffer unit 3
Selected by the selected column address and row address.
Be done. Read / write circuit unit 5 according to control signal C2
Is selected via the row address buffer unit 3.
Applying a high voltage to the gate of the memory cell only erases the data.
To do. This allows the data of the selected memory cell above to be
Write both data bit and redundant bit to data "1".
Can be replaced. All addresses A of memory unit 4₀… A _N
To erase the memory cells of
Address A₀… A_NWhile changing the value of
It is necessary to do the work.

Here, in the test write mode,
The difference between the control signal C2 supplied from the control unit 7 to the read / write circuit unit 5 and the control signal C2 in the normal write mode will be described. The operation in the test write mode and the operation in the normal write mode of the semiconductor memory device are almost the same, only the control signal C2 is different, and the operation is slightly different according to the difference.

As described above, the control signal C2 is a signal for controlling the read / write circuit section 5, and is actually composed of a plurality of signal lines. It is a READ signal line that operates the read circuit to switch to the read mode (data output state), and a WRIT that switches to the write mode.
E signal line, W signal line for operating the writing circuit, E signal line for operating the erasing circuit, HVCK signal line for supplying a clock necessary for writing, TES1 signal line for instructing test mode 1, and test mode 2 There are a TES2 signal line, a TES3 signal line for instructing the test mode 3, and the like.

In the normal write mode, not only the E signal line is activated, but also the W signal line is activated, but in the test write mode, only the E signal line is activated and only the erase operation is performed. I am trying. 2 and 3 show examples of the circuit configuration of the test mode select circuit unit 7a incorporated in the control unit 7.

FIG. 2 shows an example of a circuit in the case of detecting that a high voltage is applied to any of the terminals provided in the control section 7 to enter the test write mode.
Channel MOS transistors Q _{11 to} Q ₁₃ and N channel MOS transistor Q ₁₄ and two inverters NT ₁₁ ,
Is comprised of the NT _12, the terminal (pad) TM ₁ is when the free, P-channel MOS transistor Q ₁₃ is N-channel MOS transistor Q ₁₄ off is ON. However, when a high voltage exceeding a predetermined value is applied to the terminal TM ₁ , the P channel MOS transistor Q
_{11 to} Q ₁₃ change from off to on, and the N-channel MOS transistor Q ₁₄ changes from on to off,
P channel MOS transistor Q ₁₃ and N channel M
The connection point of the OS transistor Q ₁₄ becomes “H”, and the test write mode detection signal of “H” is output from the output terminal of the inverter NT ₁₂ . Incidentally, P-channel MOS transistor Q ₁₁ to Q ₁₃ plays a function as a resistor.

In FIG. 3, the signal IN of the control section 7 is empty.
To a specific code (eg "10101111")
In the circuit example when detecting that
Yes, P-channel MOS transistor Q_{twenty one}, Q_{twenty two}And N
Channel MOS transistor Q _{twenty three}~ Q_{twenty five}And inverter NT
_{twenty one}And a signal in the control unit 7.
D-flip-flop FF provided at the input part of IN₁
~ FF₈8 bits parallel appearing at each output terminal of
The signal has a specific code (for example, "10101111")
N channel MOS transistor Q_{twenty three}~ Q_{twenty five}
Are all on, and the P-channel MOS transistor Q
_{twenty one}Turns off and the inverter NT_{twenty one}"H" from the output end of
The test write mode detection signal of
ing. Then, by setting the set signal to "L",
The above circuits can be reset.

Incidentally, FIG. 3 shows an example of a circuit for detecting a code corresponding to a read command. P-channel MOS transistors Q ₂₆ and Q ₂₇ , N-channel MOS transistors Q ₂₈ and Q _29, and an inverter NT. ₂₂ and its operation is similar to that described above. According to the semiconductor memory device of this embodiment, both the data bit and the redundant bit of the memory section 4 are erased to be in the state of all "1", and as a result, both the data bit and the redundant bit of the memory section 4 are the same. This means that the data has been rewritten to "1". That is, the redundant bits used for error correction are rewritten to the same data as the data bits. Therefore, the burn-in test and the high temperature storage test can be simultaneously performed on all the bits of the memory section 4. That is,
The burn-in test and the high temperature storage test can be performed once, and the inspection time can be shortened.

[Second Embodiment] FIG. 4 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention. As shown in FIG. 4, this semiconductor memory device has an address select circuit capable of simultaneously selecting all addresses between the address decoder unit 1 and the column address buffer unit 2 and the row address buffer unit 3 of the embodiment of FIG. This is a configuration in which the section 8 is provided. The address select circuit section 8 receives a control signal C4 for activation from the control section 7 to the address select circuit section 8 when the test write mode is selected from the control section 7, and receives all addresses regardless of the output address of the address decoder section 1. Is selected, and all addresses of the memory unit 4, that is, all memory cells are collectively selected by the column address buffer unit 2 and the row address buffer unit 3. Other configurations are similar to those of the embodiment of FIG.

In this semiconductor memory device, in the test write mode, the control signal C2 is output from the control section 7.
In response to this, the read / write circuit unit 5 applies a high voltage through the row address buffer unit 3 to perform only the erase operation. At this time, however, all the addresses of the memory unit 4 are collectively designated, All the memory cells of the memory unit 4 are erased at once and all become "1".

FIG. 5 shows a circuit example of the address select circuit section 8. The address select circuit 8 includes NOR circuit groups NO ₁₁ , NO ₁₂ , ... Which take an inverted logical sum of the output of each bit of the address decoder unit 1 and the control signal C4, and inverters NT ₃₁ , NT which invert their outputs. ₃₂ , ..., When the control signal C4 is "0", the output of each bit of the address decoder unit 1 is sent to the column address buffer unit 2 and the row address buffer unit 3 as it is, and the control signal C4 is "1". In the case of "," the address of all "1" is sent to the column address buffer unit 2 and the row address buffer unit 3 regardless of the output of each bit of the address decoder unit 1. At this time, the column address buffer unit 2 and the row address buffer unit 3 select all addresses.

According to the semiconductor memory device of this embodiment,
The address select circuit unit 8 simultaneously selects all the addresses of the memory unit 4 regardless of the output address of the address decoder unit 1, and all the bits of the memory unit 4 including the data bits and the redundant bits are the same at the same time. Can be rewritten to data. Therefore, the time required to make the data bits and the redundant bits of all the addresses of the memory unit 4 the same can be shortened, and the inspection time when performing the burn-in test or the high temperature storage test can be further shortened.

The other effects are similar to those of the first embodiment. [Third Embodiment] FIG. 6 is a block diagram of a semiconductor memory device according to a third embodiment of the present invention. In this semiconductor memory device, as shown in FIG. 6, between the error correction circuit unit 6 and the read / write circuit unit 5 of FIG. 4, data in which data can be arbitrarily set corresponding to data bits and redundant bits is set. This is a configuration in which a setting circuit unit 9 is provided. In this semiconductor memory device, when the test write mode of the control unit 7 is selected, the control unit 7 supplies a control signal C5 for activation to the data setting circuit unit 9 regardless of the output of the error correction circuit unit 6. A control signal C2 for giving arbitrary data (all "1" or all "0") from the section 9 to the read / write circuit section 5 and causing the read / write circuit section 5 to perform the erase operation and the write operation from the control section 7. And the read / write circuit section 5 writes the data of the data setting circuit section 9 to both the data bit and the redundant bit of the memory section 4. Other configurations are similar to those of the embodiment shown in FIG.

In this semiconductor memory device, if all "1" s are set in the data setting circuit section 9, the data setting circuit section 9 receives the control signal C5 and becomes all "1" or all "0" in the test write mode. The data is sent to the read / write circuit unit 5. As a result,
The write circuit unit 5 receives the control signal C2 and applies a high voltage to the memory cell via the row address buffer unit 3, thereby rewriting the data to the state set by the data setting circuit unit 9. That is, all “1” or all “0” data is written in all the memory cells of the memory section 4. In this case, unlike the first and second embodiments, the read / write circuit unit 5 performs both the erase operation and the write operation by applying a high voltage to the memory cell.

FIG. 7 shows a circuit example of the data setting circuit section 9. The data setting circuit section 9 includes P-channel MOS transistors Q ₃₁ , Q ₃₃ , N-channel MOS transistors Q ₃₂ , Q ₃₄ , N-channel MOS transistor Q ₄₁ ,
P-channel MOS transistor Q ₄₂ and OR circuit OR ₁₁
And inverters NT ₄₁ and NT ₄₂ . Control signal C
5, C5 'are both "L" and the WRITE signal is "H"
, P-channel MOS transistors Q ₃₁ and N
The channel MOS transistor Q ₃₂ is turned on, and the data D ₀ from the error correction circuit section 6 is supplied as it is to the read / write circuit section 5 as the data d ₀ , for example.

When the control signal C5 is "H", the control signal C5 'is "L", and the WRITE signal is "L",
The N-channel MOS transistor Q ₄₁ turns on, the P-channel MOS transistor Q ₄₂ turns off, and the data d ₀
“0” (all “0”) is supplied to the read / write circuit unit 5. Further, when the control signal C5 is "L",
In the control signal C5 'is "H", when the WRITE signal is "L", P-channel MOS transistor Q ₄₂ N-channel MOS transistor Q ₄₁ is turned off is turned on, as the data d ₀ "1" (all "1 “) Is supplied to the read / write circuit unit 5.

In the read mode, the P channel M
The OS transistor Q ₃₃ and the N channel MOS transistor Q ₃₄ are turned on. There is no timing between the control signal C5 and the other control signals C1 to C4, and they are all supplied to each circuit at the same time. According to the semiconductor memory device of this embodiment, when the test write mode is selected, arbitrary data is read / written from the data setting circuit section 9 by the read / write circuit section 5.
By performing an erasing operation and a writing operation to the read / write circuit section 5, the arbitrary data supplied from the data setting circuit section 9 regardless of the output of the error correction circuit section 6 is transferred to the data bit of the memory section 4. And both redundant bits can be written. Therefore, if all "1" or all "0" data is set in the data setting circuit section 9, the same data can be written in both the data bit and the redundant bit of the memory section 4. Therefore, the burn-in test and the high temperature storage test can be simultaneously performed on all the bits of the memory section 4, and the inspection time can be shortened. At this time, the data to be written in the memory unit 4 is not limited to all “1” but all “0”.
Therefore, it is possible not only to collectively rewrite both the data bit and the redundant bit to the state of data “1”, but also to rewrite them to the state of data “0” collectively. The accuracy of inspection can be improved by performing a burn-in test or a high temperature storage test. The other effects are similar to those of the second embodiment.

The data setting circuit section 9 shown in FIG. 6 can be added to the embodiment shown in FIG. in this case,
Since the address select circuit section 8 is not provided, the data cannot be rewritten all at once, but other effects are the same as those of the embodiment of FIG.

[0037]

According to the semiconductor memory device of the first aspect, both the data bit and the redundant bit can be made the same data, and the burn-in test and the high temperature storage test can be performed once. The inspection time can be shortened. According to the semiconductor memory device of the second aspect, the data to be written in the memory section can be set to either "1" or "0", and the burn-in test and the high temperature storage test are performed at both "1" and "0". Therefore, the accuracy of the burn-in test and the high temperature storage test can be improved.

According to the semiconductor memory device of the third aspect, the rewriting of the data bits and the redundant bits into the same data of all the memories can be collectively performed, and the inspection time can be further shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a specific configuration of a test mode select circuit section.

FIG. 3 is a circuit diagram showing another example of a specific configuration of a test mode select circuit section.

FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram showing an example of a specific configuration of an address select circuit section.

FIG. 6 is a block diagram showing a third embodiment of the semiconductor memory device according to the present invention.

FIG. 7 is a circuit diagram showing an example of a specific configuration of a data setting circuit section.

FIG. 8 is a block diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Address Decoder 2 Column Address Buffer 3 Row Address Buffer 4 Memory 5 Read / Write Circuit 6 Error Correction Circuit 7 Control 7a Test Mode Select Circuit 8 Address Select Circuit 9 Data Setting Circuit

Claims (3)

[Claims] 1. An address decoder section for converting an address inputted from the outside into a column address and a row address and outputting the column address and a memory, and a memory having a data bit and a redundant bit and having an access position designated by the column address and the row address. Section, a read / write circuit section for reading data from the memory section and writing data to the memory section, and the read / write circuit section for adding a redundant bit to externally input data An error correction circuit unit for supplying data to the read / write circuit unit and performing error correction on the data supplied from the read / write circuit unit using a redundant bit to output to the outside; the address decoder unit; and the read / write circuit unit. And the error correction circuit section for each mode such as reading and writing. And a test mode select circuit unit that detects the test write command signal supplied from the outside and is selected by the control unit to select the test write mode. At the time of selection, the control unit gives a control signal to the read / write circuit unit to perform only an erase operation, and the read / write circuit unit erases both the data bit and the redundant bit of the memory unit. Semiconductor memory device. 2. An address decoder unit for converting an address inputted from the outside into a column address and a row address and outputting the column address and a row address, and a memory having a data bit and a redundant bit and having an access position designated by the column address and the row address. Section, a read / write circuit section for reading data from the memory section and writing data to the memory section, and the read / write circuit section for adding a redundant bit to externally input data An error correction circuit unit for supplying data to the read / write circuit unit and performing error correction on the data supplied from the read / write circuit unit using a redundant bit to output to the outside; the address decoder unit; and the read / write circuit unit. And the error correction circuit section for each mode such as reading and writing. A control section for providing a control signal for the control section, a test mode select circuit section which is built in the control section and detects a test write command signal supplied from the outside, and causes the control section to select a test write mode, the data bit and the redundancy. A data setting circuit section capable of arbitrarily setting data corresponding to bits, and the error correction circuit by giving a control signal for activation from the control section to the data setting circuit section when a test write mode is selected. Regardless of the output of the unit, the data setting circuit unit gives arbitrary data to the read / write circuit unit, and the control unit gives a control signal to the read / write circuit unit to perform an erase operation and a write operation. The data of the memory unit by the read / write circuit unit A semiconductor memory device, wherein the data of the data setting circuit section is written in both the bit and the redundant bit. 3. An address select circuit section capable of selecting all addresses at the same time is provided, and when the test write mode is selected, a control signal for activation is given from the control section to the address select circuit section so that the address select circuit section can address the address. 3. The semiconductor memory device according to claim 1, wherein all addresses of the memory section are selected at the same time regardless of the output address of the decoder section.