JPH08161468A - Color conversion processing unit - Google Patents

Abstract

PURPOSE: To obtain the color conversion processing unit in which color conversion with high accuracy in real time or at a speed equivalent thereto is realized with a small circuit scale and the conversion accuracy of a dark part is especially enhanced. CONSTITUTION: The processing unit is provided with a 1st storage means 20 that stores the 1st color signal where its dark part is increased densely and its highlight part (high luminance part) is converted roughly when a 1st 3-dimensional color space represented by 1st to 3rd color signals is converted into a 2nd 3-dimensional color space represented by 4th to 6th color signals, a 2nd storage means 1 that receives a storage area number of the 1st color signal stored in the 1st storage means 20 and receives the 2nd and 3rd color signals and provides an output of the 4th to 6th color signals at plural points located at unit grating in the vicinity of points represented by the 2nd and 3rd color signals in the 2nd 3-dimensional color space, an interpolation coefficient generating means 2 generating an interpolation coefficient to calculate an interpolation signal from the 4th to 6th color signals at the plural points, and interpolation processing means 11, 12, 18, 19 interpolating the 4th to 6th color signals based on the 4th to 6th color signals at plural points and the interpolation coefficient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color conversion processing device.

[0002]

2. Description of the Related Art FIG. 7 is a block circuit diagram showing a conventional color conversion processing apparatus and color inverse conversion processing apparatus. In the figure, 44 and 45 are three-dimensional lookup tables (hereinafter,
"LUT").

Next, the operation will be described. For color television systems, NTSC (National Television System C
ommittee) system, PAL (Phase Alternation by Line) system, and SECAM (Sequential a Memoire) system. For example, signals in the RGB color space in the NTSC system are CIE 1976 L
^* a ^* b ^* A method of converting to a signal in the uniform perceptual color space is shown below.

The CIE 1976 L ^* a ^* b ^* uniform perceptual color space is defined by the Commission Internationale de l'Eclaira.
ge is an abbreviated name CIE) recommended in 1976, and is a color space with a perceptually almost even rate. First, the following (1),
As shown in equations (2) and (3), the NTSC RGB signal is converted into XYZ. X = 0.6069R + 0.1739G + 0.209B …… (1) Y = 0.2991R + 0.5870G + 0.1139B …… (2) Z = 0.0000R + 0.0660G + 1.1169B …… (3)

The reference white color in the NTSC system is a C light source (chromaticity coordinate x = 0.3101, y = 0.3163: correlated color temperature of about 6770K),
The tristimulus value X ₀ Y ₀ Z ₀ of the C light source is expressed by _equations (4), (5), and (6) when Y ₀ is 100. X ₀ = 98.072 …… (4) Y ₀ ＝ 100.000 …… (5) Z ₀ ＝ 118.225 …… (6)

L ^* a ^* b ^* with XYZ as a reference white light source as C light source
Convert to. ^{L * = 116 (Y / Y} 0) 1/3 -16: Y / Y 0> 0.008856 ...... (7) L * = 903.29 (Y / Y 0): Y / Y 0 <= 0.008856 ...... (8) ^{a * = 500 (X'-Y} ') ...... (9) b * = 200 (Y'-Z') ...... (10) X '= (X / X 0) 1/3: X / X 0> 0.008856 …… (11) X '= 7.787 (X / X ₀ ) +16/116: X / X ₀ <= 0.008856 …… (12) Y' = (Y / Y ₀ ) ^1/3 : Y / Y ₀ > 0.008856 …… (13) Y '＝ 7.787 (Y / Y ₀ ) +16/116 ： Y / Y ₀ <= 0.008856 …… (14) Z' ＝ (Z / Z ₀ ) ^1/3 ： Z / Z ₀ > 0.008856 ...... (15) Z '= 7.787 (Z / Z ₀ ) +16/116: Z / Z ₀ <= 0.008856 ・ ・ ・ (16) By the conversion formulas of formula (1) to formula (16), NTSC A signal of RGB color space in the method is non-linearly converted into a signal of CIE 1976 L ^* a ^* b ^* uniform perceptual color space.

Next, a method for inversely converting the CIE 1976 L ^* a ^* b ^* uniform perceptual color space into an RGB color space signal will be described below. First, as shown in the following equations (17) to (20), L ^* a ^* b ^{* in} which the reference white color is the C light source is converted into XYZ. X = X ₀ {(L ^* + 16) / 116 + a ^* / 500} ³ (17) Y = Y ₀ {(L ^* + 16) / 116} ³ : L ^* > = 8.0 ...... (18 ) Y = Y ₀ × L ^{* /} 903.29: L ^* <8.0 …… (19) Z = Z ₀ {(L ^* + 16) / 116-b ^* / 200} ³ …… (20)

XYZ is converted into an NTSC type RGB signal. R = 1.9106X-0.5335Y-0.2893Z (21) G = -0.9848X + 1.9983Y-0.0266Z (22) B = 0.0582X-0.1181Y + 0.8969Z (23)

From the conversion formulas (1) to (16), L ^* , a ^* , and b ^* for all R, G, and B are calculated, and the converted values are stored in the three-dimensional LUT 44. Also, equations (17) to (23)
All R, G, and B for L ^* , a ^* , and b ^* are calculated from the inverse conversion formula of the formula, and the conversion values are stored in the three-dimensional LUT 45.

FIG. 8 shows a conceptual diagram of the three-dimensional LUT 44.
The three-dimensional LUT 44 allows the output signals L ^* (Ri, Gi, Bi), a ^* (R) located at the grid points of the input signals Ri, Gi, Bi.
i, Gi, Bi), b ^* (Ri, Gi, Bi) are obtained.

FIG. 9 shows a conceptual diagram of the three-dimensional LUT 45.
The three-dimensional LUT 45 allows the input signals Li ^* , ai ^* , b
The output signal is located at a lattice point of the ^{i * R (Li *, ai} *, bi *), G (L
i ^* , ai ^* , bi ^* ) and B (Li ^* , ai ^* , bi ^* ) are obtained.

Three-dimensional L used for these forward and reverse transformations
The greater the number of UT grid points, the higher the conversion accuracy. The method of directly obtaining the output signals for all the input signals by the LUT is called the direct mapping method. By using the direct mapping method, it is possible to perform high-speed and high-precision conversion regardless of any complicated conversion method.

However, for example, if the input signals R, G, B and the output signals L ^* , a ^* , b ^* are each 8 bits, the capacity of the three-dimensional LUT 44 used for this normal conversion becomes 384 Mbits, and a large scale memory is required. It is not practical because it requires means. In general, a method is used in which several nearby values are obtained by a direct mapping method using an upper signal of an input signal and an output signal is interpolated from several neighboring values using a lower signal of the input signal.

Next, another conventional technique will be described.
Figure 10 shows "ITEJ Technical Report Vol.16, No.31, pp.
25-30 ”is a block circuit diagram showing another conventional color conversion processing device. In the figure, 46 is a three-dimensional LU
T and 47 are interpolation coefficient generation circuits, 48 to 55 are multipliers,
56 is an adder circuit.

The upper signals Rn, Gn, Bn of the input signals Ri, Gi, Bi are set to 3
Input to the dimension LUT 46. Also, the lower signals of Ri, Gi, Bi
The r, g and b are input to the interpolation coefficient generation circuit 47. Three-dimensional LU
T46 of the output _{d 0, d 1, d 2} , d 3, d 4, d 5, d 6, and d ₇ each multiplier 4
Input to 8, 49, 50, 51, 52, 53, 54, 55. Outputs of interpolation coefficient generation circuit 47 w ₀ , w ₁ , w ₂ , w ₃ , w ₄ , w ₅ ,
w ₆ and w ₇ are respectively multiplied by multipliers 48, 49, 50, 51, 52, 5
Input to 3, 54, 55. Multipliers 48, 49, 50,
The outputs of 51, 52, 53, 54 and 55 are input to the adder circuit 56. The higher 8 bits d of the output of the adder circuit 56 are obtained. d is d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ respectively w ₀ , w ₁ , w ₂ , w ₃ , w
_It is obtained by multiplying ₄ , w ₅ , w ₆ , and w ₇ and adding them together, and discarding the lower 15 bits in order to normalize the interpolation coefficient to 1.

Next, the operation will be described. Input signal R
It is assumed that i, Gi, Bi are m-bit signals, and upper n bits of the input signals Ri, Gi, Bi are Rn, Gn, Bn, respectively. However, m> n. Neighborhood 8 of the input signals Ri, Gi, Bi from the three-dimensional LUT 46
Unit cubic lattice of points (Rn, Gn, Bn), (Rn + Dn, Gn, Bn), (Rn + Dn, G
n, Bn + Dn), (Rn, Gn, Bn + Dn), (Rn, Gn + Dn, Bn), (Rn + Dn, Gn + Dn,
Bn), (Rn + Dn, Gn + Dn, Bn + Dn), (Rn, Gn + Dn, Bn + Dn)
Obtain d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ . However, Dn is 2 ^mn, which is the length of one side of the unit cubic lattice of the three-dimensional LUT 46.

Next, the interpolation method will be described. As shown in FIG. 11, the output signals located in the unit cubic lattice of eight points near the input signals Ri, Gi, Bi are d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d. _Set to ₇ . The lower m-n bits of the input signals Ri, Gi, Bi are respectively r, g,
b, the length of one side of the unit cubic lattice is Dn. Input signal Ri,
3 about R axis direction, G axis direction and B axis direction with Gi and Bi as the center
The volume of a rectangular parallelepiped that is divided into eight parts in each direction is w ₀ , w ₁ , w ₂ , w ₃ ,
and _{w 4, w 5, w 6} , w 7. The output signal d for the input signals Ri, Gi, Bi is interpolated as shown in Expression (24). d = d ₀ w ₀ + d ₁ w ₁ + d ₂ w ₂ + d ₃ w ₃ + d ₄ w ₄ + d ₅ w ₅ + d ₆ w ₆ + d ₇ w ₇ (24) This interpolation method Then, each of L ^* , a ^* , and b ^* is interpolated.

The same applies to the inverse transformation. Figure 12
It is a block circuit diagram which shows the conventional color reverse conversion processing apparatus.
In the figure, 57 is a three-dimensional LUT, 58 is an interpolation coefficient generation circuit, 59 to 66 are multipliers, and 67 is an addition circuit.

Upper signal Ln ^* , an ^* , b of input signals Li ^* , ai ^* , bi ^*
Input n ^* to the three-dimensional LUT 57. Also, Li ^* , ai ^* , bi ^*
The lower order signals l ^* , a ^* , b ^* of are input to the interpolation coefficient generation circuit 58. Outputs of three-dimensional LUT 57 p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇
To multipliers 59, 60, 61, 62, 63, 64, 6 respectively.
Input to 5,66. Outputs v ₀ , v of the interpolation coefficient generation circuit 58
₁ , v ₂ , v ₃ , v ₄ , v ₅ , v ₆ , v ₇ are respectively multiplied by multipliers 59, ₆₀ , 61,
Input to 62, 63, 64, 65, 66. Multiplier 5
The outputs of 9, 60, 61, 62, 63, 64, 65, 66 are input to the adder circuit 67. The upper 8 bits p of the output of the adder circuit 67 are obtained. p is p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p ₅ , p ₆ , p ₇ respectively v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ , v ₆ , v ₇ Is added and multiplied, and the lower 15 bits are truncated to normalize the interpolation coefficient to 1.

Next, the operation will be described. Input signal Li
^* , ai ^* , bi ^* are m-bit signals and input signals Li ^* , ai ^* , bi ^*
The upper n bits of are defined as Ln ^* , an ^* , and bn ^* , respectively. However,
m> n. Input signal Li ^* , ai ^* , from the three-dimensional LUT 57
A unit cubic lattice (Ln ^* , an ^* , bn ^* ), (Ln ^* , an ^* +) with 8 points near bi ^*
Dn, bn ^* ), (Ln ^* , an ^* + Dn, bn ^* + Dn), (Ln ^* , an ^* , bn ^* + Dn), (Ln ^* +
Dn, an ^* , bn ^* ), (Ln ^* + Dn, an ^* + Dn, bn ^* ), (Ln ^* + Dn, an ^* + Dn, bn ^*
+ Dn), (Ln ^* + Dn, an ^* , bn ^* + Dn) located at p ₀ , p ₁ , p ₂ , p ₃ , p ₄ , p
_{Get 5} , p ₆ and p ₇ . However, Dn is 2 ^mn, which is the length of one side of the unit cubic lattice of the three-dimensional LUT 57.

Next, the interpolation method will be described. As shown in FIG. 13, the input signal Li ^*, ai ^*, an output signal that is located in the unit cubic lattice near eight points _{^{bi * p 0, p 1,}} p 2, p 3, p 4, p 5, p ₆ and p ₇ . The lower mn bits of the input signals Li ^* , ai ^* , and bi ^* are respectively l ^* , a ^* , and b ^* , and the length of one side of the unit cubic lattice is Dn. L ^* axis direction, a ^* axis direction, b centered on the input signal Li ^* , ai ^* , bi ^*
* The volume of a rectangular parallelepiped divided into eight in three axial directions is v ₀ ,
_{v 1, v 2, v 3} , v 4, v and _5, v _6, v _7. The output signal p for the input signals Li ^* , ai ^* , and bi ^* is interpolated as shown in Expression (25). p = p ₀ v ₀ + p ₁ v ₁ + p ₂ v ₂ + p ₃ v ₃ + p ₄ v ₄ + p ₅ v ₅ + p ₆ v ₆ + p ₇ v ₇ (25)

[0022]

Since the conventional color conversion processing device and color inverse conversion processing device are configured as described above, it is possible to perform color conversion in real time or at a speed equivalent thereto. There was a problem.

First, if output signals for all input signals are obtained by the direct mapping method, highly accurate conversion is possible, but a large capacity LUT is required.

Second, in order to reduce the capacity of the LUT,
Using the upper signal of the input signal, several neighboring values are obtained by the direct mapping method, and by using the lower signal of the input signal,
In the method of interpolating the output signal from several neighboring values, the conversion accuracy is high in 8-point interpolation using 8-point unit cubic lattice, but many multipliers are required and the circuit scale becomes large. Also,
If the circuit scale is reduced by reducing the number of data used for interpolation such as 6-point interpolation, 5-point interpolation, and 4-point interpolation, the number of multipliers decreases but the conversion accuracy also decreases.

Third, the conversion value is stored in fixed point to reduce the capacity of the LUT. For example, in the case of 8 bits, the converted value is rounded from 0 to 255. Therefore, when the converted value is small, a large rounding error is included. Since the interpolation process is performed using the conversion value including the rounding error, an error occurs between the interpolation value and the actual value. Especially, the interpolation error becomes large in the part where the color signal is small, that is, in the dark part,
The conversion accuracy is low.

The present invention has been made in order to solve the above-mentioned problems, and performs color conversion with higher accuracy than before in a small circuit scale in real time or at a speed corresponding to it, and particularly, in dark areas. It is an object of the present invention to obtain a color conversion processing device and a color inverse conversion processing device that can improve the conversion accuracy of.

[0027]

According to a first aspect of the present invention, there is provided a color conversion processing device, wherein a first three-dimensional color space represented by first, second and third color signals is used as a fourth, fifth and third color space. In the color conversion processing device for converting into the second three-dimensional color space represented by the sixth color signal, the first storage means stores the first color signal which is densely increased in the dark part and coarsely increased in the middle and high brightness parts. And a storage number obtained by inputting the first color signal into the first storage means and the second and third color signals are input, and a point in the second three-dimensional color space indicating the input signal Second storage means for outputting fourth, fifth, and sixth color signals of a plurality of points located in a unit cell in the vicinity, and an interpolation signal calculated from the fourth, fifth, and sixth color signals of the plurality of points Interpolation coefficient generating means for generating an interpolation coefficient for performing the fourth, fifth, and sixth color signals at the plurality of points and the interpolation coefficient. 5, those having an interpolation processing means for interpolating a sixth color signal.

A color conversion processing device according to the invention of claim 2 is
The first three-dimensional color space represented by the first, second, and third color signals is converted to the second three-dimensional space represented by the fourth, fifth, and sixth color signals.
In a color conversion processing device for converting into a three-dimensional color space, the lightness of a specific color represented by the fourth, fifth, and sixth color signals after color conversion is increased densely in the dark part and coarsely in the middle and high brightness parts. A first storage means for storing the first color signal and a storage number k (k is a natural number) obtained by inputting the first color signal, which is a digital signal of m (m is a natural number) bit, to the first storage means. ) And m-bit digital signals, which are second and third color signals, are input, and are assumed to be located on or located in a unit rectangular grid in the vicinity of a point in the second three-dimensional color space indicating the input signals. Second storage means for outputting the fourth, fifth, and sixth color signals of eight points, and an interpolation coefficient for generating an interpolation coefficient for multiplying the fourth, fifth, and sixth color signals of the eight points Generating means,
The fourth, fifth, and fourth positions, which include the second and third color signals of m bits and are located in the unit plane lattice of four points when the first color signal is stored in the kth position Means for outputting a first interpolated signal obtained by multiplying the color signals of 6 by the above-mentioned interpolating coefficient and adding them together, and second and third similarly having m bits
And the first, second, and sixth color signals, which are located in the unit plane lattice of four points when the first color signal is stored in the k + 1th color signal, And a means for outputting a second interpolated signal obtained by multiplying and adding, and multiplying the first interpolated signal by subtracting the m-bit first color signal from the k + 1th stored first color signal, Fourth, fifth, and sixth color signals are calculated by multiplying the second interpolation signal by the m-bit first color signal minus the k-th stored first color signal and adding the result. It is provided with an interpolation processing means.

A color conversion processing device according to a third aspect of the invention is
The first storage means stores the first color signal in which the lightness of the achromatic color represented by the fourth, fifth, and sixth color signals after color conversion is increased densely in the dark part and coarsely in the middle and high brightness parts. It was done.

A color conversion processing device according to a fourth aspect of the present invention is
When each of the first, second, and third color signals is a digital signal of m bits, one side is centered on the second and third color signals of lower m−n (n is a natural number m> n) bits. A unit plane of 2 ^mn bits is divided into four in the axial direction of the second color signal and the axial direction of the third color signal, and an interpolation coefficient generating means for outputting the area of the four planes as an interpolation coefficient is provided. It is a thing.

A color conversion processing apparatus according to the invention of claim 5 is
Input the second and third color signals for the lower mn bits,
The interpolation coefficient generating means for outputting the four interpolation coefficients necessary for calculating the interpolation signal is composed of four storage means.

A color conversion processing apparatus according to the invention of claim 6 is
Input the second and third color signals for the lower mn bits,
A storage unit that outputs one interpolation coefficient out of the four interpolation coefficients necessary for calculating the interpolation signal, a plurality of adders, and a plurality of bit shift circuits, and the other three interpolations from the output signal of the storage unit. It is provided with an interpolation coefficient generating means for calculating a coefficient.

[0033]

According to the first aspect of the present invention, the first storage means of the color conversion processing device stores the first color signals which are densely increased in the dark area and coarsely increased in the middle and high luminance areas, and the second storage means is The storage number obtained by inputting the first color signal to the first storage means and the second and third color signals are input, and the vicinity of a point in the second three-dimensional color space indicating the input signal is input. A plurality of points of fourth, fifth, and sixth color signals located on the unit grid are output, and the interpolation coefficient generating means calculates an interpolation signal from the plurality of points of fourth, fifth, and sixth color signals. For generating the interpolation coefficient, and the interpolation processing means interpolates the fourth, fifth, and sixth color signals by the fourth, fifth, and sixth color signals of the plurality of points and the interpolation coefficient, High-precision color conversion can be realized in real time or at a speed similar to that, and conversion accuracy by linear interpolation, especially in dark areas, can be improved. That.

According to the second aspect of the present invention, the first storage means of the color conversion processing device provides the lightness of the specific color represented by the fourth, fifth and sixth color signals after the color conversion, and the dark portion is dense, The medium-high brightness part stores the first color signal which is roughly increased, and the second storage means inputs the first color signal which is a digital signal of m (m is a natural number) bits to the first storage means. The storage number k (k is a natural number) obtained and the second and third color signals that are m-bit digital signals are input, and a unit in the vicinity of a point in the second three-dimensional color space indicating the input signal Eight-point fourth, fifth, and sixth color signals that are located on the assumption that they are or are located on a rectangular grid are output, and the interpolation coefficient generating means outputs the eight-point fourth, fifth, and sixth color signals. Means for generating an interpolation coefficient for multiplying by and outputting the first interpolation signal includes m-bit second and third color signals. , The 4th, 5th, and 6th color signals located in the 4-point unit plane grid in the case where the 1st color signal is the kth stored signal are multiplied by the interpolation coefficient and added. The means for outputting the first interpolation signal and the second interpolation signal also includes m-bit second and third color signals, and the first color signal is stored in the (k + 1) th order. 4th, 5th, which are located in the unit plane lattice of 4 points of
The sixth color signal is multiplied by each of the interpolation coefficients and added to output a second interpolation signal, and the interpolation processing means outputs m bits of the first color signal stored in the (k + 1) th first interpolation signal from the first color signal. By multiplying by subtracting the first color signal and multiplying the second interpolation signal by subtracting the m-bit first color signal minus the k-th stored first color signal, 4,
Since the fifth and sixth color signals are calculated, highly accurate color conversion can be realized in real time or at a speed corresponding thereto, and the conversion accuracy by linear interpolation, especially the conversion accuracy of dark areas can be improved.

According to the third aspect of the present invention, the first storage means of the color conversion processing device provides the lightness of the achromatic color represented by the fourth, fifth and sixth color signals after the color conversion, and the dark portion is densely arranged. Since the medium-high brightness portion stores the first color signal that is roughly increased, it is possible to reduce the conversion error in the lightness direction while maintaining the balance of the hue, saturation, and lightness of the converted image.

In the interpolation coefficient generating means of the color conversion processing device according to the invention of claim 4, the first, second and third color signals are respectively m.
In the case of a bit digital signal, a unit plane whose sides are 2 ^mn bits centering on the second and third chrominance signals for the lower m−n (n is a natural number m> n) bits is the second chrominance signal. Since the area of the four planes when divided into four is output as the interpolation coefficient in the axis direction of and the axis direction of the third color signal, high-precision color conversion can be performed by the small-capacity storage means and interpolation processing means. It becomes possible and the circuit scale can be reduced.

The interpolation coefficient generating means of the color conversion processing device according to the fifth aspect of the present invention inputs the second and third color signals of the lower m−n bits and outputs four signals necessary for calculating the interpolation signal. Since it is composed of four storage means for outputting the interpolation coefficient, the number of multipliers can be reduced and the circuit scale can be reduced.

The interpolation coefficient generating means of the color conversion processing device according to the sixth aspect of the present invention inputs the second and third color signals of the lower m−n bits and is required by the storage means to calculate the interpolation signal. One of the four interpolation coefficients is output, and the other three interpolation coefficients are calculated from the output signal of the storage means, the plurality of adders, and the plurality of bit shift circuits, so that the number of multipliers is reduced. It is possible to reduce the circuit scale.

[0039]

EXAMPLES Example 1. First Embodiment FIG. 1 is a block circuit diagram showing a color inverse conversion processing device according to a first embodiment of the present invention. In the figure, 1 is a three-dimensional LUT, 2 is an interpolation coefficient generation circuit, 3 to 12 are multipliers, 13 and 14 are addition circuits, 15 to 18 are adders,
Reference numeral 19 is a divider, and 20 is an LUT.

The input signal Li ^* is input to the LUT 20 and the LU
T20 of the output k and the input signal ai ^*, bi ^* higher signal an ^*, bn ^*
Is input to the three-dimensional LUT1. Output of LUT 20 L _k ^* , L
_{k + 1} ^* is input to the adder 15, Li ^* , L _{k + 1} ^* is input to the adder 16, and Li ^* , L _k ^* is input to the adder 17. Also, ai ^* , b
The low order signals a ^* and b ^* of i ^* are input to the interpolation coefficient generation circuit 2.
The outputs d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d ₇ of the three-dimensional LUT ₁ are input to the multipliers ₃ , ₄ , ₅ , ₆ , ₇ , 8, 9, 10, respectively. .
The outputs S ₀ , S ₁ , S ₂ , S ₃ of the interpolation coefficient generation circuit 2 are input to the multipliers 3, 4, 5, 6 and 7, 8, 9, 10, respectively. The outputs of the multipliers 3, 4, 5, 6 are input to the adder circuit 13, and the outputs of the multipliers 7, 8, 9, 10 are input to the adder circuit 14.
The output of the adder 16 and the output ds of the adder circuit 13 are multiplied by the multiplier 1
Input to 1, output of adder 17 and output of adder circuit 14
The ds ′ is input to the multiplier 12. These two multipliers 11,
The output of 12 is input to the adder 18. The output of the adder 15 and the output of the adder 18 are input to the divider 19 to obtain the upper 8 bits d of the output.

Next, the operation will be described. Input signal Li
Each of ^* , ai ^* , bi ^* is 8 bits. Input signal Li ^* is LUT
Enter 20. FIG. 2 shows a conceptual diagram of the LUT 20. L
For example, when the input signal Li ^* is 200, the UT 20 outputs the storage number k as 7, L _k ^* as 195, and L _{k + 1} ^* as 213. The same applies to other cases, but only when Li ^* is 243 or more, L _{k + 1} ^*
Is output as 256.

Each of R, G, and B is an 8-bit signal,
When the R, G, and B signals have the same achromatic color, Table 1 shows L ^* , a ^* , and b ^* (the C light source is the reference white color) corresponding to these signals. This L ^* is normalized to 8 bits as shown in Table 2.

[0043]

[Table 1]

[0044]

[Table 2]

In FIG. 1, the storage number k and the input signal a
Three-dimensional LUT 1 for the upper 3 bits of each of i ^* and bi ^* an ^* and bn ^*
Input to the input signal Li ^* , ai ^* , bi ^* , and unit rectangular grid (k, an ^* , bn ^* ), (k, an ^*, Dn, bn ^* ), (k, an ^* +) Dn, bn ^* + Dn),
(k, an ^* , bn ^* + Dn), (k + D _k , an ^* , bn ^* ), (k + D _k , an ^* + Dn, bn ^* ), (k
+ D _k , an ^* + Dn, bn ^* + Dn), (k + D _k , an ^* , bn ^* + Dn) output signal d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d _{Get 5} , d ₆ and d ₇ . Dn is a three-dimensional LU
The length of one side of the unit plane in the a ^* axis and b ^* axis directions of T1 is ²⁵ . D _k is the difference between the outputs L _{k + 1} ^* and L _k ^* of the LUT 20, and L ^*
It is the length of one side of the unit rectangular lattice in the axial direction.

Further, the lower 5 bits r, b of each of the input signals ai ^* , bi ^* are input to the interpolation coefficient generating circuit 2, and the interpolation coefficients S ₀ , S ₁ , S ₂ , S ₃ as shown in FIG. To get 3D LU
The upper surface (unit plane consisting of d ₄ , d ₅ , d ₆ , d ₇ points), the lower surface (unit plane consisting of d ₀ , d ₁ , d ₂ , d ₃ points) of the unit rectangular lattice of T1, and the input signal Li The position of ^{* on} the L ^* axis is shown. S ₀ , S ₁ , S ₂ , S ₃ are the lower 5 bits of the input signals ai ^* , bi ^*
It is an interpolation coefficient corresponding to four planes when a unit plane having sides of ²⁵ bits is divided into four in the a ^* axis direction and the b ^* axis direction with the point located at a ^* and b ^* as the center. S ₀ ＝ (Dn-a ^* ) × (Dn-b ^* ) …… (26) S ₁ ＝ a ^* × (Dn-b ^* ) …… (27) S ₂ ＝ a ^* × b ^* …… (28 ) S ₃ = (Dn-a ^* ) × b ^* …… (29)

FIG. 4 is a diagram showing the configuration of the interpolation coefficient generating circuit 2. In the figure, 21 and 22 are bit inversion circuits,
Reference numerals 23 to 26 are multiplication circuits. Since Dn is the length of one side of the unit plane in the a ^* -axis and b ^* -axis directions, when inputting the upper 3 bits of the 8 bits of the input signal to the three-dimensional LUT 1, Dn = ²⁵ . Therefore, Dn-a ^* is the inversion of all bits of a ^* . Similarly, Dn-b ^* is also the inversion of all bits of b ^* . Using the above, the bit inversion circuits 21 and 22 and the multiplication circuits 23, 24, 25 and 2
According to 6, equations (26), (27), (28), (29)
Can be realized.

The first interpolation signal ds is calculated using the multipliers 3, 4, 5, 6 and the adder circuit 13 shown in FIG. Also,
Using the multipliers 7, 8, 9, 10 and the adder circuit 14, the second
The interpolated signal ds' is calculated. The calculation formula is the formula (3
It is represented by 0) and (31). ds = d ₀ S ₀ + d ₁ S ₁ + d ₂ S ₂ + d ₃ S ₃ (30) ds' = d ₄ S ₀ + d ₅ S ₁ + d ₆ S ₂ + d ₇ S ₃ ...... (31) In the equations (30) and (31), the signals at the respective lattice points are multiplied by the areas located point-symmetrically with respect to the input signals ai ^* and bi ^* as interpolation coefficients to obtain a ^* and b. ^* Two interpolation signals on the plane are calculated. By interpolating these two interpolation signals ds, ds' on the L ^* axis, 3
Realize dimensional interpolation. When the length of one side of the unit rectangular lattice in the L ^* axis direction is D _k , the output signal d is calculated as in Expression (32). ^{d = {ds' × l *} + ds × (D k -l *)} / (Dn 2 × D k) ...... (32)

However, l ^* is the difference between L _k ^* and the input signal Li ^* , which is calculated by the adder 17 and D _k is calculated by the adder 15. The division by (Dn ² × D _k ) is to normalize the interpolation coefficient to 1. Here, Dn ² is to become a 2 ¹⁰ can be calculated by actually be lowered 10 bits of digits. The calculation of Expression (32) is realized by the multipliers 11 and 12, the adders 15, 16, 17, and 18, and the divider 19. D _k -l
^{The *} and the first interpolation signal ds are input to the multiplier 11, and the l ^* and the second interpolation signal ds ′ are input to the multiplier 12. Multiplier 11,
The output signal of 12 is input to the adder 18, and the output of the adder 18 is divided by D _k by the divider 19. The higher 8 bits d of the output of the divider 19 are obtained. d is d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d
₅ , d ₆ , d ₇ are multiplied by each interpolation coefficient and added together.
The lower 20 bits are truncated to normalize the interpolation coefficient to 1. R, G, B by the same calculation method
Interpolation processing is performed.

In the present embodiment, in order to improve the conversion accuracy, the number of grid points in the dark area is made larger than the number of grid points in the middle and high brightness areas. In this case, the dark part is a part having a small L ^* . The conversion value to be stored in the three-dimensional LUT may be a floating point whose number of significant digits is compensated, but since the floating point requires a storage means larger than the fixed point, the conversion value is generally fixed point. Remember. When the converted value is stored in the fixed point as described above, the rounding error increases when the converted value is small. When the linear interpolation is performed using the converted value including many rounding errors, the error between the actual value and the interpolated value becomes large.

There are two possible methods of reducing this error. There are a method of increasing the number of bits of the converted value while keeping the number of grid points, and a method of increasing the number of grid points in the dark part as in the present embodiment. In the former case, it is necessary to increase the number of bits not only in the dark part but also in the middle and high brightness parts, and the number of redundant parts increases. The latter is a method of making the grid point distance of the dark part where the error becomes large shorter than that of the middle and high brightness parts to reduce the interpolation error, and there are few redundant parts.

However, in order to reduce the interpolation error in such a dark part, negative R, G, B (imaginary color that does not actually exist) or R, G, B exceeding the maximum value is used as the conversion value. It needs to be stored in a three-dimensional LUT. The reason will be described.

From CIE 1976 L ^* a ^* b ^* uniform perceptual color space to RG
Conversion to the B color space requires a three-dimensional LUT that fully contains the RGB color space. This color space conversion is non-linear, and negative R, G, B (imaginary colors that do not actually exist) and R, G, B exceeding the maximum value are included in the three-dimensional LUT. When the number of grid points of the three-dimensional LUT for the input value is sufficiently large, any conversion value for a color that does not exist in the RGB color space does not significantly affect the conversion accuracy. Negative R, G, B is rounded to 0, and R, G, B exceeding the maximum value are rounded to the maximum value. However, when the number of grid points of the three-dimensional LUT for the input value is small and the linear interpolation is simply performed, the original RGB
If the conversion value for a color that does not exist in the color space is rounded to 0 or the maximum value, the conversion accuracy is greatly affected.

For example, consider the case where 8-bit L ^* , a ^* , b ^* is inversely converted into 8-bit R, G, B. 33 If there are ³ grid points and the conversion value of each grid point is rounded to 8 bits with 0 and 255 (maximum value) and used in combination with linear interpolation, the conversion accuracy does not deteriorate, but 5 ^In the case of ³ grid points, the conversion accuracy deteriorates significantly. Such deterioration of conversion accuracy occurs when a plurality of conversion values used for interpolation include points that exist in the RGB color space and points that do not exist in the RGB color space. This is because the linear interpolation is performed using the converted value rounded with a value of 0 to 255, and this is because an error occurs between the originally obtained value and the interpolated value. Three-dimensional LU
When the number of grid points of T is sufficiently large, such an error is unlikely to occur, and the error itself is small, so that there are few problems. However, if the number of grid points is reduced in order to reduce the circuit scale, an error is more likely to occur and the error itself becomes large, which is a problem.

In the first embodiment, by storing negative R, G, B (imaginary colors that do not actually exist) or R, G, B exceeding the maximum value as conversion values in the three-dimensional LUT, Improve conversion accuracy by interpolation. For example, the converted value is expanded to 10 bits, and the values from -512 to +511 are three-dimensional LUT.
It is possible to improve the conversion accuracy by storing in the memory.

In the first embodiment, the conversion from the CIE 1976 L ^* a ^* b ^* uniform perceptual color space to the RGB color space is shown, but the reverse RGB color space to CIE 1976 L ^* a ^* b ^* uniform perceptual. This method is not very effective for conversion to the color space. The reason will be described. From RGB color space to CIE 1976 L ^* a ^* b ^*
The dark part of the three-dimensional LUT used for conversion to the uniform perceptual color space needs to be considered in three dimensions, and increasing the number of grid points in the dark part is not efficient. However, CIE 1976 L ^* a ^* b ^*
Since the dark part of the three-dimensional LUT used for conversion from the uniform perceptual color space to the RGB color space need only be considered in the L ^* axis direction, it is possible to reduce the increase in the capacity of the three-dimensional LUT. As described above, the first embodiment can be said to be an effective method in the case of converting a color space in which the lightness axis is separated into another color space.

Example 2. The configuration of the color conversion processing device according to the second embodiment of the present invention is the same as that of FIG. 1, but the signal processing in the interpolation coefficient generation circuit 2 is different.

Next, the operation will be described. Input signal Li
^*, ai^*, bi^*Are each 8 bits. Input signal Li^*The LUT
Type in 20, k, L_k ^*, L_{k + 1} ^*Get. Storage number k and input
Signal ai^*, bi^*Upper 3 bits of each an^*, bn^*3D LU
Input to T1, input signal Li ^*, ai^*, bi^*Unit of 8 points near
Rectangular lattice (k, an^*, bn^*), (k, an^*+ Dn, bn^*), (k, an^*+ Dn, bn^*+ D
n), (k, an^*, bn^*+ Dn), (k + D_k, an^*, bn^*), (k + D_k, an^*+ Dn, b
n^*), (k + D_k, an^*+ Dn, bn^*+ Dn), (k + D_k, an^*, bn^*+ Dn)
Output signal d₀, d₁, d₂, d₃, d_Four, d_Five, d₆, d₇Get. Also, enter
Force signal ai^*, bi^*Lower 5 bits of each a^*, b^*Interpolation coefficient raw
Input to the synthesis circuit 2 and the interpolation coefficient S as shown in FIG.₀, S₁,
S₂, S₃Get.

FIG. 4 is a diagram showing the configuration of the interpolation coefficient generation circuit 2 in the second embodiment. Reference numerals 21 and 22 are bit inversion circuits, and 23, 24, 25 and 26 are multiplication circuits. The multiplication circuits 23, 24, 25, and 26 apply S ₀ , S ₁ , S ₂ , and S ₃ shown in equations (26), (27), (28), and (29) to the inputs a ^* and b ^* . Output. Input a ^* and b ^* are both 5 bits,
Since the outputs S ₀ , S ₁ , S ₂ , S ₃ are 10 bits, the multiplication circuit 2
If 3, 24, 25, 26 are configured by LUT, the total capacity is 40
It becomes k bits. With this capacity, the circuit scale is smaller when four multipliers are used. Therefore, the LUT is reduced by dividing the input signal into an upper signal and a lower signal and multiplying them.

As shown in equations (33) and (34), input
If a ^* and b ^* are divided into upper signals a _H ^* and b _H ^* and lower signals a _L ^* and b _L ^* , S ₂ is expressed by equation (35). a ^* = a _H ^* x 2 ^K + a _L ^* ... (33) b ^* = b _H ^* x 2 ^K + b _L ^* ... (34) S ₂ = a ^* x b ^* = a _H ^* b _H ^* × 2 ^2K + (a _H ^* b _L ^* + a _L ^* b _H ^* ) × 2 ^K + a _L ^* b _L ^* ... (35) Since a ^* and b ^* are 5-bit signals respectively, When K is 3, a ^* and b ^* are divided into upper 2 bits and lower 3 bits.
As a result, the LUT of 3 bits for input and 6 bits for output is 16
Although the number is required, the capacity can be reduced to 6k bits. As is clear from the equation (35), twelve adders are required in total, but the circuit scale is smaller than when four multipliers are used.

FIG. 5 shows a multiplication circuit 2 for realizing the equation (35).
It is a figure which shows the structure of No. 5. In the figure, 27 to 30 are L for outputting the multiplication result of 6 bits for the input 3 bits.
UTs, 31, 32, and 33 are adders, 34 is a 6-bit shift circuit, and 35 is a 3-bit shift circuit. LUT2
By _{^{7,28,29,30, a H * b H *}} , a L * b H *, a H * b L *, a
And calculates the _L ^* b _L ^*. An adder _{^{31, a L * b H *}} + a H * b L * is calculated, and a _H ^* b _H ^* was raised six bits of digits by 6-bit shift circuit 34, a by 3-bit shift circuit 35 _L ^* b _H ^*
+ a _H ^* b _L ^* is carried by 3 bits and these signals are added by the adders 32 and 33 to calculate S ₂ . The multiplication circuits 23, 24, and 26 can also be configured with a similar circuit configuration.

In FIG. 1, the output of the interpolation coefficient generation circuit 2
S ₀ , S ₁ , S ₂ , S ₃ are input to the multipliers 3, 4, 5, 6 and the multipliers 7, 8, 9, 10, respectively, and the outputs of these multipliers are added to the adder circuit 13, respectively. The first interpolation signal ds and the second interpolation signal ds ′ are calculated by inputting to the input terminal 14. Three-dimensional interpolation is performed by interpolating the two interpolation signals on the L ^* axis as shown in Expression (32), and the output signal d is obtained. Interpolation processing for each of R, G, and B is performed by the same calculation method.

Example 3. The configuration of the color conversion processing device according to the third embodiment of the present invention is the same as that of FIG. 1, but the signal processing in the interpolation coefficient generation circuit 2 is different.

Next, the operation will be described. Input signal Li
Each of ^* , ai ^* , bi ^* is 8 bits. Input signal Li ^* is LUT
Input to 20, and obtain k, L _k ^* , L _{k + 1} ^* . The storage number k and the upper 3 bits of each of the input signals ai ^* and bi ^* are an ^* and bn ^*, which are three-dimensional LU
Input signal T1 and output signals d ₀ , d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , d located on the unit rectangular grid of 8 points near the input signal Li ^* , ai ^* , bi ^* ₇
Get. The lower 5 bits of each of the input signals ai ^* and bi ^* are a
Input ^* and b ^* to the interpolation coefficient generation circuit 2 to obtain the interpolation coefficients S ₀ , S ₁ , S ₂ and S ₃ as shown in FIG. Only the interpolation coefficient S ₂ calculated by the equation (28) is obtained from the multiplication circuit 25, and the other interpolation coefficient S ₂ is obtained.
S ₀ , S ₁ , and S ₃ are calculated using S ₂ as shown in equations (36), (37), (38). Since Dn is ²⁵ , the formula (3
6), (37) and (38) can be realized by a combination of an adder and a bit shift circuit. S ₀ ＝ (Dn-a ^* ) × (Dn-b ^* ) ＝ Dn ^2- (a ^* + b ^* ) × Dn + S ₂ …… (36) S ₁ ＝ a ^* × (Dn-b ^* ) ＝ a ^* × Dn-S ₂ …… (37) S ₃ ＝ (Dn-a ^* ) × b ^* ＝ b ^* × Dn-S ₂ …… (38)

FIG. 6 is a diagram showing the configuration of the interpolation coefficient generation circuit 2 in this embodiment. In the figure, 36, 37,
38 is a 5-bit shift circuit, and 39 to 43 are adders. The multiplication circuit 25 calculates the interpolation coefficient S ₂ . a ^* is 5
It is input to the bit shift circuit 36 to obtain an output a ^* × ^25, and an adder 39 subtracts S ₂ from a ^* × ²⁵ to obtain an interpolation coefficient S ₁ . Similarly, the 5-bit shift circuit 37 and the adder 40 obtain the interpolation coefficient S ₃ . Also, the sum of a ^* and b ^* added by the adder 43 is input to the 5-bit shift circuit 38, and (a ^* +
b ^* ) × 2 ⁵ is obtained, 2 ¹⁰ and S ₂ are added by the adder 41, and the adder 42 outputs (a ^* + b ^* ) × 2 ⁵ from the output of this adder 41.
To obtain the interpolation coefficient S ₀ . Compared to the case where four multipliers are used, the interpolation coefficient generation circuit 2 can be realized by a LUT having a total capacity of 1.5 kbits and eight adders by the above-described calculation method, and the circuit scale can be reduced. It will be possible.

In FIG. 1, the output of the interpolation coefficient generation circuit 2
S ₀ , S ₁ , S ₂ , S ₃ are input to the multipliers 3, 4, 5, 6 and the multipliers 7, 8, 9, 10, respectively, and the outputs of these multipliers are added to the adder circuit 13, respectively. The first interpolation signal ds and the second interpolation signal ds ′ are calculated by inputting to the input terminal 14. Three-dimensional interpolation is performed by interpolating the two interpolation signals on the L ^* axis as shown in Expression (32), and the output signal d is obtained. Interpolation processing for each of R, G, and B is performed by the same calculation method.

In the above-described first embodiment, the input signal of m bits is input.
In the case of Li ^* signal, ai ^* signal, and bi ^* signal, the unit plane with 2 ^mn bits on each side of the a ^* signal and b ^* signal for the lower ^mn bits is the axis of the a ^* signal. And b ^* 4 in the axial direction of the signal
Although the areas of the four planes in the case of division are used as the interpolation coefficients, other interpolation coefficients may be used in consideration of the conversion characteristics of the color space before conversion and the color space after conversion.

In the first embodiment, CIE 1976 L ^* a ^* b
^* Conversion from uniform perceptual color space is shown, but CIE 1976 L ^* u ^*
v ^* Any conversion from a color space in which the lightness axis is separated, such as a uniform perceptual color space or Munsell color system, may be used.

In the first embodiment, the number of lattice points of the three-dimensional LUT is 9 points in the a ^* axis and b ^* axis directions and 3 points in the L ^* axis direction is added to 12 points. , L ^{* The} number of grid points added in the direction of the axis may be any number.

Further, the storage means and LUT in each of the above embodiments are ROM (Read Only Memory), RAM (Rand).
It may be composed of a semiconductor element such as an om access memory) or other high-speed storage means.

In each of the above embodiments, the three-dimensional LUT in which the grid points in the achromatic direction in the converted three-dimensional color space are arranged so that the dark part is fine and the middle and high brightness parts are coarse has been described. The same applies to a specific color such as a skin color that emphasizes reproducibility. If the reference white is C light source, CI
E 1976 L ^* a ^* b ^* Achromatic color in the uniform perceptual color space exists on the L ^* axis where a ^* and b ^{* are} almost zero. The same applies to other colors, and it can be said that the particular a ^* and b ^* are different in lightness only on the L ^* axis. Therefore, a ^* , b that indicates a color for which color reproducibility is emphasized
^If the grid points on the L ^* axis of ^* are arranged so that the dark part is fine and the middle and high brightness parts are coarse, the transmission accuracy of the specific color is improved.

[0072]

The present invention converts video information from a color space dependent on one image input / output device into a color space dependent on the other image input / output device, and has the following effects.

According to the first aspect of the present invention, it is possible to realize highly accurate color conversion at real time or at a speed equivalent thereto, and to improve conversion accuracy by linear interpolation, particularly conversion accuracy of dark areas.

According to the second aspect of the invention, it is possible to realize highly accurate color conversion with a small circuit scale in real time or at a speed corresponding thereto, and to improve conversion accuracy by linear interpolation. A three-dimensional LUT in which the grid points in the specific color direction are arranged so that the dark part is fine and the middle and high brightness parts are coarse
Therefore, it is possible to improve the conversion accuracy of the specific color.

For example, when the CIE 1976 L ^* a ^* b ^* uniform perceptual color space is converted to another color space, the conversion value in the skin color direction, which is the most sensitive to human visual characteristics, is converted into the above three-dimensional LUT. By arranging them, it is possible to improve the conversion accuracy with respect to the storage capacity. For example, the number of grid points is 729,
An image simulation was performed using a three-dimensional LUT for forward conversion and a three-dimensional LUT for inverse conversion in which the conversion value is 8 bits and the C light source is the reference light source of the CIE 1976 L ^* a ^* b ^* uniform perceptual color space. . The image used for evaluation is ITE Color Matching
This is an image of a Chart (a girl with carnation) captured on a workstation using a video camera. The evaluation after positive conversion from RGB to ^{L * a * b *, L} * a * b * from RG
The color difference between the processed image inversely converted to B and the original image was used.

The color difference is not in the RGB color space, but in the CIE
1976 L ^* a ^* b ^* Calculated in uniform perceptual color space. Color difference of 8-point interpolation which is the conventional method is 1.24, color difference of 6-point interpolation is 1.34, 5
The color difference for point interpolation was 2.23, the color difference for point interpolation was 1.33, and the color difference without interpolation processing was 27.43. According to the present invention using a three-dimensional LUT for inverse conversion in which a conversion value is added to the dark area, the number of grid points is 972 points, and the conversion value is expanded to 10 bits, the color difference is
It became 1.18, and the conversion accuracy was the best.

Further, assuming that the image which has been subjected to the normal conversion is subjected to the inverse conversion and returned to the original color space as one transmission, the color difference of the 8-point interpolation is 9.94, the color difference of the 6-point interpolation is 10.63, and the transmission of 10 times.
The 5-point interpolation color difference was 10.48, and the 4-point interpolation color difference was 7.76. According to the present invention, the color difference is 10.65, and the color difference is the largest, but the processed image subjected to image simulation by a method other than the present invention has discontinuous gradation, and false contours are generated in the low frequency part of the image. In particular, in the dark area such as the hair portion, the gradation was completely destroyed in the conventional method and became black, but in the present invention, the deterioration of the dark area was suppressed.

Further, simulations were carried out by both the 8-point interpolation and the method according to the present invention (the above conditions) using a ramp function whose luminance continuously changes as shown in FIG. FIG. 15 shows transmission using the 8-point interpolation method.
This is the output value of the processed image when repeated 10 times, and FIG. 16 is the output value of the processed image when transmission is repeated 10 times using the present invention. As is clear from these results, it can be said that the processed image of the present invention maintains gradation continuity. Further, in FIG. 16, since three grid points of the dark part in the L ^* axis direction are added, it can be seen that the deterioration of the gradation of the dark part is improved. Since the dark area has a small signal, even if the error is a little large, it is difficult to appear as a color difference (numerical value), but the difference can be clearly seen in the visual evaluation. The dark area can be further improved by increasing the number of grid points, but the increase in the number of grid points will increase the circuit scale, so it is necessary to make the number appropriate.

According to the third aspect of the present invention, since the three-dimensional LUT in which the grid points in the achromatic color direction are arranged so that the dark portion is fine and the middle and high luminance portions are coarse is used, the hue, lightness, and It is possible to reduce the error in the lightness direction while maintaining the saturation balance. For example, in the case of a black and white image, coloring due to conversion error is reduced.

According to the fourth aspect of the present invention, since the color conversion is performed by the small capacity storage means and the interpolation processing means, for example, the input signal is an 8-bit digital signal, and the storage means stores the upper 3 bits of the input signal. Input and the lower 5 of the input signal
When performing interpolation processing with bits, it is 7 with the conventional interpolation method.
You can reduce the number of multipliers from 2 to 30
It is possible to reduce the circuit scale.

According to the fifth aspect of the present invention, for example, multiplication of a 5-bit signal can be realized by four 384-bit LUTs, two bit shift circuits, and three adders, and four multipliers required for generating an interpolation signal. Since the LUT having a total capacity of 6 k bits, eight bit shift circuits and twelve adders can be realized, the circuit scale can be reduced.

According to the invention of claim 6, the interpolation coefficient generation circuit 2 can be realized by a plurality of LUTs, a plurality of bit shift circuits and a plurality of adders, and the interpolation coefficient generation circuit 2 can have a total capacity of 1.5k.
Since it can be realized by a bit LUT, five bit shift circuits, and eight adders, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a color conversion processing device according to first, second and third embodiments of the present invention.

FIG. 2 is a diagram illustrating a conceptual diagram of an LUT 20 according to the first embodiment.

FIG. 3 is a diagram illustrating an interpolation method in the color conversion processing devices according to the first, second, and third embodiments.

FIG. 4 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 2 according to the first and second embodiments.

FIG. 5 is a block circuit diagram showing a configuration of a multiplication circuit 25 according to the second embodiment of the present invention.

FIG. 6 is a block circuit diagram showing a configuration of an interpolation coefficient generation circuit 2 in Embodiment 3 of the present invention.

FIG. 7 is a block circuit diagram showing a conventional color conversion processing device and conventional color inverse conversion processing device.

FIG. 8 is a diagram showing a conceptual diagram of a three-dimensional LUT 44.

FIG. 9 is a diagram showing a conceptual diagram of a three-dimensional LUT 45.

FIG. 10 is a block circuit diagram showing another conventional color conversion processing device.

FIG. 11 is a diagram showing an interpolation method in a conventional color conversion processing device.

FIG. 12 is a block circuit diagram showing a conventional color inverse conversion processing device.

FIG. 13 is a diagram showing an interpolation method in a conventional color inverse conversion processing device.

FIG. 14 is a diagram showing output values of a ramp function in which RGB are the same and gradation is continuously changed.

FIG. 15 is a diagram showing output values of a processed image obtained by repeating conversion and inverse conversion by the conventional color conversion method 10 times using the ramp function of FIG. 14 as an original image.

16 is a diagram showing output values of a processed image obtained by repeating conversion and inverse conversion 10 times each by the color conversion method of the present invention using the ramp function of FIG. 14 as an original image.

[Explanation of symbols]

1, 44, 45, 46, 57 ... Three-dimensional LUT, 2, 4
7, 58 ... Interpolation coefficient generation circuit, 3 to 12, 48 to 55,
59 to 66 ... Multiplier, 13, 14, 56, 67 ... Adder circuit, 15-18, 31-33, 39-43 ... Adder, 1
9 ... Divider, 20, 27-30 ... LUT, 21, 22 ...
Bit inversion circuit, 23-26 ... Multiplication circuit, 34 ... 6-bit shift circuit, 35 ... 3-bit shift circuit, 36-38
... 5-bit shift circuit.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 28, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

The present invention has been made in order to solve the above-mentioned problems, and performs color conversion with higher accuracy than before in a small circuit scale in real time or at a speed corresponding to it, and particularly, in dark areas. and to obtain a color conversion process equipment which can improve the conversion accuracy.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

[0039]

EXAMPLES Example 1. Figure 1 is a block circuit diagram illustrating a color conversion processing apparatus according to the first embodiment of the present invention. In the figure, 1 is 3
Dimension LUT, 2 is an interpolation coefficient generation circuit, 3 to 12 are multipliers, 13 and 14 are addition circuits, 15 to 18 are adders, 1
Reference numeral 9 is a divider, and 20 is an LUT.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction content]

As shown in equations (33) and (34), input
If a ^* and b ^* are divided into upper signals a _H ^* and b _H ^* and lower signals a _L ^* and b _L ^* , S ₂ is expressed by equation (35). a ^* = a _H ^* x 2 ^K + a _L ^* ... (33) b ^* = b _H ^* x 2 ^K + b _L ^* ... (34) S ₂ = a ^* x b ^* = a _H ^* b _H ^* × 2 ^2K + (a _H ^* b _L ^* + a _L ^* b _H ^* ) × 2 ^K + a _L ^* b _L ^* ... (35) Since a ^* and b ^* are 5-bit signals respectively, When K is 3, a ^* and b ^* are divided into upper 2 bits and lower 3 bits.
As a result, the LUT of 3 bits for input and 6 bits for output is 16
Although the number is required, the capacity can be reduced to 6k bits. As is clear from the equation (35), twelve adders are required in total, but the circuit scale is smaller than when four multipliers are used.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H04N 1/46 9/64 Z G06F 15/68 310 A H04N 1/46 Z

Claims (6)

[Claims] 1. A first three-dimensional color space represented by first, second, and third color signals is converted into a second three-dimensional color space represented by fourth, fifth, and sixth color signals. In the color conversion processing device, the dark part is densely increased and the middle and high brightness parts are coarsely increased.
A first storage means storing the color signal of No. 1, a storage number obtained by inputting the first color signal to the first storage means, and a second
A third color signal is input, and fourth, fifth, and sixth color signals at a plurality of points located on a unit cell in the vicinity of a point in the second three-dimensional color space indicating the input signal are output. 2 storage means, and interpolation coefficient generation means for generating an interpolation coefficient for calculating an interpolation signal from the fourth, fifth, and sixth color signals of the plurality of points,
A color conversion processing device, comprising: interpolation processing means for interpolating the fourth, fifth, and sixth color signals based on the plurality of points of the fourth, fifth, and sixth color signals and the interpolation coefficient. . 2. A first three-dimensional color space represented by first, second, and third color signals is converted into a second three-dimensional color space represented by fourth, fifth, and sixth color signals. In the color conversion processing device, the dark portion of the brightness of the specific color represented by the fourth, fifth, and sixth color signals after the color conversion is dense, and the middle and high luminance portions are the coarsely increased first color signal. The stored first storage means and m (m
Is a natural number) bit, and the first color signal, which is a digital signal, is input to the first storage means to obtain a storage number k (k
Is a natural number) and the second and third color signals, which are m-bit digital signals, are input, and they are located in a unit rectangular grid near a point in the second three-dimensional color space indicating the input signal.
Alternatively, it is assumed that the second storage means for outputting the fourth, fifth, and sixth color signals of eight points and the interpolation coefficient for multiplying the fourth, fifth, and sixth color signals of the eight points are located. It is located in the unit plane lattice of 4 points when the first color signal is stored in the kth position, including the interpolation coefficient generating means for generating and the second and third color signals of m bits. 4th, 5th,
Means for outputting a first interpolated signal obtained by multiplying a sixth color signal by each of the interpolation coefficients and adding it together; and, similarly, including the second and third color signals of m bits, the first color signal A second interpolation signal obtained by multiplying each of the fourth, fifth, and sixth color signals located in the unit plane lattice of four points when the signal is stored in the k + 1th order by multiplying the interpolation coefficient by each other, and adding the result. The means for outputting is multiplied by the first interpolation signal obtained by subtracting the m-bit first color signal from the k + 1th stored first color signal, and the second interpolation signal is multiplied by the m-bit first color signal. It is characterized by comprising interpolation processing means for calculating the fourth, fifth and sixth color signals by multiplying the color signal by subtracting the k-th stored first color signal and adding it. Color conversion processing device. 3. The first color signal, in which the lightness of the achromatic color represented by the fourth, fifth, and sixth color signals after color conversion is increased in the dark portion and coarsely in the middle and high luminance portions, is changed into the first color signal. The color conversion processing device according to claim 2, wherein the color conversion processing device is stored in a storage means. 4. When the first, second and third color signals are digital signals of m bits each, the second and third color signals of lower m−n (n is a natural number m> n) bits. Centered on 1
An interpolation coefficient generation unit is provided which outputs an area of four planes as an interpolation coefficient when a unit plane having sides of 2 ^mn bits is divided into four in the axial direction of the second color signal and the axial direction of the third color signal. The color conversion processing device according to claim 2, wherein 5. An interpolation coefficient generating means for inputting second and third color signals of lower m-n bits and outputting four interpolation coefficients required for calculation of an interpolation signal is composed of four storage means. The color conversion processing device according to claim 4, wherein 6. A storage means for inputting second and third color signals of lower m−n bits and outputting one interpolation coefficient out of four interpolation coefficients required for calculation of an interpolation signal, and a plurality of storage means. 5. The color conversion processing device according to claim 4, further comprising: an interpolation coefficient generating unit configured to add the other three interpolation coefficients from an output signal of the storage unit, the interpolation coefficient generating unit including an adder and a plurality of bit shift circuits. .