JPH08161280A - Interruption mediation system of multiprocessor system - Google Patents

Abstract

PURPOSE: To input an interruption request signal in a CPU where arithmetic processing load is minimum when this interruption request signal is generated. CONSTITUTION: Each MES 5 and 6 of CPU 1 and 2 investigates whether ALU (artlhmelic and logial unit) 3 and 4 are in arithmetic operations or no, and outputs a logical value '0' if the self-ALU is not in operation by the measurement result and the logical value '1' if the self-ALU is in operation to an ARB(arbiter) 10. In the ARB 10, the presence or absence of the interruption signal from an I/O 8 through an IOC(input output controller) 9 is judged, the priority levels for the interruption requests of each CPU 1 and 2 are compared if the interruption requests are received, and an interruption request signal 14 is inputted in the CPU of the higher priority level through a bus 11. Namely, when the priority level of the CPU 1 is higher than the priority level of the CPU 2, the interruption request signal 14 is inputted in the CUP 1, and when the priority level is reversed, the interruption request signal is inputted in the CPU 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt arbitration system for a multiprocessor system which arbitrates which processor should process an interrupt request signal from an input / output device in the multiprocessor system.

[0002]

2. Description of the Related Art Generally, in a real-time system, an interrupt request signal from an input / output device is used as a trigger for processing.

FIG. 4 is a block diagram of a single processor system showing an example of a conventional interrupt processing system.

Referring to FIG. 4, a processor (CPU)
The arithmetic unit (ALU) 44 in 41 is an input device (INE) 4
When the interrupt request signal 45 input from 2 is detected and it is determined that there is the processing request 46, the processing result 46 is calculated and the calculation result 47 is output to the output device (OTE) 43.

FIG. 5 is a block diagram of a multiprocessor system showing another example of the conventional interrupt processing system.

Referring to FIG. 5, the ALU in the CPU 51
55 receives the processing request 58 by the interrupt request signal 57 from the INE 53, and outputs the calculation result 59 to the OTE 54.

If another processing request is issued by the INE 53 while the ALU 55 in the CPU 51 is performing processing, the interrupt request signal 57 is sent to another CP as shown by the broken line.
The number of signals that can be processed per unit time is increased by inputting it to U52 and processing it by the ALU 56 in the CPU 52.

In this case, as a procedure for assigning interrupt arbitration to which CPU the interrupt request signal from the INE 53 is input, in the prior art, the interrupt request signal was sequentially input to each CPU for machine equality.

FIG. 6 is a diagram for explaining the delay of interrupt processing in the conventional multiprocessor system shown in FIG.

The ALU 55 in the CPU 51 and the ALU 56 in the CPU 52 perform different operations.

When the processing requests 61 and 62 occur, each CPU
Interrupt request signals are sequentially input to 51 and 52, and the ALU
55 and 56 perform arithmetic processing.

In this case, even when the processing time for the processing request 61 is longer than the processing time for the processing request 62, the next processing request 63 is input to the CPU 51.
Although the ALU 56 of the CPU 52 has already finished the arithmetic processing and is vacant, the processing start of the processing request 63 is CP.
This is after the ALU 55 of U51 finishes the arithmetic processing of the processing request 61.

[0013]

In this conventional interrupt processing system, the interrupt request signal is sequentially input to each CPU regardless of the operating condition of the ALU in each CPU.
When the next interrupt request signal is input to the CPU that is processing the input interrupt request signal, there is a problem that the processing start is delayed.

Therefore, it is an object of the present invention to input an interrupt request signal to a CPU having a minimum arithmetic processing load when an interrupt request signal is generated, thereby improving the processing efficiency of the entire system and thereby arbitrating interrupts in a multiprocessor system. To provide a method.

[0015]

According to the present invention, in a multiprocessor system configured by bus-coupling a plurality of processors in a real-time system in which an interrupt request signal from an input / output device is used as a trigger to start processing, An interrupt arbitration system for a multiprocessor system is obtained, in which the interrupt request signal is input to the processor with the minimum load to perform processing according to the result from each processor that measures its own load state.

Further, each processor is provided with load measuring means for measuring its own load condition and outputting the result to the outside as a priority level signal for acceptance of the interrupt request signal. When an interrupt occurs, an interrupt arbitration method for a multiprocessor system is provided, which comprises arbitration means for determining a processor to which the interrupt request signal should be input based on the priority level signal from each processor.

[0017]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an interrupt arbitration system for a multiprocessor system according to the present invention.

Referring to FIG. 1, the multiprocessor system of the present embodiment comprises processors (CPU) 1 and 2 connected by a bus 11 and an input / output device (IOE) 7.

CPUs 1 and 2 are arithmetic units (ALU), respectively.
3 and 4, and processes a processing request input from the IOE 7 through the bus 11. The CPUs 1 and 2 have load measuring means (MES) 5 and 6, respectively, measure the operating states of the ALUs 3 and 4, and output the measurement results as priority level signals 12 and 13 for the interrupt request signal from the IOE 7. .

The functions of the MESs 5 and 6 can be incorporated into an operating system (software) for software processing.

The IOE 7 has an input / output unit (I / O) 8, an input / output control unit (IOC) 9, and an arbiter (ARB) 10.

When an interrupt signal is generated in I / O8, IO
C9 inquires the priority level of the priority level signal from each of the CPUs 1 and 2 input to the ARB 9, judges the interrupt request signal 14 from the response, and sends the interrupt request signal 14 to the CP having a high priority level.
Input to U via bus 11.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.

FIG. 2 is a flow chart showing an example of the processing of the load measuring means in FIG. 1, and FIG. 3 is a flow chart showing an example of the arbitration processing in FIG.

The MESs 5 and 6 of the CPUs 1 and 2 are respectively A
It is checked whether or not the LU3 and LU4 are in operation (step S2).
1).

According to the measurement result, if the own ALU is not in operation (NO in S21), the logical value "0" is set (S23), and if it is in operation (YE in S21).
S), the logical value "1" is output to the ARB 9 (S22).

The ARB 10 judges whether or not there is an interrupt request signal from the I / O 8 (S31), and if there is an interrupt request signal, compares the priority levels of the priority level signals 12 and 13 with respect to the interrupt requests of the CPUs 1 and 2. (S32), the interrupt request signal 14 is input to the CPU having the higher priority level through the bus 11.

That is, in S32, when the priority level of CPU1 is higher than the priority level of CPU2 (CPU
1 ≧ CPU2) inputs the interrupt request signal 14 to the CPU1 (S33), and when the priority level is opposite (CPU1 <CP
U2) inputs the interrupt request signal 14 to the CPU 2 (S2)
34).

In this embodiment, when the MES function is incorporated in the operating system, for example, when a plurality of arithmetic functions operate in each processor, the priority level is determined according to the number of arithmetic units waiting for operation. You can

Further, the priority level can be determined according to the urgency of the function of the arithmetic unit operating in each processor.

Although the above-described embodiment exemplifies a multiprocessor system having two processors, the same operation is performed in a multiprocessor system having three or more processors.

[0033]

As described above, according to the present invention, the interrupt request signal from the input / output device is input to the processor with the least load at the time when the interrupt request signal is generated, and the processor is caused to perform the processing. The effect is that the processing efficiency of the multiprocessor system as a whole can be improved.

By incorporating the load measuring function in the operating system, the priority level of the processor can be flexibly set.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an interrupt arbitration method for a multiprocessor system according to the present invention.

FIG. 2 is a flowchart showing an example of processing of load measuring means in FIG.

FIG. 3 is a flowchart showing an example of arbitration processing in FIG.

FIG. 4 is a block diagram of a single processor system showing an example of a conventional interrupt processing system.

FIG. 5 is a block diagram of a multiprocessor system showing another example of a conventional interrupt processing system.

FIG. 6 is a diagram for explaining a delay of interrupt processing in the conventional multiprocessor system shown in FIG.

[Explanation of symbols]

 1, 2, 41, 51, 52 Processor (CPU) 3, 4, 44, 55, 56 Operation Unit (ALU) 5, 6 Load Measuring Means (MES) 7 Input / Output Device (IOE) 8 Input / Output Unit (I / O) 9 Input / output control unit (IOC) 10 Arbiter (ARB) 11 Bus 12, 13 Priority level signal 14, 45, 57 Interrupt request signal 42, 53 Input device (INE) 43, 54 Output device (OTE) 46, 58 , 61, 62, 63 Processing request 47, 59 Operation result

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Onoi, 1-1, Shinurashima-cho, Kanagawa-ku, Yokohama-shi, Kanagawa 1-25, NEC Electric Robot Engineering Co., Ltd.

Claims (2)

[Claims] 1. A multiprocessor system configured by bus-combining a plurality of processors in a real-time system in which an interrupt request signal from an input / output device is used as a trigger to start processing, and each of the processors measures its own load state. An interrupt arbitration method for a multiprocessor system, characterized in that the interrupt request signal is input to a processor with the least load to perform processing. 2. Each of the processors includes load measuring means for measuring its own load state and outputting the result to the outside as a priority level signal for acceptance of the interrupt request signal, wherein the interrupt request signal is provided by the input / output device. 2. An interrupt arbitration system for a multiprocessor system according to claim 1, further comprising arbitration means for determining a processor to which said interrupt request signal should be inputted based on said priority level signal from said each processor when the above occurs.